Sail Model: E-extension Work (RV32E/RV64E)

[jjscheel]

Technical Group

Other

ratification-pkg

RV32E/RV64E

Technical Liaison

Bill McSpadden (bill@riscv.org)

Task Category

SAIL model

Task Sub Category

• gcc
• binutils
• gdb
• intrinsics
• Java
• KVM
• ld
• llvm
• Linux kernel
• QEMU
• Spike

Ratification Target

1Q2023

spec-link

https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view?usp=share_link

Statement of Work (SOW)

Component names:
RISC-V Sail Golden Model

Requirements:
The RISC-V E extension (E is typically understood to mean “Embedded”) is an extension that is beneficial to cores that are optimized to reduce size. The main feature of this extension is the reduction of the register file from 32 registers down to 16.

There are 2 areas that need to be addressed in the model:

1. For opcodes that attempt to use the upper 16 registers, an instruction access fault needs to be generated.
2. For CSR writes, the ordering of the write and the completion of the instruction if there is a fault, must be handled correctly. Currently, the write occurs before the fault.

See github issue, riscv/sail-riscv#523

More information can be found in the RISC-V Unprivileged Specification chapter titled "RV32E and RV64E Base Integer Instruction Sets, Version 2.0" (Ch. 3).

Deliverables:
Accepted PRs for the the following:

• sail-riscv github fork/branch with the implementation
• Build verification test

Acceptance Criteria:

• Accepted PR(s)

Projected timeframe: (best guess date)
2 people for 1 month. 1 person for implementation and 1 person for testing.

SOW Signoffs: (delete those not needed)

• Development partner sign-off
• Golden Model SIG sign-off (if SAIL work)

Waiver

• Freeze
• Ratification

Pull Request Details

No response

[jjscheel]

@billmcspadden-riscv , I built this based upon the information you shared. Please review and comment if I missed something.