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Integrated Matrix Extension Task Group Charter

The Integrated Matrix Extension is an ISA extension that will build on top of the RISC-V Vector extensions and will define new matrix instructions that operate on the existing vector registers (in contrast to the Attached Matrix Extension). Multiple options for storing matrices in vector registers will be explored and evaluated based on a key set of architectural and microarchitectural metrics reflective of real-world implementations ranging from low-end embedded cores to high-end apps cores to HPC cores. One approach will be selected as the basis for the IME extension.

The initial IME extension will focus on matrix instructions and any necessary supporting instructions for AI/ML applications and also for HPC applications. This will include support for currently used AI/ML and HPC data types (e.g. int8, bfloat16, FP32, FP64). Follow-on extensions will add support for newer AI/ML data types (e.g. FP8, 4-bit block FP), and consider adding support for sparse matrices. The initial extension will, though, strive to ensure clear paths for these and other expansions. The initial IME specification will also be developed with consideration of the following in mind:

  • Enabling >2x higher performance than vector-based code alternatives

  • Enabling maximum achievable performance within practical implementation constraints (and enabling a range of efficient design points)

  • Consideration of not just the actual matrix operations, but also necessary supporting operations (e.g. packing/unpacking sub-matrices between memory and vector registers), when evaluating the performance potential of various IME options

  • Binary software portability across implementations with different vector lengths

  • IME instructions will be encoded as 32-bit instructions

  • Minimization of additional architectural (e.g. CSR) state and instructions (following the general philosophy of RISC-V)

  • Consider key low-level AI/ML and HPC benchmark kernels for early evaluation of options

  • Work with the AME TG to identify key higher-level AI/ML and HPC benchmarks, and to explore common software enablement issues

The IME TG will also collaborate with the Unpriv IC, the Apps & Tools Software HC, the Vector and AI/ML SIGs, the Unified Discovery TG, and any future “standard AI/ML performance primitives for IME/AME/RVV” TG