diff --git a/charter.adoc b/charter.adoc
index a64d7ea..4882074 100644
--- a/charter.adoc
+++ b/charter.adoc
@@ -7,6 +7,6 @@ The Performance Event Sampling TG aims to address these limitations by defining
 * An extension that enables precise attribution of samples based on select events (e.g., instruction/uop retirement events) to the instruction that caused the counter overflow, despite implementations where the associated sampling interrupt may skid.  This will provide more directly actionable information to the user, by precisely identifying the instructions that are most often experiencing performance events.
 * An extension that enables sampling of instructions and/or uops, with collection of runtime event occurrences and latencies incurred by the instruction/uop.  Such samples can be filtered based on instruction/uop type, events incurred, or latencies observed, allowing the user to focus on samples of interest.  Further, associated sampling interrupts can be skidless, allowing the user to collect additional sample state (call-stack, register values) reliably.
 
-Each extension will be crafted to be implementation-friendly even for high-performance, out-of-order microarchitectures, aiming to require no additional performance overhead beyond that resulting from the handling of sampling interrupts.  The extensions will be compatible with the H extension, and supoprt RISC-V security objectives.
+Each extension will be crafted to be implementation-friendly even for high-performance, out-of-order microarchitectures, aiming to require no additional performance overhead beyond that resulting from the handling of sampling interrupts.  The extensions will be compatible with the H extension, and support RISC-V security objectives.
 
 The TG will prototype support for the new extensions in Qemu and Linux perf, to demonstrate the usability of the ISA for kernels and tools.