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Preliminary Scalar Efficiency SIG Charter

The Scalar Efficiency SIG aims to explore new unprivileged instructions that broadly reduce code size and/or improve performance.

Scope

The SIG will consider new unprivileged instructions that are:

  1. Scalar (i.e., not SIMD instructions)

  2. Either:

    • Targetable by a compiler code generator, or

    • Part of a compiler builtin/intrinsic

Note
 Compiler builtins cover a wide range of generally useful functions. For example, GCC provides builtins for integer overflow, most of libc/libm, and bit operations. LLVM supports the same plus more. A builtin is also referred to as an intrinsic, though not all instrinsics use the 'builtin' prefix in their name. The LLVM documentation has a complete list of compiler-supported intrinsics.

The SIG will consider instructions spanning multiple processor classes, from limited in-order designs up to wide out-of-order designs.

The SIG will identify target device types, and, for each one, develop metrics to evaluate new instructions by balancing tradeoffs between code size, performance, and implementation costs. Based on results, we expect to spin off multiple Task Groups to define new extensions.

Background

RISC-V lags the competition on code size in many workloads, even when compiled with compressed 16-bit encodings. To address that gap, many RVI members have custom extensions for more efficient instructions (e.g., additional load/store addressing modes). Standardizing combined instructions will benefit vendors with custom instructions by enabling consolidated toolchain support, and will improve key metrics for the ecosystem as a whole.

Example instruction combinations include, but are not limited to:

  • Load/store operations with additional addressing modes

  • Load/store operations operating on multiple input/output registers

  • Conditional branches with immediate operands

  • Macro-operations occurring in string operations (e.g., testing for NUL-octets in a register) and Unicode-processing

  • Bitfield insertion/extraction

  • Checksum-calculation operations for storage and networking

  • Conditional select, mov, aluop

  • Branches with large offsets

  • Instructions to generate large (e.g., 64-bit) immediates

  • …​

Objectives

Objectives include:

  • Standardizing common instructions currently implemented as custom extensions by multiple vendors

  • Identifying additional gaps relative to competitive ISAs and new opportunities that will set RISC-V apart

  • Identifying target markets, and for each defining:

    • Target workloads, algorithms, and/or real-world applications

    • Priority metrics (e.g., code size, performance)

    • Specific inclusion criteria based on use-cases, frequency-of-occurrence, predicted code-size reduction, and/or predicted effect on performance.

  • Define and develop an evaluation methodology for proposed instructions, possibly including:

    • Static binary analysis

    • Compiler prototyping

    • Runtime analysis

  • Coordinating the development of ISA extensions that meet the inclusion criteria through one or more standard or fast-track task groups.

  • Archiving reasons when studied instructions are not advanced to a TG for standardization.

Governance

To fulfill its objectives, the Combined Instruction SIG will report to:

  • Apps and Tools HC

  • Unpriv IC (dotted line)

Leadership

Acting chair: Derek Hower (Qualcomm)