From 4f214d460dcb1b5af43f7611b8773aeec91581c9 Mon Sep 17 00:00:00 2001
From: dhower-qc <134728312+dhower-qc@users.noreply.github.com>
Date: Thu, 5 Sep 2024 12:05:41 -0400
Subject: [PATCH] Create 2024-09-05.adoc

Signed-off-by: dhower-qc <134728312+dhower-qc@users.noreply.github.com>
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+= Scalar Efficiency SIG 8/5/2024
+
+== Attendees
+
+ * Christian Herber (NXP)
+ * Derek Hower (Qualcomm)
+ * David Weaver (Akeana)
+ * Al Martin (Akeana)
+ * Mehul Shah (Rivos)
+ * Ana Pazos (Qualcomm)
+ * Punit Agrawal (Bytedance)
+ * Olaf Bernstein (Individual)
+ * Allen Baum (Esperanto)
+ * Ved Shanbhogue (Rivos)
+ * Greg Favor (Ventana)
+
+== Topics
+
+ * 48-bit instructions. Olaf suggested defining new 32-bit instructions in the 48-bit instruction opcode space.
+ ** Christian pointed out 48-bit space may not be as free as it seems, since it may get used with large immediate instructions
+ ** Derek observed that this would buy at most one extra major opcode int 32-bit space
+ * Allen suggested prefix instructions to extend immediate of following instruction
+ ** Requires extra CSR register that is saved/restored
+ ** May have implementations costs (adds implicit source and dest to following instruction)
+ *** ...unless you can gaurantee neither an exception or interrupt can happen between prefix
+ * Derek pointed out that Qualcomm has released a custom RISC-V microcontroller spec
+ ** Qualcomm will release LLVM implementation for instructions, which SE Sig can use.
+ * Punit will send out results from load/store pair performance on silicon.