Update charter.adoc

Include new wording for compiler restriction

Signed-off-by: dhower-qc <134728312+dhower-qc@users.noreply.github.com>

charter.adoc

@@ -6,7 +6,7 @@ The Scalar Efficiency SIG aims to explore new unprivileged instructions that red
 
  * Scalar (i.e., not SIMD instructions)
  ** Includes floating point instructions. When considered, will coordinate with the FP SIG.
-// * Targetable by a compiler  TODO: Get Krste's opinion based on feedback that this requirement would be too narrowing.
+ * Targetable by a compiler code generator or builtin function
 
 The SIG will consider instructions spanning multiple processor classes, from limited in-order designs up to wide out-of-order designs.
 
@@ -15,7 +15,7 @@ Based on results, we expect to spin off multiple Task Groups to define new exten
 
 == Background
 
-RISC-V lacks common instructions present in competitive ISAs, and as such lags the competition on code size in many workloads.
+RISC-V lacks common instructions present in competitive ISAs, and as such lags the competition on code size in many workloads even with compressed 16-bit encodings.
 To address that gap, many RVI members have custom extensions for combined instructions (_e.g._, additional load/store addressing modes).
 Standardizing combined instructions will benefit vendors with custom instructions by enabling consolidated toolchain support, and will improve key metrics for the ecosystem as a whole.