From cfb469ff733b24b70dd647f861ed437d5d432ef8 Mon Sep 17 00:00:00 2001
From: liweiwei <liweiwei@iscas.ac.cn>
Date: Sat, 18 Dec 2021 12:44:21 +0800
Subject: [PATCH] add support for cbo.zero in cmo extension

---
 .../device/rv32i_m/cmo/Makefile.include       |  41 +++
 .../device/rv64i_m/cmo/Makefile.include       |  42 ++++
 riscv-test-suite/env/arch_test.h              |   6 +
 riscv-test-suite/rv32i_m/cmo/Makefile         |   3 +
 riscv-test-suite/rv32i_m/cmo/Makefrag         |  35 +++
 .../references/cbo.zero-01.reference_output   |  64 +++++
 .../rv32i_m/cmo/src/cbo.zero-01.S             | 235 ++++++++++++++++++
 riscv-test-suite/rv64i_m/cmo/Makefile         |   3 +
 riscv-test-suite/rv64i_m/cmo/Makefrag         |  35 +++
 .../references/cbo.zero-01.reference_output   | 124 +++++++++
 .../rv64i_m/cmo/src/cbo.zero-01.S             | 235 ++++++++++++++++++
 11 files changed, 823 insertions(+)
 create mode 100644 riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include
 create mode 100644 riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include
 create mode 100644 riscv-test-suite/rv32i_m/cmo/Makefile
 create mode 100644 riscv-test-suite/rv32i_m/cmo/Makefrag
 create mode 100644 riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output
 create mode 100644 riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S
 create mode 100644 riscv-test-suite/rv64i_m/cmo/Makefile
 create mode 100644 riscv-test-suite/rv64i_m/cmo/Makefrag
 create mode 100644 riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output
 create mode 100644 riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S

diff --git a/riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include b/riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include
new file mode 100644
index 000000000..1d9c643e9
--- /dev/null
+++ b/riscv-target/sail-riscv-c/device/rv32i_m/cmo/Makefile.include
@@ -0,0 +1,41 @@
+TARGET_SIM   ?= riscv_sim_RV32 -V
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_CMD=\
+    $(TARGET_SIM) $(TARGET_FLAGS) -B 8\
+        --test-signature=$(*).signature.output \
+        $(<)
+
+RISCV_PREFIX   ?= riscv32-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include b/riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include
new file mode 100644
index 000000000..93ffce3fc
--- /dev/null
+++ b/riscv-target/sail-riscv-c/device/rv64i_m/cmo/Makefile.include
@@ -0,0 +1,42 @@
+TARGET_SIM   ?= riscv_sim_RV64 -V
+TARGET_FLAGS ?= $(RISCV_TARGET_FLAGS)
+ifeq ($(shell command -v $(TARGET_SIM) 2> /dev/null),)
+    $(error Target simulator executable '$(TARGET_SIM)` not found)
+endif
+
+RUN_CMD=\
+    $(TARGET_SIM) $(TARGET_FLAGS) -B 16\
+        --test-signature=$(*).signature.output \
+        $(<)
+
+RISCV_PREFIX   ?= riscv64-unknown-elf-
+RISCV_GCC      ?= $(RISCV_PREFIX)gcc
+RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
+RISCV_GCC_OPTS ?= -g -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RVTEST_DEFINES)
+
+COMPILE_CMD = $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+							-I$(ROOTDIR)/riscv-test-suite/env/ \
+							-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+							-T$(TARGETDIR)/$(RISCV_TARGET)/link.ld \
+							$$(<) -o $$@ 
+OBJ_CMD = $$(RISCV_OBJDUMP) $$@ -D > $$@.objdump; \
+					$$(RISCV_OBJDUMP) $$@ --source > $$@.debug
+
+
+
+COMPILE_TARGET=\
+				$(COMPILE_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m$$(RISCV_GCC) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ; \
+				$(OBJ_CMD); \
+        if [ $$$$? -ne 0 ] ; \
+                then \
+                echo "\e[31m $$(RISCV_OBJDUMP) failed for target $$(@) \e[39m" ; \
+                exit 1 ; \
+                fi ;
+
+RUN_TARGET=\
+	$(RUN_CMD) 
diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
index ab255fca1..4dfc48aa0 100644
--- a/riscv-test-suite/env/arch_test.h
+++ b/riscv-test-suite/env/arch_test.h
@@ -781,6 +781,12 @@ inst rs2, imm_val(rs1)                                                      ;\
 nop                                                                         ;\
 nop                                                                         
 
+#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val,offset)   ;\
+addi rs1,swreg,offset*2+imm_val                                                     ;\
+inst rs1                                                      ;\
+nop                                                                         ;\
+nop     
+
 #define TEST_LOAD(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj)   ;\
 LA(rs1,rvtest_data+(index*4)+adj-imm_val)                                      ;\
 inst destreg, imm_val(rs1)                                                   ;\
diff --git a/riscv-test-suite/rv32i_m/cmo/Makefile b/riscv-test-suite/rv32i_m/cmo/Makefile
new file mode 100644
index 000000000..74d788175
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/cmo/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv32i -mabi=ilp32 -DXLEN=$(XLEN)))
diff --git a/riscv-test-suite/rv32i_m/cmo/Makefrag b/riscv-test-suite/rv32i_m/cmo/Makefrag
new file mode 100644
index 000000000..ace9351fc
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/cmo/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV32I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV32I architectural tests
+
+rv32i_sc_tests = \
+  cbo.zero-01
+
+rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
+
+target_tests += $(rv32i_tests)
diff --git a/riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output b/riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output
new file mode 100644
index 000000000..6b0ece1a3
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/cmo/references/cbo.zero-01.reference_output
@@ -0,0 +1,64 @@
+00000000
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diff --git a/riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S b/riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S
new file mode 100644
index 000000000..985337086
--- /dev/null
+++ b/riscv-test-suite/rv32i_m/cmo/src/cbo.zero-01.S
@@ -0,0 +1,235 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.5.9
+// timestamp : Sat Dec 18 03:44:49 2021 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /workspace/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /workspace/riscv-ctg/sample_cgfs/rv32i_cbo.cgf \
+ \
+//                  -- xlen 32  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the cbo.zero instruction of the RISC-V I extension for the cbo.zero covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero)
+
+RVTEST_SIGBASE(x6,signature_x6_1)
+
+inst_0:
+// rs1==x11, imm_val == 0x2 
+// opcode: cbo.zero ; op1:x11; adj:0x2
+TEST_CBO_ZERO(x6,x11,cbo.zero,0x2,0)
+
+inst_1:
+// rs1==x16, imm_val == 0x3 
+// opcode: cbo.zero ; op1:x16; adj:0x3
+TEST_CBO_ZERO(x6,x16,cbo.zero,0x3,4)
+
+inst_2:
+// rs1==x2, imm_val == 0x4 
+// opcode: cbo.zero ; op1:x2; adj:0x4
+TEST_CBO_ZERO(x6,x2,cbo.zero,0x4,8)
+
+inst_3:
+// rs1==x15, imm_val == 0x5 
+// opcode: cbo.zero ; op1:x15; adj:0x5
+TEST_CBO_ZERO(x6,x15,cbo.zero,0x5,12)
+
+inst_4:
+// rs1==x20, imm_val == 0x0 
+// opcode: cbo.zero ; op1:x20; adj:0x0
+TEST_CBO_ZERO(x6,x20,cbo.zero,0x0,16)
+
+inst_5:
+// rs1==x27, imm_val == 0x7 
+// opcode: cbo.zero ; op1:x27; adj:0x7
+TEST_CBO_ZERO(x6,x27,cbo.zero,0x7,20)
+
+inst_6:
+// rs1==x29, imm_val == 0x1 
+// opcode: cbo.zero ; op1:x29; adj:0x1
+TEST_CBO_ZERO(x6,x29,cbo.zero,0x1,24)
+
+inst_7:
+// rs1==x3, imm_val == 0x6 
+// opcode: cbo.zero ; op1:x3; adj:0x6
+TEST_CBO_ZERO(x6,x3,cbo.zero,0x6,28)
+
+inst_8:
+// rs1==x1, 
+// opcode: cbo.zero ; op1:x1; adj:0x0
+TEST_CBO_ZERO(x6,x1,cbo.zero,0x0,32)
+
+inst_9:
+// rs1==x22, 
+// opcode: cbo.zero ; op1:x22; adj:0x0
+TEST_CBO_ZERO(x6,x22,cbo.zero,0x0,36)
+
+inst_10:
+// rs1==x13, 
+// opcode: cbo.zero ; op1:x13; adj:0x0
+TEST_CBO_ZERO(x6,x13,cbo.zero,0x0,40)
+
+inst_11:
+// rs1==x10, 
+// opcode: cbo.zero ; op1:x10; adj:0x0
+TEST_CBO_ZERO(x6,x10,cbo.zero,0x0,44)
+
+inst_12:
+// rs1==x7, 
+// opcode: cbo.zero ; op1:x7; adj:0x0
+TEST_CBO_ZERO(x6,x7,cbo.zero,0x0,48)
+
+inst_13:
+// rs1==x21, 
+// opcode: cbo.zero ; op1:x21; adj:0x0
+TEST_CBO_ZERO(x6,x21,cbo.zero,0x0,52)
+
+inst_14:
+// rs1==x28, 
+// opcode: cbo.zero ; op1:x28; adj:0x0
+TEST_CBO_ZERO(x6,x28,cbo.zero,0x0,56)
+
+inst_15:
+// rs1==x26, 
+// opcode: cbo.zero ; op1:x26; adj:0x0
+TEST_CBO_ZERO(x6,x26,cbo.zero,0x0,60)
+
+inst_16:
+// rs1==x30, 
+// opcode: cbo.zero ; op1:x30; adj:0x0
+TEST_CBO_ZERO(x6,x30,cbo.zero,0x0,64)
+
+inst_17:
+// rs1==x14, 
+// opcode: cbo.zero ; op1:x14; adj:0x0
+TEST_CBO_ZERO(x6,x14,cbo.zero,0x0,68)
+
+inst_18:
+// rs1==x8, 
+// opcode: cbo.zero ; op1:x8; adj:0x0
+TEST_CBO_ZERO(x6,x8,cbo.zero,0x0,72)
+
+inst_19:
+// rs1==x17, 
+// opcode: cbo.zero ; op1:x17; adj:0x0
+TEST_CBO_ZERO(x6,x17,cbo.zero,0x0,76)
+
+inst_20:
+// rs1==x5, 
+// opcode: cbo.zero ; op1:x5; adj:0x0
+TEST_CBO_ZERO(x6,x5,cbo.zero,0x0,80)
+
+inst_21:
+// rs1==x25, 
+// opcode: cbo.zero ; op1:x25; adj:0x0
+TEST_CBO_ZERO(x6,x25,cbo.zero,0x0,84)
+
+inst_22:
+// rs1==x18, 
+// opcode: cbo.zero ; op1:x18; adj:0x0
+TEST_CBO_ZERO(x6,x18,cbo.zero,0x0,88)
+
+inst_23:
+// rs1==x31, 
+// opcode: cbo.zero ; op1:x31; adj:0x0
+TEST_CBO_ZERO(x6,x31,cbo.zero,0x0,92)
+
+inst_24:
+// rs1==x23, 
+// opcode: cbo.zero ; op1:x23; adj:0x0
+TEST_CBO_ZERO(x6,x23,cbo.zero,0x0,96)
+
+inst_25:
+// rs1==x4, 
+// opcode: cbo.zero ; op1:x4; adj:0x0
+TEST_CBO_ZERO(x6,x4,cbo.zero,0x0,100)
+
+inst_26:
+// rs1==x9, 
+// opcode: cbo.zero ; op1:x9; adj:0x0
+TEST_CBO_ZERO(x6,x9,cbo.zero,0x0,104)
+
+inst_27:
+// rs1==x19, 
+// opcode: cbo.zero ; op1:x19; adj:0x0
+TEST_CBO_ZERO(x6,x19,cbo.zero,0x0,108)
+RVTEST_SIGBASE(x1,signature_x1_0)
+
+inst_28:
+// rs1==x12, 
+// opcode: cbo.zero ; op1:x12; adj:0x0
+TEST_CBO_ZERO(x1,x12,cbo.zero,0x0,0)
+
+inst_29:
+// rs1==x6, 
+// opcode: cbo.zero ; op1:x6; adj:0x0
+TEST_CBO_ZERO(x1,x6,cbo.zero,0x0,4)
+
+inst_30:
+// rs1==x24, 
+// opcode: cbo.zero ; op1:x24; adj:0x0
+TEST_CBO_ZERO(x1,x24,cbo.zero,0x0,8)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x6_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x6_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/riscv-test-suite/rv64i_m/cmo/Makefile b/riscv-test-suite/rv64i_m/cmo/Makefile
new file mode 100644
index 000000000..18dc245c8
--- /dev/null
+++ b/riscv-test-suite/rv64i_m/cmo/Makefile
@@ -0,0 +1,3 @@
+include ../../Makefile.include
+
+$(eval $(call compile_template,-march=rv64i -mabi=lp64 -DXLEN=$(XLEN)))
diff --git a/riscv-test-suite/rv64i_m/cmo/Makefrag b/riscv-test-suite/rv64i_m/cmo/Makefrag
new file mode 100644
index 000000000..36bf7904f
--- /dev/null
+++ b/riscv-test-suite/rv64i_m/cmo/Makefrag
@@ -0,0 +1,35 @@
+# RISC-V Architecture Test RV64I Makefrag
+#
+# Copyright (c) 2017, Codasip Ltd.
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#      * Redistributions of source code must retain the above copyright
+#        notice, this list of conditions and the following disclaimer.
+#      * Redistributions in binary form must reproduce the above copyright
+#        notice, this list of conditions and the following disclaimer in the
+#        documentation and/or other materials provided with the distribution.
+#      * Neither the name of the Codasip Ltd. nor the
+#        names of its contributors may be used to endorse or promote products
+#        derived from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
+# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Description: Makefrag for RV64I architectural tests
+
+rv64i_sc_tests = \
+  cbo.zero-01
+
+rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests))
+
+target_tests += $(rv64i_tests)
diff --git a/riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output b/riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output
new file mode 100644
index 000000000..9d5ec03a9
--- /dev/null
+++ b/riscv-test-suite/rv64i_m/cmo/references/cbo.zero-01.reference_output
@@ -0,0 +1,124 @@
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diff --git a/riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S b/riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S
new file mode 100644
index 000000000..fdf06959b
--- /dev/null
+++ b/riscv-test-suite/rv64i_m/cmo/src/cbo.zero-01.S
@@ -0,0 +1,235 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.5.9
+// timestamp : Sat Dec 18 03:46:46 2021 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /workspace/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /workspace/riscv-ctg/sample_cgfs/rv64i_cbo.cgf \
+ \
+//                  -- xlen 64  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the cbo.zero instruction of the RISC-V I extension for the cbo.zero covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero)
+
+RVTEST_SIGBASE(x13,signature_x13_1)
+
+inst_0:
+// rs1==x23, imm_val == 0x4 
+// opcode: cbo.zero ; op1:x23; adj:0x4
+TEST_CBO_ZERO(x13,x23,cbo.zero,0x4,0)
+
+inst_1:
+// rs1==x27, imm_val == 0x5 
+// opcode: cbo.zero ; op1:x27; adj:0x5
+TEST_CBO_ZERO(x13,x27,cbo.zero,0x5,8)
+
+inst_2:
+// rs1==x22, imm_val == 0x6 
+// opcode: cbo.zero ; op1:x22; adj:0x6
+TEST_CBO_ZERO(x13,x22,cbo.zero,0x6,16)
+
+inst_3:
+// rs1==x10, imm_val == 0x9 
+// opcode: cbo.zero ; op1:x10; adj:0x9
+TEST_CBO_ZERO(x13,x10,cbo.zero,0x9,24)
+
+inst_4:
+// rs1==x21, imm_val == 0x7 
+// opcode: cbo.zero ; op1:x21; adj:0x7
+TEST_CBO_ZERO(x13,x21,cbo.zero,0x7,32)
+
+inst_5:
+// rs1==x9, imm_val == 0xa 
+// opcode: cbo.zero ; op1:x9; adj:0xa
+TEST_CBO_ZERO(x13,x9,cbo.zero,0xa,40)
+
+inst_6:
+// rs1==x31, imm_val == 0x1 
+// opcode: cbo.zero ; op1:x31; adj:0x1
+TEST_CBO_ZERO(x13,x31,cbo.zero,0x1,48)
+
+inst_7:
+// rs1==x16, imm_val == 0x8 
+// opcode: cbo.zero ; op1:x16; adj:0x8
+TEST_CBO_ZERO(x13,x16,cbo.zero,0x8,56)
+
+inst_8:
+// rs1==x4, imm_val == 0xe 
+// opcode: cbo.zero ; op1:x4; adj:0xe
+TEST_CBO_ZERO(x13,x4,cbo.zero,0xe,64)
+
+inst_9:
+// rs1==x15, imm_val == 0x2 
+// opcode: cbo.zero ; op1:x15; adj:0x2
+TEST_CBO_ZERO(x13,x15,cbo.zero,0x2,72)
+
+inst_10:
+// rs1==x25, imm_val == 0x3 
+// opcode: cbo.zero ; op1:x25; adj:0x3
+TEST_CBO_ZERO(x13,x25,cbo.zero,0x3,80)
+
+inst_11:
+// rs1==x18, imm_val == 0xd 
+// opcode: cbo.zero ; op1:x18; adj:0xd
+TEST_CBO_ZERO(x13,x18,cbo.zero,0xd,88)
+
+inst_12:
+// rs1==x2, imm_val == 0xb 
+// opcode: cbo.zero ; op1:x2; adj:0xb
+TEST_CBO_ZERO(x13,x2,cbo.zero,0xb,96)
+
+inst_13:
+// rs1==x8, imm_val == 0xc 
+// opcode: cbo.zero ; op1:x8; adj:0xc
+TEST_CBO_ZERO(x13,x8,cbo.zero,0xc,104)
+
+inst_14:
+// rs1==x14, 
+// opcode: cbo.zero ; op1:x14; adj:0x0
+TEST_CBO_ZERO(x13,x14,cbo.zero,0x0,112)
+
+inst_15:
+// rs1==x1, 
+// opcode: cbo.zero ; op1:x1; adj:0x0
+TEST_CBO_ZERO(x13,x1,cbo.zero,0x0,120)
+
+inst_16:
+// rs1==x11, 
+// opcode: cbo.zero ; op1:x11; adj:0x0
+TEST_CBO_ZERO(x13,x11,cbo.zero,0x0,128)
+
+inst_17:
+// rs1==x19, 
+// opcode: cbo.zero ; op1:x19; adj:0x0
+TEST_CBO_ZERO(x13,x19,cbo.zero,0x0,136)
+
+inst_18:
+// rs1==x12, 
+// opcode: cbo.zero ; op1:x12; adj:0x0
+TEST_CBO_ZERO(x13,x12,cbo.zero,0x0,144)
+
+inst_19:
+// rs1==x7, 
+// opcode: cbo.zero ; op1:x7; adj:0x0
+TEST_CBO_ZERO(x13,x7,cbo.zero,0x0,152)
+
+inst_20:
+// rs1==x17, 
+// opcode: cbo.zero ; op1:x17; adj:0x0
+TEST_CBO_ZERO(x13,x17,cbo.zero,0x0,160)
+
+inst_21:
+// rs1==x6, 
+// opcode: cbo.zero ; op1:x6; adj:0x0
+TEST_CBO_ZERO(x13,x6,cbo.zero,0x0,168)
+
+inst_22:
+// rs1==x24, 
+// opcode: cbo.zero ; op1:x24; adj:0x0
+TEST_CBO_ZERO(x13,x24,cbo.zero,0x0,176)
+
+inst_23:
+// rs1==x5, 
+// opcode: cbo.zero ; op1:x5; adj:0x0
+TEST_CBO_ZERO(x13,x5,cbo.zero,0x0,184)
+
+inst_24:
+// rs1==x20, 
+// opcode: cbo.zero ; op1:x20; adj:0x0
+TEST_CBO_ZERO(x13,x20,cbo.zero,0x0,192)
+
+inst_25:
+// rs1==x28, 
+// opcode: cbo.zero ; op1:x28; adj:0x0
+TEST_CBO_ZERO(x13,x28,cbo.zero,0x0,200)
+
+inst_26:
+// rs1==x30, 
+// opcode: cbo.zero ; op1:x30; adj:0x0
+TEST_CBO_ZERO(x13,x30,cbo.zero,0x0,208)
+
+inst_27:
+// rs1==x3, 
+// opcode: cbo.zero ; op1:x3; adj:0x0
+TEST_CBO_ZERO(x13,x3,cbo.zero,0x0,216)
+RVTEST_SIGBASE(x1,signature_x1_0)
+
+inst_28:
+// rs1==x13, 
+// opcode: cbo.zero ; op1:x13; adj:0x0
+TEST_CBO_ZERO(x1,x13,cbo.zero,0x0,0)
+
+inst_29:
+// rs1==x26, 
+// opcode: cbo.zero ; op1:x26; adj:0x0
+TEST_CBO_ZERO(x1,x26,cbo.zero,0x0,8)
+
+inst_30:
+// rs1==x29, 
+// opcode: cbo.zero ; op1:x29; adj:0x0
+TEST_CBO_ZERO(x1,x29,cbo.zero,0x0,16)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+
+
+signature_x13_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
+
+
+signature_x13_1:
+    .fill 56*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 6*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END