diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index d5e9fb7e4..580f2a642 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -135,7 +135,7 @@ jobs: - name: Config and run riscof for RV${{ matrix.xlen }} run: | cd riscof-plugins/rv${{ matrix.xlen }} - riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/ --env ../../riscv-test-suite/env + riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m --env ../../riscv-test-suite/env #Check the existance of the riscof work folder, and add the PATH to environment variable - name: Check size and determine upload path @@ -147,8 +147,8 @@ jobs: if [ -d "$work_folder" ]; then folder_size=$(du -sm "$work_folder" | cut -f1) echo "Folder size: ${folder_size} MB" - if [ "$folder_size" -gt 1000 ]; then - echo "Size exceeds 1 GB. Checking if report exists." + if [ "$folder_size" -gt 100000 ]; then + echo "Size exceeds 10 GB. Checking if report exists." if [ -f "$report_file" ]; then echo "Uploading RISCOF generated report only." echo "upload_path=$report_file" >> $GITHUB_ENV @@ -173,4 +173,4 @@ jobs: name: riscof-artifact-rv${{ matrix.xlen }} path: ${{ env.upload_path }} compression-level: 6 - overwrite: true \ No newline at end of file + overwrite: true diff --git a/coverage/header_file.yaml b/coverage/header_file.yaml index b7386d8f0..9090c41c0 100644 --- a/coverage/header_file.yaml +++ b/coverage/header_file.yaml @@ -67,7 +67,7 @@ common: SATP64_ASID: 0x0FFFF00000000000 SATP64_PPN: 0x00000FFFFFFFFFFF SATP_MODE_OFF: 0 - SATP_MODE_SV32: 1 + SATP_MODE_SV32: 0x1 SATP_MODE_SV39: 8 SATP_MODE_SV48: 9 SATP_MODE_SV57: 10 @@ -932,4 +932,17 @@ PMP_helper_Coverpoints: TOR_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2)) NA4_REGION_ADDRESS_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2)) NA4_PRIORITY_REGION_MATCH: (rs1_val + imm_val == (pmpaddr3 << 2)) - NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2)) \ No newline at end of file + NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2)) + +SV32_MACROS: + LEVEL_1_JUMP_SIZE: (0x400000 - 4) + LEVEL_0_JUMP_SIZE: (0x1000-4) + read: "RWX" + writ: "rx" + va_data_sv32: (0x91400000) + +PMM_MACROS: + PMM_MASK: 0x300000000 + PMM_MASK_SV57: 0x200000000 + PMM_MASK_SV48: 0x300000000 + PMM_MASK_DISABLED: 0x000000000 \ No newline at end of file diff --git a/coverage/rv32_pmp.cgf b/coverage/pmp/rv32_pmp.cgf similarity index 100% rename from coverage/rv32_pmp.cgf rename to coverage/pmp/rv32_pmp.cgf diff --git a/coverage/rv64_pmp.cgf b/coverage/pmp/rv64_pmp.cgf similarity index 100% rename from coverage/rv64_pmp.cgf rename to coverage/pmp/rv64_pmp.cgf diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf new file mode 100644 index 000000000..f75c8f069 --- /dev/null +++ b/coverage/sv32/rv32_vm_sv32.cgf @@ -0,0 +1,364 @@ +#If A and D are not set, then hardware will update it atomically with the access and no faults! +a_and_d_bit_hart_upd: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def HARDWARE_UPDATE_A_D=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw0cont) == 1': 0 + #Faults check at LEVEL 1 and LEVEL 0 + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw0cont) == 1 and len_dptw == 2': 0 + +#If A and D are not set, then hardware will NOT update it and we will get a respective fault ! +a_and_d_bit_soft_upd: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def HARDWARE_UPDATE_A_D=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw0cont) == 1': 0 + #Faults check at LEVEL 1 + #Successful Accesses Cases + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX"}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + #Load, Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop({"aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}': 0 + #Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("AdRWX", dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + #Fetch Page Faults + 'mode == "M" and get_pte_prop({"aDRWX", "adRWX"}, iptw1cont) == 1 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Faults check at LEVEL 0 + #Successful Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AdRWX", "ADRWX"}, dptw0cont) == 1 and len_dptw == 2': 0 + #Load, Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"aDRWX", "adRWX"}, dptw0cont) == 1 and mcause == {15, 13}': 0 + #Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("AdRWX", dptw0cont) == 1 and mcause == 15': 0 + #Fetch Page Faults + 'mode == "M" and get_pte_prop("rwx", iptw1cont) == 1 and get_pte_prop({"aDRWX", "adRWX"}, iptw0cont) == 1 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#Check that when PA has no PMP Permissions, it should give Load, Store and Fetch access Faults. +pmp_check_pa: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + 'mode == {"S", "U"} and ((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + 'mode == {"S", "U"} and (pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_TOR_MODE}': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop({"AuDRWX", "AUDRWX"}{[$1]}, dptw1cont) == 1 and dptw0cont == None': 0 #Level 1 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AuDRWX", "AUDRWX"}{[$1]}, dptw0cont) == 1': 0 #Level 0 + # Fault Checks: + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$2]}': 0 + 'mode == "M" and mnemonic == "jal" and mcause == ${CAUSE_FETCH_ACCESS}': 0 + +#Check that when PA has no PMP Permissions, it should give Load, Store and Fetch access Faults. +pmp_check_pte: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + 'mode == {"S", "U"} and ((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + 'mode == {"S", "U"} and ((pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT}) == ${PMPCFG_NA4_MODE}': 0 + val_comb: + #Note: No way to check the PTW since we will get the access fault before we are able to check the PTW, therefore, no coverpoints! + #For this case, the only way to verify that the Virtual Memory is enabled is by checking the satp register. + # Fault Checks: + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$2]}': 0 + 'mode == "M" and mnemonic == "jal" and mcause == ${CAUSE_FETCH_ACCESS}': 0 + +#if the Valid bit is not set, then there should be load, store, fetch page fault +invalid_pte: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop("RWXv", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXv", dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("RWXv", dptw1cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXv", dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#Test Section (PA of our test VA) is misaligned -> We will get a Load, Store, Fetch Page Fault +misaligned_superpage: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 #Make sure we get a page table walk level 1 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +# If MVPV bit is set, then do page table walk in machine mode for loads and stores. +MPRV_bit: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == "M" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #check mstatus has: case1: MPP& U in MPP and case2: MPP& S in MPP + mstatus == {0x00020000, 0x00020800}: 0 + val_comb: + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw0cont) == 1 and len_dptw == 2': 0 + + +# If MXR bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault +MXR_bit: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + '(mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop("rwX", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwX", dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("rwX", dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("rwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwX", dptw0cont) == 1 and mcause == 15': 0 + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwX", dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 + +#If a PTE at Level 0 has no RWX permissions i.e., similar to non leaf pte then give a load, store, fetch page fault +nonleaf_pte_level0: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwx", dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwx", dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#If reserved PTE permissions are chosen, then get a load, store and fetch page fault +reserved_rwx_pte_perm: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop({"rWX", "rWx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"rWX", "rWx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop({"rWX", "rWx"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"rWX", "rWx"}, dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#If SUM bit is set, then User mode pages can be accessed in the Supervisor mode. +U_bit_sum_set_in_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + '(mstatus & ${MSTATUS_SUM}) == ${MSTATUS_SUM}': 0 + val_comb: + 'mode == "S" and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "S" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw0cont) == 1': 0 + #Fault Check + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UrwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop({"URwX", "URwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("UrwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URwX", "URwx"}, dptw0cont) == 1 and mcause == 15': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#If SUM bit is NOT set, then User mode pages can NOT be accessed in the Supervisor mode, get a fault. +U_bit_no_sum_set_in_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + '(mstatus & ${MSTATUS_SUM}) != ${MSTATUS_SUM}': 0 + val_comb: + 'mode == "S" and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "S" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw0cont) == 1': 0 + #Fault Check + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop({"UrwX", "URwX", "URwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"UrwX", "URwX", "URwx"}, dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#If U bit is set in U mode, then page should be accessed successfully. +U_bit_set_in_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == "U" and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "U" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("UrwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "U" and mnemonic == "sw" and get_pte_prop({"URwX", "URwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("UrwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "U" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URwX", "URwx"}, dptw0cont) == 1 and mcause == 15': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#If U bit is NOT set in U mode, then we will get load, store and fetch page faults. +U_bit_unset_in_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == "U" and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "U" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#If U bit is NOT set in S mode, then page should be accessed successfully. +U_bit_unset_in_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == "S" and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "S" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("urwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop({"uRwX", "uRwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("urwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRwX", "uRwx"}, dptw0cont) == 1 and mcause == 15': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#Access satp register in all three M, S, U modes and expect illegal instruction expection in U Mode. +satp_access_all_modes: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{csrrc, csrrs, csrrw}": 0 + csr_comb: + #Make sure we have some value in case of satp access in M, S modes + 'mode == "M" and mnemonic == "csrrw" and satp != 0': 0 + 'mode == "M" and mnemonic == "csrrs" and satp != 0': 0 + 'mode == "M" and mnemonic == "csrrc" and satp != 0': 0 + 'mode == "S" and mnemonic == "csrrw" and satp != 0': 0 + 'mode == "S" and mnemonic == "csrrs" and satp != 0': 0 + 'mode == "S" and mnemonic == "csrrc" and satp != 0': 0 + #Make sure we have illegal instruction fault for satp access in U mode + 'mode == "U" and mnemonic == "csrrw" and satp != 0 and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + 'mode == "U" and mnemonic == "csrrs" and satp != 0 and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + 'mode == "U" and mnemonic == "csrrc" and satp != 0 and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + #check all ones + 'mode == "M" and mnemonic == "csrrw" and satp == 0x3FFFFF': 0 + #check walking ones on the PPN Width + 'mode == "M" and mnemonic == "csrrw" and satp == 1 << {0 ... 21}': 0 + +#When mstatus TVM bit is set, accessing satp and sfence.vma in S-Mode should raise illegal instruction fault. +mstatus_tvm: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + csrrw: 0 + csr_comb: + #Make sure we have some value in case of satp access in M mode + 'mode == "M" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and satp != 0': 0 + #Make sure we have illegal instruction fault for satp access in S mode + 'mode == "S" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + +#If reserved PTE permissions bits (RSW) are set, then the Page table walk should give no RSW set in return +reserved_rsw_pte_perm: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrw, lw}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop("RWXAD", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXAD", dptw0cont) == 1': 0 + +# If MVPV bit is set, then do page table walk in machine mode for loads and stores. +MPRV_SUM_bit: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + 'mode == "M" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #check mstatus has: Case 1: MPP=S, SUM=1, MPRV=1 Case 2: MPP=S, SUM=0, MPRV=1 + mstatus == {0x00060800, 0x00020800}: 0 + val_comb: + 'mode == "M" and mnemonic == {"lw", "sw"} and old_csr_val("mstatus") == {0x00060800, 0x00020800} and get_pte_prop("ADURWXV", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "M" and mnemonic == {"lw", "sw"} and old_csr_val("mstatus") == {0x00060800, 0x00020800} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV", dptw0cont) == 1': 0 + #Fault Checks + 'mode == "M" and old_csr_val("mstatus") == 0x00060800 and get_pte_prop("ADURWXV", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + 'mode == "M" and old_csr_val("mstatus") == 0x00060800 and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV", dptw0cont) == 1 and len_dptw == 2': 0 + 'mode == "M" and old_csr_val("mstatus") == 0x00020800 and get_pte_prop("ADURWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {${CAUSE_LOAD_PAGE_FAULT}, ${CAUSE_STORE_PAGE_FAULT}}': 0 + 'mode == "M" and old_csr_val("mstatus") == 0x00020800 and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV", dptw0cont) == 1 and mcause == {${CAUSE_LOAD_PAGE_FAULT}, ${CAUSE_STORE_PAGE_FAULT}}': 0 \ No newline at end of file diff --git a/riscof-plugins/rv32/sail_cSim/env/model_test.h b/riscof-plugins/rv32/sail_cSim/env/model_test.h index 94f54405d..decd48c1b 100644 --- a/riscof-plugins/rv32/sail_cSim/env/model_test.h +++ b/riscof-plugins/rv32/sail_cSim/env/model_test.h @@ -1,5 +1,11 @@ #ifndef _COMPLIANCE_MODEL_H #define _COMPLIANCE_MODEL_H +#if XLEN == 64 + #define ALIGNMENT 3 +#else + #define ALIGNMENT 2 +#endif + #define RVMODEL_DATA_SECTION \ .pushsection .tohost,"aw",@progbits; \ @@ -23,12 +29,13 @@ li x1, 1 ;\ //RV_COMPLIANCE_DATA_BEGIN #define RVMODEL_DATA_BEGIN ;\ RVMODEL_DATA_SECTION ;\ -.align 4 ;\ +.align ALIGNMENT;\ .global begin_signature ;\ begin_signature: //RV_COMPLIANCE_DATA_END #define RVMODEL_DATA_END \ +.align ALIGNMENT;\ .global end_signature; end_signature: @@ -54,4 +61,4 @@ RVMODEL_DATA_SECTION ;\ #define RVMODEL_CLEAR_MEXT_INT -#endif // _COMPLIANCE_MODEL_H +#endif // _COMPLIANCE_MODEL_H \ No newline at end of file diff --git a/riscof-plugins/rv32/spike_simple/env/model_test.h b/riscof-plugins/rv32/spike_simple/env/model_test.h index 53c6e8cab..79c3c4700 100644 --- a/riscof-plugins/rv32/spike_simple/env/model_test.h +++ b/riscof-plugins/rv32/spike_simple/env/model_test.h @@ -33,6 +33,7 @@ li x1, 1 ;\ //RV_COMPLIANCE_DATA_END #define RVMODEL_DATA_END \ +.align ALIGNMENT;\ .global end_signature; end_signature: //RVTEST_IO_INIT @@ -57,4 +58,4 @@ li x1, 1 ;\ #define RVMODEL_CLEAR_MEXT_INT -#endif // _COMPLIANCE_MODEL_H +#endif // _COMPLIANCE_MODEL_H \ No newline at end of file diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index 80a150505..32fdf8711 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -1374,6 +1374,11 @@ vmem_adj_\__MODE__\()epc: add T4, T4, sp /* calc address of correct sv_area */ csrr T2, CSR_XEPC /* T4 now pts to trapping sv_area mode */ +#ifdef SKIP_MEPC + addi T3, T3, 0 + j adj_\__MODE__\()epc +#endif + LREG T3, vmem_bgn_off(T4) // see if epc is in the vmem area LREG T6, vmem_seg_siz(T4) add T6, T6, T3 // construct vmem seg end @@ -1421,6 +1426,11 @@ adj_\__MODE__\()epc_rtn: // adj mepc so there is at least 4B of p csrr T2, CSR_XTVAL +#ifdef SKIP_MTVAL + addi T3, T3, 0 + j adj_\__MODE__\()tval +#endif + chk_\__MODE__\()tval: andi T5, T5, EXCPT_CAUSE_MSK // ensures shift amt will be within range LI( T3, SET_REL_TVAL_MSK) // now check if code or data (or sig) region adjustment diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 4ed2bc010..92ca994f1 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -21,6 +21,8 @@ #define LEVEL3 0x03 #define LEVEL4 0x04 +#define ALL_F_S 0xFFFFFFFF + #define sv39 0x00 #define sv48 0x01 #define sv57 0x02 @@ -189,14 +191,37 @@ Mend_PMP: ;\ or _PAR, _PAR, _PR ;\ SREG _PAR, 0(_TR1); -#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ - .if (level==1) ;\ - LA(_TR1, rvtest_Sroot_pg_tbl) ;\ - .endif ;\ - .if (level==0) ;\ - LA(_TR1, rvtest_slvl1_pg_tbl) ;\ - .endif ;\ - PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) +#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\ + srli _PAR, _PAR, 12 ;\ + slli _PAR, _PAR, 10 ;\ + or _PAR, _PAR, _PR ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + LI(_TR0, ((VA>>22)&0x3FF)<<2) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + LI(_TR0, ((VA>>12)&0x3FF)<<2) ;\ + .endif ;\ + add _TR1, _TR1, _TR0 ;\ + SREG _PAR, 0(_TR1); + +// More Robust version of PTE_SETUP_32 to setup a PTE for a PA using Va +// in a single line. +//args: PA: Label of Physical Address, PERMS: permissions in hex +//args: VA: Virtual Address in hex, level: Level to store at +#define PTE_SETUP_RV32_New(PA_LBL, PERMS, VA, level) ;\ + LA(a0, PA_LBL) ;\ + LI(a1, PERMS) ;\ + PTE_SETUP_RV32(a0, a1, t0, t1, VA, level) ;\ + +#define SAVE_AREA_SETUP(VA, PA_LBL, _REG_NAME) ;\ + LI (t0, VA) ;\ + LA (t1, PA_LBL) ;\ + sub t0, t0, t1 ;\ + LREG t1, _REG_NAME##_bgn_off+0*sv_area_sz(sp) ;\ + add t2, t1, t0 ;\ + SREG t2, _REG_NAME##_bgn_off+1*sv_area_sz(sp) ;\ #define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ .if (level==2) ;\ diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S b/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S new file mode 100644 index 000000000..350279292 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S @@ -0,0 +1,130 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// This test verifies the functionality of mstatus.TVM bit with the satp and sfence.vma +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. satp and sfence.vma accessed in M Mode with mstatus.tvm bit set -> Successful +// 2. satp and sfence.vma accessed in S Mode with mstatus.tvm bit set -> illegal instruction exception +// +// Total Expected Faults: 2 +// ---------------------------------------------------------------------------------------------------------------------- + +//TODO: instead of using two different tests, use a single test for hart/software update. + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", mstatus_tvm) + +RVTEST_SIGBASE( x13,signature_x13_1) + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + + #set the mstatus with the TVM bit + LI (t4, MSTATUS_TVM) + csrw mstatus, t4 + csrr t3, mstatus + RVTEST_SIGUPD(x13,t3) + +// ------------------------------------------------------------------------------------------------------------ +// satp access in M Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + li t0, 1 //initial value for t0 = 1 + #successful access + csrw satp, t0 // write satp with some value + csrr t3, satp + RVTEST_SIGUPD(x13,t3) + + #successful access + sfence.vma + nop + nop + +// ------------------------------------------------------------------------------------------------------------ +// satp access in S Mode +// ------------------------------------------------------------------------------------------------------------ + + RVTEST_GOTO_LOWER_MODE Smode + + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + nop + nop + + sfence.vma + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 64*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S new file mode 100644 index 000000000..173770638 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S @@ -0,0 +1,328 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the physical address in S mode in the SV-32 virtual memory system. +// +// PMP Permissions on the physical address test in S mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section Physical address is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our region of interest has the lablel = rvtest_data_1_l1 and rvtest_data_1_l0 +The rvtest_data_1_l0 comes right after the rvtest_data_1_l1 +Therefore, Region 1 can be configured with RWX with TOR with the label rvtest_slvl1_pg_tbl -> next label after the rvtest_data_1_l0 +Then, Region 2 can be configured with NO RWX and as a TOR region consisting of rvtest_data_1_l1 and rvtest_data_1_l0 +Then, Region 3 till 0xFFFFFFFF with RWX and as a TOR Region above rvtest_data_1_l0. +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_data_1_l1) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the TOR region sized 4MB+4KB labeled as rvtest_data_1_l1 + rvtest_data_1_l0 + LA (t0, return_page_level_1_with_PMP_perms) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg01 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg02 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(return_page_level_1_with_PMP_perms, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(return_page_level_0_with_PMP_perms, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +.align 22 + +return_page_level_1_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +return_page_level_0_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S new file mode 100644 index 000000000..4258538a4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S @@ -0,0 +1,328 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the physical address in U mode in the SV-32 virtual memory system. +// +// PMP Permissions on the physical address test in U mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section Physical address is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our region of interest has the lablel = rvtest_data_1_l1 and rvtest_data_1_l0 +The rvtest_data_1_l0 comes right after the rvtest_data_1_l1 +Therefore, Region 1 can be configured with RWX with TOR with the label rvtest_slvl1_pg_tbl -> next label after the rvtest_data_1_l0 +Then, Region 2 can be configured with NO RWX and as a TOR region consisting of rvtest_data_1_l1 and rvtest_data_1_l0 +Then, Region 3 till 0xFFFFFFFF with RWX and as a TOR Region above rvtest_data_1_l0. +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_data_1_l1) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the TOR region sized 4MB+4KB labeled as rvtest_data_1_l1 + rvtest_data_1_l0 + LA (t0, return_page_level_1_with_PMP_perms) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg01 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg02 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(return_page_level_1_with_PMP_perms, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(return_page_level_0_with_PMP_perms, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +.align 22 + +return_page_level_1_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +return_page_level_0_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S new file mode 100644 index 000000000..c07982092 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S @@ -0,0 +1,302 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in S mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in S mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section PTE is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our data section maps to 0x91400000 which means the offset for root page table is 0x914 and 0x000 for the level1 page table. +Therefore, we will give RWX permission before this offset via TOR i.e., rvtest_Sroot_pg_tbl + 0x914 +For this region we will use NA4 and will give only X permissions. +After this region till 0xFFFFFFFF, RWX permissions via TOR +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_Sroot_pg_tbl) //load the address of root page table + LI (t1, 0x914) // ALL perms before the data section + add t0, t0, t1 + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the NAPOT region sized 4KB (0x1FF) labeled as + LI (t1, (PMP_NA4)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S new file mode 100644 index 000000000..28c8b2254 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S @@ -0,0 +1,302 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in U mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in U mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section PTE is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our data section maps to 0x91400000 which means the offset for root page table is 0x914 and 0x000 for the level1 page table. +Therefore, we will give RWX permission before this offset via TOR i.e., rvtest_Sroot_pg_tbl + 0x914 +For this region we will use NA4 and will give only X permissions. +After this region till 0xFFFFFFFF, RWX permissions via TOR +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_Sroot_pg_tbl) //load the address of root page table + LI (t1, 0x914) // ALL perms before the data section + add t0, t0, t1 + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the NAPOT region sized 4KB (0x1FF) labeled as + LI (t1, (PMP_NA4)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S new file mode 100644 index 000000000..ab346a9ff --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S @@ -0,0 +1,195 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// This test verifies the functionality of satp register in M, S and U Mode using csrrw, csrrs, csrrc. +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. satp register accessed in M, S Mode -> Successful +// 2. satp register accessed in U Mode -> Illegal Instruction exception +// 3. Walking ones on the PPN of satp -> Successful +// Total Expected Faults: 3 +// ---------------------------------------------------------------------------------------------------------------------- + +//TODO: instead of using two different tests, use a single test for hart/software update. + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", satp_access_all_modes) + +RVTEST_SIGBASE( x13,signature_x13_1) + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +// ------------------------------------------------------------------------------------------------------------ +// satp access in M Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrs satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrc satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + +// ------------------------------------------------------------------------------------------------------------ +// satp access in S Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + + //Go to S mode + RVTEST_GOTO_LOWER_MODE Smode + + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrs satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrc satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + RVTEST_GOTO_MMODE // Switching back to M mode + +// ------------------------------------------------------------------------------------------------------------ +// satp access in U Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + + RVTEST_GOTO_LOWER_MODE Umode + + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + nop + nop + + csrs satp, t0 // write satp with some value + nop + nop + + csrc satp, t0 // write satp with some value + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +// ------------------------------------------------------------------------------------------------------------ +// PPN Write all zeros, ones and walking ones to the PPN bits of satp register csrw instruction +// ------------------------------------------------------------------------------------------------------------ + csrw satp, zero // All ZEROES + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + + li t0, 0x3FFFFF //All ONES in the PPN + csrw satp, t0 + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + +RVTEST_SIGBASE( x14,signature_x14_1) + +//Walking one test for PPN bits of satp register + li t2, 0 // shift left value + li t3, 22 // max value of shift left (PPN Width) +walking_ones_satp: + li t0, 1 //initial value for t0 = 1 + sll t0, t0, t2 + addi t2, t2, 1 + csrw satp, t0 + csrr t1, satp + RVTEST_SIGUPD(x14,t1) + addi x14, x14, REGWIDTH + bne t3, t2, walking_ones_satp + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 64*(XLEN/32),4,0xcafebeef + +// test signatures initialization +signature_x14_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S new file mode 100644 index 000000000..b0ffeab68 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S @@ -0,0 +1,387 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. +// +// Access and Dirty Bit Test in S-Mode with Software Update +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Store-page-fault +// +// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: No fault should occur. +// +// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Store-page-fault +// +// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: No fault should occur. +// +// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// Total Expected Faults: 14 +// ---------------------------------------------------------------------------------------------------------------------- + +//TODO: instead of using two different tests, use a single test for hart/software update. + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +/* + ! If the hardware updates the A and D bit, Please add " def HARDWARE_UPDATE_A_D=True; " in the RVTEST_CASE + SOFTWARE_UPDATE_A_D=True is defined here by default, replace when using the hardware update +*/ + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def SOFTWARE_UPDATE_A_D=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", a_and_d_bit_soft_upd, a_and_d_bit_hart_upd) + +RVTEST_SIGBASE( x13,signature_x13_1) +// ------------------------------------------------------------------------------------------------------------ +// Macro to test RWX (read, write, execute) permissions. +// ------------------------------------------------------------------------------------------------------------ +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +// ------------------------------------------------------------------------------------------------------------ +// Macro to run the test +// ------------------------------------------------------------------------------------------------------------ +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + #endif + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + #endif + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = Store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + #endif + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + #endif + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S new file mode 100644 index 000000000..6ec4ef4c7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S @@ -0,0 +1,385 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. +// +// Access and Dirty Bit Test in U-Mode with Software Update +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Store-page-fault +// +// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: No fault should occur. +// +// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Store-page-fault +// +// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: No fault should occur. +// +// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// Total Expected Faults: 14 +// ---------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +/* + ! If the hardware updates the A and D bit, Please add " def HARDWARE_UPDATE_A_D=True; " in the RVTEST_CASE + SOFTWARE_UPDATE_A_D=True is defined here by default, replace when using the hardware update +*/ + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def SOFTWARE_UPDATE_A_D=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd) + +RVTEST_SIGBASE( x13,signature_x13_1) +// ------------------------------------------------------------------------------------------------------------ +// Macro to test RWX (read, write, execute) permissions. +// ------------------------------------------------------------------------------------------------------------ +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +// ------------------------------------------------------------------------------------------------------------ +// Macro to run the test +// ------------------------------------------------------------------------------------------------------------ +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + #endif + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + #endif + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = Store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + #endif + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + #ifdef SOFTWARE_UPDATE_A_D + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + #endif + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S new file mode 100644 index 000000000..1316f8864 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S @@ -0,0 +1,373 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. U bit is set for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: No Fault +// 2. U bit is set for the page at level 1 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 3. U bit is set for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Store-page-fault +// 4. U bit is set for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Fetch-page-fault +// 5. U bit is set for the page at level 1 with R Permissions (Read only page): +// Then, in U-Mode, the page is accessed --> required: fetch-page-fault, store-page-fault + +// 6. U bit is set for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: No Fault +// 7. U bit is set for the page at level 0 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 8. U bit is set for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Store-page-fault +// 9. U bit is set for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Fetch-page-fault +// 10. U bit is set for the page at level 0 with R Permissions (Read only page): +// Then, in U-Mode, the page is accessed --> required: fetch-page-fault, store-page-fault + +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_set_in_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +//Test Cases are checked in this macro by switching to the expected mode. +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit set | Test in U-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit set | Test in U-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit set | Test in U-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit set | Test in U-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit set | Test in U-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit set | Test in U-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit set | Test in U-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit set | Test in U-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4kB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit set | Test in U-Mode | R bit set | expected = Store-page-fault, fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit set | Test in U-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 64*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S new file mode 100644 index 000000000..3dd17d376 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S @@ -0,0 +1,393 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. U bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No fault +// 2. U bit is UnSet for the page at level 1 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault +// 3. U bit is UnSet for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 4. U bit is UnSet for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 5. U bit is UnSet for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault + +// 6. U bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No fault +// 7. U bit is UnSet for the page at level 0 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault +// 8. U bit is UnSet for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 9. U bit is UnSet for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 10. U bit is UnSet for the page at level 0 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault + +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_unset_in_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit unset | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit unset | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit unset | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit unset | Test in S-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit unset | Test in S-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit unset | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit unset | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit unset | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit unset | Test in S-Mode | R bit set | expected = Store-page-fault, fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit unset | Test in S-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S new file mode 100644 index 000000000..e67ce9ad6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S @@ -0,0 +1,403 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ----------- +// This test is a part of the test plan for SV-32 based Virtual Memory System available at https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- 10.3 +// This assembly file tests the working of U bit. The test is organized in the following pattern: +// ------------------------------------------U bit Unset test in U Mode --------------------------------------------------- +// 1. U bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. U bit is UnSet for the page at level 1 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 3. U bit is UnSet for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 4. U bit is UnSet for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 5. U bit is UnSet for the page at level 1 with X Permissions (execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault + +// 6. U bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 7. U bit is UnSet for the page at level 0 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 8. U bit is UnSet for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 9. U bit is UnSet for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 10. U bit is UnSet for the page at level 0 with X Permissions (execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault + +// Total Expected Faults :: 30 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", U_bit_unset_in_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit Unset | Test in U-Mode | RWX bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit Unset | Test in U-Mode | RX bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit Unset | Test in U-Mode | RW bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit Unset | Test in U-Mode | RWX bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit Unset | Test in U-Mode | RX bit set | expected = Load, Store, Fetch Page Faults Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit Unset | Test in U-Mode | R bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S new file mode 100644 index 000000000..8182e5ee6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S @@ -0,0 +1,279 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in S mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in S mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. V bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. V bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",invalid_pte) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S new file mode 100644 index 000000000..7a5136595 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S @@ -0,0 +1,280 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in U mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in U mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------Invalid PTE test in U Mode --------------------------------------------------- +// 1. V bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. V bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", invalid_pte) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S new file mode 100644 index 000000000..b8df0ee6c --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S @@ -0,0 +1,255 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. At level 1 with R,W,X Permissions; Misaligned rvtest_data_1_l1 (.align 12) (read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: Load Page Fault, store page fault, fetch page fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: R,W,X set and A, D bit set | Test in S-Mode | RWX bit set | expected = Fetch ,Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A| PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 12 //misaligned page + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S new file mode 100644 index 000000000..5d366bc7a --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S @@ -0,0 +1,254 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. At level 1 with R,W,X Permissions; Misaligned rvtest_data_1_l1 (.align 12) (read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load Page Fault, store page fault, fetch page fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: R,W,X set and A bit unset | Test in U-Mode | RWX bit set | expected = Fetch ,Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 12 //misaligned page + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S new file mode 100644 index 000000000..5b5c6302e --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S @@ -0,0 +1,295 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test in M Mode (with S bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + LI (s7, MSTATUS_MPRV) + csrs mstatus,s7 + LI (s7, 0x1800) //clear previous mode + csrc mstatus,s7 + LI (s7, 0x800) //Smode + csrs mstatus,s7 + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S new file mode 100644 index 000000000..6e124b7eb --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S @@ -0,0 +1,293 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test in M Mode (with U bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + LI (s7, MSTATUS_MPRV) + csrs mstatus,s7 + LI (s7, 0x1800) //Set to U Mode + csrc mstatus,s7 + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S new file mode 100644 index 000000000..dbb58d87d --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S @@ -0,0 +1,309 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test with the combination of SUM set in mstatus in M Mode (with U bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus and SUM bit is not SET: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#define SKIP_MTVAL +#define SKIP_MEPC + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sfence.vma + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + #Set the required mstatus values for this test (in case of a trap) + SET_REQ_MSTATUS_VAL + + sfence.vma + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + SET_REQ_MSTATUS_VAL + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +.macro SET_REQ_MSTATUS_VAL + LI (s7, MSTATUS_MPRV) + csrs mstatus,s7 + LI (s7, MSTATUS_SUM) //SET the MSTATUS sum bit + csrs mstatus,s7 + LI (s7, 0x1800) //clear previous mode + csrc mstatus,s7 + LI (s7, 0x800) //Smode + csrs mstatus,s7 +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S new file mode 100644 index 000000000..127f07714 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S @@ -0,0 +1,301 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test with the combination of SUM unset in mstatus in M Mode (with U bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus and SUM bit is not SET: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#define SKIP_MTVAL +#define SKIP_MEPC + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sfence.vma + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + #Set the required mstatus values for this test + SET_REQ_MSTATUS_VAL + + sfence.vma + nop + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + SET_REQ_MSTATUS_VAL + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +.macro SET_REQ_MSTATUS_VAL + LI (s7, MSTATUS_MPRV) + csrw mstatus,s7 //using csrrw to remove anyother values written on the mstatus register. + LI (s7, MSTATUS_SUM) //Clear the MSTATUS sum bit + csrc mstatus,s7 + LI (s7, 0x1800) //clear previous mode + csrc mstatus,s7 + LI (s7, 0x800) //Smode + csrs mstatus,s7 +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S new file mode 100644 index 000000000..bd61564a1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S @@ -0,0 +1,298 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. X bit is set and MXR bit in mstatus is unset for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: Load Page Fault, store page fault +// 2. X bit is set and MXR bit in mstatus is set for the page at level 1 with X Permissions (execute page, read page --> MXR Bit): +// Then, in S-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault + +// 3. X bit is set and MXR bit in mstatus is unset for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in S-Mode, the page is accessed --> required: Load Page Fault, store page fault + +// 4. X bit is set and MXR bit in mstatus is set for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in S-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: X bit set and MXR bit unset | Test in S-Mode | RWX bit set | expected = Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: X bit set and MXR bit set | Test in S-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: X bit set and MXR bit unset | Test in S-Mode | RWX bit set | expected = store, load page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrc mstatus,s7 // unset the mstatus.MXR = 0 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: X bit set and MXR bit set | Test in S-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S new file mode 100644 index 000000000..b646b63ee --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S @@ -0,0 +1,298 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. X bit is set and MXR bit in mstatus is unset for the page at level 1 with X Permissions (execute page): +// Then, in U-Mode, the page is accessed --> required: Load Page Fault, store page fault +// 2. X bit is set and MXR bit in mstatus is set for the page at level 1 with X Permissions (execute page, read page --> MXR Bit): +// Then, in U-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault + +// 3. X bit is set and MXR bit in mstatus is unset for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in U-Mode, the page is accessed --> required: Load Page Fault, store page fault + +// 4. X bit is set and MXR bit in mstatus is set for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in U-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: X bit set and MXR bit unset | Test in U-Mode | RWX bit set | expected = Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: X bit set and MXR bit set | Test in U-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: X bit set and MXR bit unset | Test in U-Mode | RWX bit set | expected = store, load page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrc mstatus,s7 // unset the mstatus.MXR = 0 + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: X bit set and MXR bit set | Test in U-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S new file mode 100644 index 000000000..83e43f743 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S @@ -0,0 +1,257 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. No RWX but only V bit is set for the PTE at Level 0: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in S-Mode | Only V bit set at Level 0 | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S new file mode 100644 index 000000000..eaf8bf5b6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S @@ -0,0 +1,257 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. No RWX but only V bit is set for the PTE at Level 0: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- No RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in U-Mode | Only V bit set at Level 0 | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S new file mode 100644 index 000000000..a3e1010c0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S @@ -0,0 +1,273 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. RSW Permissions is Set for the page at level 1 (11): +// Then, in U-Mode, the page is accessed --> required: No affect on these bits, successful page table walk +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S new file mode 100644 index 000000000..1290dd2e7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S @@ -0,0 +1,273 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. RSW Permissions is Set for the page at level 1 (11): +// Then, in U-Mode, the page is accessed --> required: No affect on these bits, successful page table walk +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S new file mode 100644 index 000000000..f64b55a4c --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S @@ -0,0 +1,307 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. WX Permissions is Set for the page at level 1: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. W Permissions is Set for the page at level 1: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 3. WX Permissions is Set for the page at level 0: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 4. W Permissions is Set for the page at level 0: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in S-Mode | WX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in S-Mode | W bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in S-Mode | WX bit set | expected = WX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in S-Mode | WX bit set | expected = W fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S new file mode 100644 index 000000000..96ac761d3 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S @@ -0,0 +1,307 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. WX Permissions is Set for the page at level 1: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. W Permissions is Set for the page at level 1: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 3. WX Permissions is Set for the page at level 0: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 4. W Permissions is Set for the page at level 0: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in U-Mode | WX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in U-Mode | W bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in U-Mode | WX bit set | expected = WX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in U-Mode | WX bit set | expected = W fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S new file mode 100644 index 000000000..7ba5a32f0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S @@ -0,0 +1,423 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ----------- +// This test is a part of the test plan for SV-32 based Virtual Memory System available at https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- 10.3 +// This assembly file tests the working of U bit. The test is organized in the following: +// ------------------------------------------Sum bit test in S Mode --------------------------------------------------- +// 1. U bit is set and Sum bit in mstatus is set for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No Fault +// 2. U bit is set and Sum bit in mstatus is set for the page at level 1 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 3. U bit is set and Sum bit in mstatus is set for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 4. U bit is set and Sum bit in mstatus is set for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 5. U bit is set and Sum bit in mstatus is set for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault + +// 6. U bit is set and Sum bit in mstatus is set for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No Fault +// 7. U bit is set and Sum bit in mstatus is set for the page at level 0 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 8. U bit is set and Sum bit in mstatus is set for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 9. U bit is set and Sum bit in mstatus is set for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 10. U bit is set and Sum bit in mstatus is set for the page at level 0 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault + +// Total Expected Faults :: 18 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_sum_set_in_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit set | Test in S-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit set | Test in S-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit set | Test in S-Mode | R bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit set | Test in S-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S new file mode 100644 index 000000000..9227af039 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S @@ -0,0 +1,403 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. U bit is set and Sum bit in mstatus is unset for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 2. U bit is set and Sum bit in mstatus is unset for the page at level 1 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 3. U bit is set and Sum bit in mstatus is unset for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 4. U bit is set and Sum bit in mstatus is unset for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 5. U bit is set and Sum bit in mstatus is unset for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault + +// 6. U bit is set and Sum bit in mstatus is unset for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 7. U bit is set and Sum bit in mstatus is unset for the page at level 0 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 8. U bit is set and Sum bit in mstatus is unset for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 9. U bit is set and Sum bit in mstatus is unset for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 10. U bit is set and Sum bit in mstatus is unset for the page at level 0 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault + +// Total Expected Faults :: 30 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_no_sum_set_in_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit set | Test in S-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit set | Test in S-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit set | Test in S-Mode | R bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit set | Test in S-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END