From 63b31cbe88f8476a134eef5007db9821fc4c4011 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 11 Oct 2024 19:59:26 +0500 Subject: [PATCH 01/19] SV32 Tests and Covergroups added --- coverage/rv32_vm_sv32_hart_upd.cgf | 97 +++ coverage/rv32_vm_sv32_soft_upd.cgf | 763 ++++++++++++++++++ .../vm_A_and_D_hart_upd_S_mode.S | 358 ++++++++ .../vm_A_and_D_hart_upd_U_mode.S | 358 ++++++++ .../pmp_check_on_pa_S_mode.S | 328 ++++++++ .../pmp_check_on_pa_U_mode.S | 328 ++++++++ .../pmp_check_on_pte_S_mode.S | 302 +++++++ .../pmp_check_on_pte_U_mode.S | 302 +++++++ .../vm_A_and_D_soft_upd_S_mode.S | 372 +++++++++ .../vm_A_and_D_soft_upd_U_mode.S | 372 +++++++++ .../vm_U_Bit_set_U_mode.S | 372 +++++++++ .../vm_U_Bit_unset_S_mode.S | 392 +++++++++ .../vm_U_Bit_unset_U_mode.S | 402 +++++++++ .../vm_invalid_pte_S_mode.S | 278 +++++++ .../vm_invalid_pte_U_mode.S | 279 +++++++ .../vm_misaligned_S_mode.S | 254 ++++++ .../vm_misaligned_U_mode.S | 253 ++++++ .../vm_sv32_software_update/vm_mxr_S_mode.S | 297 +++++++ .../vm_sv32_software_update/vm_mxr_U_mode.S | 297 +++++++ .../vm_nleaf_pte_level0_S_mode.S | 256 ++++++ .../vm_nleaf_pte_level0_U_mode.S | 256 ++++++ .../vm_reserved_pte_S_mode.S | 306 +++++++ .../vm_reserved_pte_U_mode.S | 306 +++++++ .../vm_sum_set_S_mode.S | 422 ++++++++++ .../vm_sum_unset_S_mode.S | 402 +++++++++ 25 files changed, 8352 insertions(+) create mode 100644 coverage/rv32_vm_sv32_hart_upd.cgf create mode 100644 coverage/rv32_vm_sv32_soft_upd.cgf create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S diff --git a/coverage/rv32_vm_sv32_hart_upd.cgf b/coverage/rv32_vm_sv32_hart_upd.cgf new file mode 100644 index 000000000..5765f93a7 --- /dev/null +++ b/coverage/rv32_vm_sv32_hart_upd.cgf @@ -0,0 +1,97 @@ +a_and_d_bit_hart_upd_S_mode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + #CASES at LEVEL 1 + # Test Case:1 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 1 + 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 -> D bit set and A bit set and RWX set -> NO FAULT -- LEVEL 1 + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case:3 -> D bit set but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 + 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:4 -> No D bit unset but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 + #CASES at LEVEL 0 + # Test Case:5 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 + # Test Case:6 -> D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 + # Test Case:7 -> D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 + # Test Case:8 -> No D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 + #Faults check at LEVEL 1 and LEVEL 0 + #Test Case:1 --> successfull page table walk + 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:2 --> successfull page table walk + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:3 --> successfull page table walk + 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:4 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:5 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 + #Test Case:6 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1 and len_dptw == 2': 0 + #Test Case:7 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 + #Test Case:8 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 + +a_and_d_bit_hart_upd_U_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # LEVEL 1 Test Cases: + # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 2: Both A and D bits set, RWX set --> No fault. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 + # LEVEL 0 Test Cases: + # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 + # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 + # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 + # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 + # Fault Checks: + # Test Case 1: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 2: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 3: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 4: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 5: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 + # Test Case 6: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1 and len_dptw == 2': 0 + # Test Case 7: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 + # Test Case 8: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 diff --git a/coverage/rv32_vm_sv32_soft_upd.cgf b/coverage/rv32_vm_sv32_soft_upd.cgf new file mode 100644 index 000000000..0864ed1c5 --- /dev/null +++ b/coverage/rv32_vm_sv32_soft_upd.cgf @@ -0,0 +1,763 @@ +a_and_d_bit_soft_upd_S_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # LEVEL 1 Test Cases: + # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 2: Both A and D bits set, RWX set --> No fault. + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 + # LEVEL 0 Test Cases: + # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 + # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 + # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 + # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 + # Fault Checks: + # Test Case 1: Store Page Fault, successful page table walk for load, fetch. + 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 + # Test Case 2: Successful page table walk at Level 1. + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + #Test Case 3: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("RWX", iptw1cont) == 1 and get_pte_prop("AD", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 4: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("DRWX", iptw1cont) == 1 and get_pte_prop("A", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + # Test Case 5: Store Page Fault, successful page table walk for load, fetch. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 + # Test Case 6: Successful page table walk at Level 0. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1 and len_dptw == 2': 0 + #Test Case 7: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("RWX", iptw1cont) == 0 and get_pte_prop("DRWX", iptw0cont) == 1 and get_pte_prop("A", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 8: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("RWX", iptw1cont) == 0 and get_pte_prop("RWX", iptw0cont) == 1 and get_pte_prop("AD", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +a_and_d_bit_soft_upd_U_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # LEVEL 1 Test Cases: + # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 2: Both A and D bits set, RWX set --> No fault. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 + # LEVEL 0 Test Cases: + # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 + # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 + # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 + # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 + # Fault Checks: + # Test Case 1: Store Page Fault, successful page table walk for load, fetch. + 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + 'mode == "U" and mnemonic == "sw" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 + # Test Case 2: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + #Test Case 3: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("RWUX", iptw1cont) == 1 and get_pte_prop("AD", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 4: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("DRWUX", iptw1cont) == 1 and get_pte_prop("A", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + # Test Case 5: Store Page Fault, successful page table walk for load, fetch. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 + 'mode == "U" and mnemonic == "sw" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 + # Test Case 6: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1 and len_dptw == 2': 0 + #Test Case 7: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("RWUX", iptw1cont) == 0 and get_pte_prop("DRWUX", iptw0cont) == 1 and get_pte_prop("A", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 8: expected: Load-page-fault, Store-page-fault, Fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + 'mode == "M" and get_pte_prop("RWUX", iptw1cont) == 0 and get_pte_prop("RWUX", iptw0cont) == 1 and get_pte_prop("AD", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +pmp_check_pa_S_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + # Region of Interest -> Test Section has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg + '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_TOR_MODE}': 0 + val_comb: + # LEVEL 1 Test Cases: + # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 + # LEVEL 0 Test Cases: + # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 + # Fault Checks: + # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]}': 0 + 'mode == "M" and mnemonic == "jal" and mcause == 1': 0 + +pmp_check_pa_U_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + # Region of Interest -> Test Section has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg + '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_TOR_MODE}': 0 + val_comb: + # LEVEL 1 Test Cases: + # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 + # LEVEL 0 Test Cases: + # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 + # Fault Checks: + # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]}': 0 + 'mode == "M" and mnemonic == "jal" and mcause == 1': 0 + +pmp_check_pte_U_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + # Region of Interest -> Page Table Entry has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg + '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_NA4_MODE}': 0 + val_comb: + #Note: No way to check the PTW since we will get the access fault before we are able to check the PTW, therefore, no coverpoints! + #For this case, the only way to verify that the Virtual Memory is enabled is by checking the satp register. + # Fault Checks: + # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]} and len_dptw == 0': 0 + 'mode == "M" and mnemonic == "jal" and mcause == 1 and len_iptw == 0': 0 + +pmp_check_pte_S_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + # Region of Interest -> Page Table Entry has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg + '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_NA4_MODE}': 0 + val_comb: + #Note: No way to check the PTW since we will get the access fault before we are able to check the PTW, therefore, no coverpoints! + #For this case, the only way to verify that the Virtual Memory is enabled is by checking the satp register. + # Fault Checks: + # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]} and len_dptw == 0': 0 + 'mode == "M" and mnemonic == "jal" and mcause == 1 and len_iptw == 0': 0 + +invalid_pte_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Test Case:1 -> No V bit set but RWX set -> load, store, fetch page fault + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0': 0 + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +invalid_pte_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Test Case:1 -> No V bit set but RWX set -> load, store, fetch page fault + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0': 0 + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +misaligned_superpage_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_dptw == 1': 0 + # Test Case:1 -> All permissions given for RWX -> still we will get RWX fault because of the misaligned super page. + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None': 0 + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +misaligned_superpage_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "U" and len_dptw == 1': 0 + # Test Case:1 -> All permissions given for RWX -> still we will get RWX fault because of the misaligned super page. + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None': 0 + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +MXR_bit_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #CHECK THE SUM BIT IS SET in MSTATUS: + '(mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_{i,d}ptw == {1,2}': 0 + # Test Case:1 + 'mode == "S" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and {i, d}ptw0cont == None': 0 + # Test Case:10 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 + #Checks for Loads, Store, fetch Faults start from here + #Test Case 1: expected: store-page-fault + 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #Test Case 2: expected: store-page-fault, load-page-fault -> No MXR set with No R, so expected load page fault + 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == 15': 0 + #Test Case 3: expected: load-page-fault, store-page-fault -> No MXR set with No R, so expected load page fault + 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + +MXR_bit_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #CHECK THE SUM BIT IS SET in MSTATUS: + '(mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "U" and len_{i,d}ptw == {1,2}': 0 + # Test Case:1 + 'mode == "U" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and {i, d}ptw0cont == None': 0 + # Test Case:10 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 + #Checks for Loads, Store, fetch Faults start from here + #Test Case 1: expected: store-page-fault + 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #Test Case 2: expected: store-page-fault, load-page-fault -> No MXR set with No R, so expected load page fault + 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == 15': 0 + #Test Case 3: expected: load-page-fault, store-page-fault -> No MXR set with No R, so expected load page fault + 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + +nonleaf_pte_level0_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_dptw == 2': 0 + # Test Case:1 + 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $1ptw0cont) == 0': 0 + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $2ptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +nonleaf_pte_level0_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "U" and len_dptw == 2': 0 + # Test Case:1 + 'mode == "U" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $1ptw0cont) == 0': 0 + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $2ptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +reserved_pte_perm_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_dptw == {1,2}': 0 + # Test Case:1 + 'mode == "S" and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 + 'mode == "S" and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:3 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0': 0 + # Test Case:4 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0': 0 + + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault, page-fault-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 4: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +reserved_pte_perm_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "U" and len_dptw == {1,2}': 0 + # Test Case:1 + 'mode == "U" and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 + 'mode == "U" and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:3 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0': 0 + # Test Case:4 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0': 0 + + #checks for load, store and page faults begin from here. + #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault, page-fault-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 4: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +U_bit_sum_set_in_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #CHECK THE SUM BIT IS SET in MSTATUS: + '(mstatus & ${MSTATUS_SUM}) == ${MSTATUS_SUM}': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_{i,d}ptw == {1,2}': 0 + # Test Case:1 + 'mode == "S" and get_pte_prop("URWX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case:2 + 'mode == "S" and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:3 + 'mode == "S" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:4 + 'mode == "S" and get_pte_prop("URW", dptw1cont) == 1 and get_pte_prop("X", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:5 + 'mode == "S" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:6 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URWX", dptw0cont) == 1': 0 + # Test Case:7 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 + # Test Case:8 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0': 0 + # Test Case:9 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URW", dptw0cont) == 1 and get_pte_prop("X", dptw0cont) == 0': 0 + # Test Case:10 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0': 0 + #Checks for the load, store and fetch page faults begin here + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0 and mcause == 15': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0 and mcause == 15': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +U_bit_no_sum_set_in_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #CHECK THE SUM BIT IS SET in MSTATUS: + '(mstatus & ${MSTATUS_SUM}) != ${MSTATUS_SUM}': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_{i,d}ptw == {1,2}': 0 + # Test Case:1 + 'mode == "S" and get_pte_prop("URWX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case:2 + 'mode == "S" and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:3 + 'mode == "S" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:4 + 'mode == "S" and get_pte_prop("URW", dptw1cont) == 1 and get_pte_prop("X", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:5 + 'mode == "S" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:6 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URWX", dptw0cont) == 1': 0 + # Test Case:7 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 + # Test Case:8 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0': 0 + # Test Case:9 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URW", dptw0cont) == 1 and get_pte_prop("X", dptw0cont) == 0': 0 + # Test Case:10 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0': 0 + #Checks for Loads, Store, fetch Faults start from here + #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 5: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +U_bit_set_in_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Set up checks (Mostly M Mode) + #Check that the satp is active --> in U mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Testing Checks (Mostly U Mode) + # '(mnemonic == "sw" and (get_pte_prop("U", get_addr("vm_en"), rs1_val+imm_val, get_addr("rvtest_slvl1_pg_tbl")) == 1)) if ieva is not None else False': 0 + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "U" and len_{i,d}ptw == {1,2}': 0 + #---------------------------------------------------------------------------------------------- + # Test Cases for Level 1 + #---------------------------------------------------------------------------------------------- + #We expect that the U bit is set at the level 1, we are going to use the cross comb such that the + # U bit is set for the PTE at level 1 (U Mode) and the RWX is set + # Nothing is available for the PTE at the level 0 + # Side Note: This is done by the jalr instruction only at level 1 because we have no instruction at level 1 in the test + # except the jalr :( + # Test Case:1 + 'mode == "U" and get_pte_prop("URWX", {i, d}ptw1cont) == 1 and $1ptw0cont == None': 0 + # Test Case:2 + 'mode == "U" and get_pte_prop("UX", {i, d}ptw1cont) == 1 and get_pte_prop("RW", $1ptw1cont) == 0 and $1ptw0cont == None': 0 + # Test Case:3 + 'mode == "U" and get_pte_prop("URX", {i, d}ptw1cont) == 1 and get_pte_prop("W", $1ptw1cont) == 0 and $1ptw0cont == None': 0 + # Test Case:4 + 'mode == "U" and get_pte_prop("URW", dptw1cont) == 1 and get_pte_prop("X", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:5 + 'mode == "U" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None': 0 + #---------------------------------------------------------------------------------------------- + # Test Cases for Level 0 + #---------------------------------------------------------------------------------------------- + #We expect that the U bit is set at the level 0, we are going to use the cross comb such that the + # The RWX is zero meaning that it is a pointer to level 0!!! + # U bit is set for the PTE at level 1 (U Mode) and the RWX is set + # Test Case:6 + 'mode == "U" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("URWX", $1ptw0cont) == 1': 0 + # Test Case:7 + 'mode == "U" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("UX", $1ptw0cont) == 1 and get_pte_prop("RW", $1ptw0cont) == 0': 0 + # Test Case:8 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0': 0 + # Test Case:9 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URW", dptw0cont) == 1 and get_pte_prop("X", dptw0cont) == 0': 0 + # Test Case:10 + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0': 0 + #---------------------------------------------------------------------------------------------- + + #Now, we going to check that we get the required load, store, execute page faults for the ptes + #Load and stores can be checked using the same condition + #We set the U bit equal to zero and set the RWX equal to 1 but still get page fault because of no U bit in U mode + + #---------------------------------------------------------------------------------------------- + # Test Cases for Level 1 + #---------------------------------------------------------------------------------------------- + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "U" and mnemonic == "sw" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "U" and mnemonic == "sw" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + + #---------------------------------------------------------------------------------------------- + # Test Cases for Level 0 + #---------------------------------------------------------------------------------------------- + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "U" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0 and mcause == 15': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "U" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0 and mcause == 15': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +U_bit_unset_in_UMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in U mode & also check that SV32 is configured + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "U" and len_{i,d}ptw == {1,2}': 0 + # Test Case:1 -> RWX with NO U + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("U", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 -> X with NO U + 'mode == "U" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("URW", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:3 -> RX with NO U + 'mode == "U" and get_pte_prop("RX", dptw1cont) == 1 and get_pte_prop("UW", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:4 -> RW with NO U + 'mode == "U" and get_pte_prop("RW", dptw1cont) == 1 and get_pte_prop("UX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:5 -> R with NO U + 'mode == "U" and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:6 -> RWX with NO U + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("U", dptw0cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1': 0 + # Test Case:7 -> X with NO U + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("URW", dptw0cont) == 0': 0 + # Test Case:8 -> RX with NO U + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RX", dptw0cont) == 1 and get_pte_prop("UW", dptw0cont) == 0': 0 + # Test Case:9 -> X with NO U + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RW", dptw0cont) == 1 and get_pte_prop("UX", dptw0cont) == 0': 0 + # Test Case:10-> R with NO U + 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0': 0 + #Checks for Loads, Store, fetch Faults start from here + #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("URW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RX", dptw1cont) == 1 and get_pte_prop("UW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 5: expected: load-page-fault, store-page-fault, fetch-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("URW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RX", dptw0cont) == 1 and get_pte_prop("UW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +U_bit_unset_in_SMode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + csr_comb: + #Check that the satp is active --> in U mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. + 'mode == "S" and len_{i,d}ptw == {1,2}': 0 + # Test Case:1 + 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 1 and get_pte_prop("U", $1ptw1cont) == 0 and $1ptw0cont == None': 0 + # Test Case:2 + 'mode == "S" and get_pte_prop("X", {i, d}ptw1cont) == 1 and get_pte_prop("URW", $1ptw1cont) == 0 and $1ptw0cont == None': 0 + # Test Case:3 + 'mode == "S" and get_pte_prop("RX", {i, d}ptw1cont) == 1 and get_pte_prop("UW", $1ptw1cont) == 0 and $1ptw0cont == None': 0 + # Test Case:4 + 'mode == "S" and get_pte_prop("RW", dptw1cont) == 1 and get_pte_prop("UX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:5 + 'mode == "S" and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:6 + 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $1ptw0cont) == 1 and get_pte_prop("U", $1ptw0cont) == 0 ': 0 + # Test Case:7 + 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("X", $1ptw0cont) == 1 and get_pte_prop("URW", $1ptw0cont) == 0': 0 + # Test Case:8 + 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RX", $1ptw0cont) == 1 and get_pte_prop("UW", $1ptw0cont) == 0': 0 + # Test Case:9 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RW", dptw0cont) == 1 and get_pte_prop("UX", dptw0cont) == 0': 0 + # Test Case:10 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0': 0 + #Checks for Load, store, fetch page faults start from here + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("URW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("RX", dptw1cont) == 1 and get_pte_prop("UW", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Test Case 2: expected: load-page-fault, store-page-fault + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("URW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + #Test Case 3: expected: store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RX", dptw0cont) == 1 and get_pte_prop("UW", dptw0cont) == 0 and mcause == 15': 0 + #Test Case 5: expected: fetch-page-fault, store-page-fault + 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0 and mcause == 15': 0 + #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S new file mode 100644 index 000000000..f02cc4aea --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S @@ -0,0 +1,358 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. +// +// Access and Dirty Bit Test in S-Mode with Hardware Update +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: HART updates the PTE by setting the D-bit. No fault should occur. +// +// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: No fault should occur. +// +// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: HART updates the PTE by setting the A-bit. No fault should occur. +// +// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. +// +// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: HART updates the PTE by setting the D-bit. No fault should occur. +// +// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: No fault should occur. +// +// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: HART updates the PTE by setting the A-bit. No fault should occur. +// +// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. +// +// Total Expected Faults: 0 +// ---------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_hart_upd_S_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +// ------------------------------------------------------------------------------------------------------------ +// Macro to test RWX (read, write, execute) permissions. +// ------------------------------------------------------------------------------------------------------------ +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +// ------------------------------------------------------------------------------------------------------------ +// Macro to run the test +// ------------------------------------------------------------------------------------------------------------ +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A| PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S new file mode 100644 index 000000000..890e69ade --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S @@ -0,0 +1,358 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. +// +// Access and Dirty Bit Test in U-Mode with Hardware Update +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: HART updates the PTE by setting the D-bit. No fault should occur. +// +// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: No fault should occur. +// +// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: HART updates the PTE by setting the A-bit. No fault should occur. +// +// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. +// +// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: HART updates the PTE by setting the D-bit. No fault should occur. +// +// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: No fault should occur. +// +// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: HART updates the PTE by setting the A-bit. No fault should occur. +// +// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. +// +// Total Expected Faults: 0 +// ---------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_hart_upd_U_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +// ------------------------------------------------------------------------------------------------------------ +// Macro to test RWX (read, write, execute) permissions. +// ------------------------------------------------------------------------------------------------------------ +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +// ------------------------------------------------------------------------------------------------------------ +// Macro to run the test +// ------------------------------------------------------------------------------------------------------------ +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S new file mode 100644 index 000000000..3d1ca4b27 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S @@ -0,0 +1,328 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the physical address in S mode in the SV-32 virtual memory system. +// +// PMP Permissions on the physical address test in S mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section Physical address is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa_S_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our region of interest has the lablel = rvtest_data_1_l1 and rvtest_data_1_l0 +The rvtest_data_1_l0 comes right after the rvtest_data_1_l1 +Therefore, Region 1 can be configured with RWX with TOR with the label rvtest_slvl1_pg_tbl -> next label after the rvtest_data_1_l0 +Then, Region 2 can be configured with NO RWX and as a TOR region consisting of rvtest_data_1_l1 and rvtest_data_1_l0 +Then, Region 3 till 0xFFFFFFFF with RWX and as a TOR Region above rvtest_data_1_l0. +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_data_1_l1) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the TOR region sized 4MB+4KB labeled as rvtest_data_1_l1 + rvtest_data_1_l0 + LA (t0, return_page_level_1_with_PMP_perms) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg01 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg02 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(return_page_level_1_with_PMP_perms, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(return_page_level_0_with_PMP_perms, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +.align 22 + +return_page_level_1_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +return_page_level_0_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S new file mode 100644 index 000000000..c58649896 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S @@ -0,0 +1,328 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the physical address in U mode in the SV-32 virtual memory system. +// +// PMP Permissions on the physical address test in U mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section Physical address is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa_U_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our region of interest has the lablel = rvtest_data_1_l1 and rvtest_data_1_l0 +The rvtest_data_1_l0 comes right after the rvtest_data_1_l1 +Therefore, Region 1 can be configured with RWX with TOR with the label rvtest_slvl1_pg_tbl -> next label after the rvtest_data_1_l0 +Then, Region 2 can be configured with NO RWX and as a TOR region consisting of rvtest_data_1_l1 and rvtest_data_1_l0 +Then, Region 3 till 0xFFFFFFFF with RWX and as a TOR Region above rvtest_data_1_l0. +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_data_1_l1) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the TOR region sized 4MB+4KB labeled as rvtest_data_1_l1 + rvtest_data_1_l0 + LA (t0, return_page_level_1_with_PMP_perms) //load the address of root page table + srli t0, t0, 2 + LI (t1, (PMP_TOR)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg01 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg02 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(return_page_level_1_with_PMP_perms, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(return_page_level_0_with_PMP_perms, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +.align 22 + +return_page_level_1_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +return_page_level_0_with_PMP_perms: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S new file mode 100644 index 000000000..f6cb0c663 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S @@ -0,0 +1,302 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in S mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in S mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section PTE is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte_S_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our data section maps to 0x91400000 which means the offset for root page table is 0x914 and 0x000 for the level1 page table. +Therefore, we will give RWX permission before this offset via TOR i.e., rvtest_Sroot_pg_tbl + 0x914 +For this region we will use NA4 and will give only X permissions. +After this region till 0xFFFFFFFF, RWX permissions via TOR +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_Sroot_pg_tbl) //load the address of root page table + LI (t1, 0x914) // ALL perms before the data section + add t0, t0, t1 + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the NAPOT region sized 4KB (0x1FF) labeled as + LI (t1, (PMP_NA4)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S new file mode 100644 index 000000000..f5edae29c --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S @@ -0,0 +1,302 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in U mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in U mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. Test Section PTE is given the PMP Permission = None, Level 1 +// expected: Load, store, fetch access faults +// 2. Test Section PTE is given the PMP Permission = None, Level 0 +// expected: Load, store, fetch access faults +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte_U_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + csrw satp, zero // write satp with all zeros (bare mode) +/* +Our data section maps to 0x91400000 which means the offset for root page table is 0x914 and 0x000 for the level1 page table. +Therefore, we will give RWX permission before this offset via TOR i.e., rvtest_Sroot_pg_tbl + 0x914 +For this region we will use NA4 and will give only X permissions. +After this region till 0xFFFFFFFF, RWX permissions via TOR +*/ + +// RWX permissions given to the TOR region before the root page table labeled as + LA (t0, rvtest_Sroot_pg_tbl) //load the address of root page table + LI (t1, 0x914) // ALL perms before the data section + add t0, t0, t1 + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 0 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr0, t0 // Load the address in the pmpaddr0 +// X permissions given to the NAPOT region sized 4KB (0x1FF) labeled as + LI (t1, (PMP_NA4)) //NO permissions given with TOR selected + slli t1, t1, 8 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr1, t0 // Load the address in the pmpaddr1 +// RWX permissions given to all the regions before 0xFFFFFFFF + li t0, ALL_F_S // load the address of the whole memory + srli t0, t0, 2 + LI (t1, (PMP_TOR | PMP_R | PMP_W | PMP_X)) //RWX permissions given with TOR selected + slli t1, t1, 16 // permissions stored in t1 + add t2, t1, t2 // t2 = pmpcfg00 + csrw pmpaddr2, t0 // Load the address in the pmpaddr0 + //Enable the PMP Configurations + csrw pmpcfg0, t2 //write the pmpcfg0 +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x917FF000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91800000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_D| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: NO RWX permissions given to the PMP Region | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_D| PTE_X |PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S new file mode 100644 index 000000000..8244af564 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S @@ -0,0 +1,372 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. +// +// Access and Dirty Bit Test in S-Mode with Software Update +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Store-page-fault +// +// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: No fault should occur. +// +// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Store-page-fault +// +// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: No fault should occur. +// +// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in S-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// Total Expected Faults: 14 +// ---------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd_S_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +// ------------------------------------------------------------------------------------------------------------ +// Macro to test RWX (read, write, execute) permissions. +// ------------------------------------------------------------------------------------------------------------ +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +// ------------------------------------------------------------------------------------------------------------ +// Macro to run the test +// ------------------------------------------------------------------------------------------------------------ +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = Store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S new file mode 100644 index 000000000..6b4a1fe0e --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S @@ -0,0 +1,372 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. +// +// Access and Dirty Bit Test in U-Mode with Software Update +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Store-page-fault +// +// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: No fault should occur. +// +// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Store-page-fault +// +// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: No fault should occur. +// +// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): +// Action: Access the page in U-Mode. +// Expected: Load-page-fault, Store-page-fault, Fetch-page-fault +// +// Total Expected Faults: 14 +// ---------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd_U_mode) + +RVTEST_SIGBASE( x13,signature_x13_1) +// ------------------------------------------------------------------------------------------------------------ +// Macro to test RWX (read, write, execute) permissions. +// ------------------------------------------------------------------------------------------------------------ +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +// ------------------------------------------------------------------------------------------------------------ +// Macro to run the test +// ------------------------------------------------------------------------------------------------------------ +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = Store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = Store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = Load-page-fault, Store-page-fault, Fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 //complete the 4KB permission memory range +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S new file mode 100644 index 000000000..fbf6ae1dd --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S @@ -0,0 +1,372 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. U bit is set for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: No Fault +// 2. U bit is set for the page at level 1 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 3. U bit is set for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Store-page-fault +// 4. U bit is set for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Fetch-page-fault +// 5. U bit is set for the page at level 1 with R Permissions (Read only page): +// Then, in U-Mode, the page is accessed --> required: fetch-page-fault, store-page-fault + +// 6. U bit is set for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: No Fault +// 7. U bit is set for the page at level 0 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 8. U bit is set for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Store-page-fault +// 9. U bit is set for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Fetch-page-fault +// 10. U bit is set for the page at level 0 with R Permissions (Read only page): +// Then, in U-Mode, the page is accessed --> required: fetch-page-fault, store-page-fault + +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_set_in_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +//Test Cases are checked in this macro by switching to the expected mode. +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit set | Test in U-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit set | Test in U-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit set | Test in U-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit set | Test in U-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit set | Test in U-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit set | Test in U-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit set | Test in U-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit set | Test in U-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4kB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit set | Test in U-Mode | R bit set | expected = Store-page-fault, fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit set | Test in U-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 64*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S new file mode 100644 index 000000000..4a79714c6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S @@ -0,0 +1,392 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. U bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No fault +// 2. U bit is UnSet for the page at level 1 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault +// 3. U bit is UnSet for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 4. U bit is UnSet for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 5. U bit is UnSet for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault + +// 6. U bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No fault +// 7. U bit is UnSet for the page at level 0 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault +// 8. U bit is UnSet for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 9. U bit is UnSet for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 10. U bit is UnSet for the page at level 0 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault + +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_unset_in_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit unset | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit unset | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit unset | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit unset | Test in S-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit unset | Test in S-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit unset | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit unset | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit unset | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit unset | Test in S-Mode | R bit set | expected = Store-page-fault, fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit unset | Test in S-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S new file mode 100644 index 000000000..ec43f6fe9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S @@ -0,0 +1,402 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ----------- +// This test is a part of the test plan for SV-32 based Virtual Memory System available at https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- 10.3 +// This assembly file tests the working of U bit. The test is organized in the following pattern: +// ------------------------------------------U bit Unset test in U Mode --------------------------------------------------- +// 1. U bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. U bit is UnSet for the page at level 1 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 3. U bit is UnSet for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 4. U bit is UnSet for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 5. U bit is UnSet for the page at level 1 with X Permissions (execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault + +// 6. U bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 7. U bit is UnSet for the page at level 0 with X Permissions (Execute only page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 8. U bit is UnSet for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 9. U bit is UnSet for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 10. U bit is UnSet for the page at level 0 with X Permissions (execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault + +// Total Expected Faults :: 30 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", U_bit_unset_in_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit Unset | Test in U-Mode | RWX bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit Unset | Test in U-Mode | RX bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit Unset | Test in U-Mode | RW bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit Unset | Test in U-Mode | RWX bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit Unset | Test in U-Mode | RX bit set | expected = Load, Store, Fetch Page Faults Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit Unset | Test in U-Mode | R bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit Unset | Test in U-Mode | X bit set | expected = Load, Store, Fetch Page Faults + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S new file mode 100644 index 000000000..9a89f4052 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S @@ -0,0 +1,278 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in S mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in S mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. V bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. V bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",invalid_pte_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S new file mode 100644 index 000000000..95207e64d --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S @@ -0,0 +1,279 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// This test verifies the functioning of the PMP Permissions on the PTE in U mode in the SV-32 virtual memory system. +// +// PMP Permissions on the Page Table Entry test in U mode +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------Invalid PTE test in U Mode --------------------------------------------------- +// 1. V bit is UnSet for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. V bit is UnSet for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", invalid_pte_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: V bit unset | Test in U-Mode | RWX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S new file mode 100644 index 000000000..788fa4c9f --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S @@ -0,0 +1,254 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. At level 1 with R,W,X Permissions; Misaligned rvtest_data_1_l1 (.align 12) (read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: Load Page Fault, store page fault, fetch page fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: R,W,X set and A, D bit set | Test in S-Mode | RWX bit set | expected = Fetch ,Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A| PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 12 //misaligned page + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S new file mode 100644 index 000000000..a65b84f84 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S @@ -0,0 +1,253 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. At level 1 with R,W,X Permissions; Misaligned rvtest_data_1_l1 (.align 12) (read, write, execute page): +// Then, in U-Mode, the page is accessed --> required: Load Page Fault, store page fault, fetch page fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: R,W,X set and A bit unset | Test in U-Mode | RWX bit set | expected = Fetch ,Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 12 //misaligned page + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S new file mode 100644 index 000000000..58c8aae13 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S @@ -0,0 +1,297 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. X bit is set and MXR bit in mstatus is unset for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: Load Page Fault, store page fault +// 2. X bit is set and MXR bit in mstatus is set for the page at level 1 with X Permissions (execute page, read page --> MXR Bit): +// Then, in S-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault + +// 3. X bit is set and MXR bit in mstatus is unset for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in S-Mode, the page is accessed --> required: Load Page Fault, store page fault + +// 4. X bit is set and MXR bit in mstatus is set for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in S-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: X bit set and MXR bit unset | Test in S-Mode | RWX bit set | expected = Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: X bit set and MXR bit set | Test in S-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: X bit set and MXR bit unset | Test in S-Mode | RWX bit set | expected = store, load page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrc mstatus,s7 // unset the mstatus.MXR = 0 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: X bit set and MXR bit set | Test in S-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S new file mode 100644 index 000000000..1b06d9910 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S @@ -0,0 +1,297 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. X bit is set and MXR bit in mstatus is unset for the page at level 1 with X Permissions (execute page): +// Then, in U-Mode, the page is accessed --> required: Load Page Fault, store page fault +// 2. X bit is set and MXR bit in mstatus is set for the page at level 1 with X Permissions (execute page, read page --> MXR Bit): +// Then, in U-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault + +// 3. X bit is set and MXR bit in mstatus is unset for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in U-Mode, the page is accessed --> required: Load Page Fault, store page fault + +// 4. X bit is set and MXR bit in mstatus is set for the page at level 0 with X Permissions (execute page, read page --> MXR Bit): +// Then, in U-Mode, the page is accessed --> required: No Load and Execute Page Fault, store page fault +// Total Expected Faults :: 6 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: X bit set and MXR bit unset | Test in U-Mode | RWX bit set | expected = Store, load page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: X bit set and MXR bit set | Test in U-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL1) + sfence.vma + + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: X bit set and MXR bit unset | Test in U-Mode | RWX bit set | expected = store, load page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrc mstatus,s7 // unset the mstatus.MXR = 0 + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: X bit set and MXR bit set | Test in U-Mode | X bit set | expected = store page fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + li s7, MSTATUS_MXR + csrs mstatus,s7 // set the mstatus.MXR = 1 + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S new file mode 100644 index 000000000..44a08ed20 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S @@ -0,0 +1,256 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. No RWX but only V bit is set for the PTE at Level 0: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in S-Mode | Only V bit set at Level 0 | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S new file mode 100644 index 000000000..5de93fb8b --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S @@ -0,0 +1,256 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. No RWX but only V bit is set for the PTE at Level 0: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 3 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- No RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in U-Mode | Only V bit set at Level 0 | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_U | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S new file mode 100644 index 000000000..e7acfd2af --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S @@ -0,0 +1,306 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. WX Permissions is Set for the page at level 1: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. W Permissions is Set for the page at level 1: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 3. WX Permissions is Set for the page at level 0: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 4. W Permissions is Set for the page at level 0: +// Then, in S-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in S-Mode | WX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in S-Mode | W bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in S-Mode | WX bit set | expected = WX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in S-Mode | WX bit set | expected = W fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S new file mode 100644 index 000000000..25827854c --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S @@ -0,0 +1,306 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. WX Permissions is Set for the page at level 1: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 2. W Permissions is Set for the page at level 1: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 3. WX Permissions is Set for the page at level 0: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// 4. W Permissions is Set for the page at level 0: +// Then, in U-Mode, the page is accessed --> required: Load-page-fault, Store-page-fault, Fetch-page-fault +// Total Expected Faults :: 12 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm_UMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in U-Mode | WX bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in U-Mode | W bit set | expected = RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in U-Mode | WX bit set | expected = WX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: Test in U-Mode | WX bit set | expected = W fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S new file mode 100644 index 000000000..7d32d10d2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S @@ -0,0 +1,422 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ----------- +// This test is a part of the test plan for SV-32 based Virtual Memory System available at https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- 10.3 +// This assembly file tests the working of U bit. The test is organized in the following: +// ------------------------------------------Sum bit test in S Mode --------------------------------------------------- +// 1. U bit is set and Sum bit in mstatus is set for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No Fault +// 2. U bit is set and Sum bit in mstatus is set for the page at level 1 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 3. U bit is set and Sum bit in mstatus is set for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 4. U bit is set and Sum bit in mstatus is set for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 5. U bit is set and Sum bit in mstatus is set for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault + +// 6. U bit is set and Sum bit in mstatus is set for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: No Fault +// 7. U bit is set and Sum bit in mstatus is set for the page at level 0 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault +// 8. U bit is set and Sum bit in mstatus is set for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: Store-page-fault +// 9. U bit is set and Sum bit in mstatus is set for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: Fetch-page-fault +// 10. U bit is set and Sum bit in mstatus is set for the page at level 0 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault + +// Total Expected Faults :: 18 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_sum_set_in_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit set | Test in S-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit set | Test in S-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit set | Test in S-Mode | R bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit set | Test in S-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + li s7, MSTATUS_SUM + csrs mstatus,s7 // set the mstatus.SUM = 1 + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S new file mode 100644 index 000000000..4648eeab0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S @@ -0,0 +1,402 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. U bit is set and Sum bit in mstatus is unset for the page at level 1 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 2. U bit is set and Sum bit in mstatus is unset for the page at level 1 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 3. U bit is set and Sum bit in mstatus is unset for the page at level 1 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 4. U bit is set and Sum bit in mstatus is unset for the page at level 1 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 5. U bit is set and Sum bit in mstatus is unset for the page at level 1 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault + +// 6. U bit is set and Sum bit in mstatus is unset for the page at level 0 with RWX Permissions (Read, write, execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 7. U bit is set and Sum bit in mstatus is unset for the page at level 0 with X Permissions (Execute only page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 8. U bit is set and Sum bit in mstatus is unset for the page at level 0 with R,X Permissions (Read, Execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 9. U bit is set and Sum bit in mstatus is unset for the page at level 0 with R,W Permissions (Read, Store page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault +// 10. U bit is set and Sum bit in mstatus is unset for the page at level 0 with X Permissions (execute page): +// Then, in S-Mode, the page is accessed --> required: load-page-fault, store-page-fault, Fetch Page Fault + +// Total Expected Faults :: 30 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",U_bit_no_sum_set_in_SMode) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 1 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 1 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 3: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 1 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 4: U bit set | Test in S-Mode | RW bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 1 -- R permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 5: U bit set | Test in S-Mode | X bit set | expected = fetch-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL1) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 6: U bit set | Test in S-Mode | RWX bit set | expected = No RWX fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 2 under test at level 0 -- X permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 7: U bit set | Test in S-Mode | X bit set | expected = Load, Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 3 under test at level 0 -- RX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 8: U bit set | Test in S-Mode | RX bit set | expected = Store Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_X | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 4 under test at level 0 -- RW permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 9: U bit set | Test in S-Mode | R bit set | expected = fetch-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 5 under test at level 0 -- W permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 10: U bit set | Test in S-Mode | X bit set | expected = load-page-fault, store-page-fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END + +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 85219aecbb2631d7db79dd7dd9c70bb90b6fc71a Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 11 Oct 2024 20:19:29 +0500 Subject: [PATCH 02/19] macro file updated and header_file added --- coverage/header_file.yaml | 948 +++++++++++++++++++++++++++++ riscv-test-suite/env/test_macros.h | 39 +- 2 files changed, 979 insertions(+), 8 deletions(-) create mode 100644 coverage/header_file.yaml diff --git a/coverage/header_file.yaml b/coverage/header_file.yaml new file mode 100644 index 000000000..fdfda6a47 --- /dev/null +++ b/coverage/header_file.yaml @@ -0,0 +1,948 @@ +common: + MSTATUS_UIE: 0x00000001 + MSTATUS_SIE: 0x00000002 + MSTATUS_HIE: 0x00000004 + MSTATUS_MIE: 0x00000008 + MSTATUS_UPIE: 0x00000010 + MSTATUS_SPIE: 0x00000020 + MSTATUS_HPIE: 0x00000040 + MSTATUS_MPIE: 0x00000080 + MSTATUS_SPP: 0x00000100 + MSTATUS_HPP: 0x00000600 + MSTATUS_MPP: 0x00001800 + MSTATUS_FS: 0x00006000 + MSTATUS_VS: 0x00000600 + MSTATUS_XS: 0x00018000 + MSTATUS_MPRV: 0x00020000 + MSTATUS_SUM: 0x00040000 + MSTATUS_MXR: 0x00080000 + MSTATUS_TVM: 0x00100000 + MSTATUS_TW: 0x00200000 + MSTATUS_TSR: 0x00400000 + MSTATUS32_SD: 0x80000000 + MSTATUS_UXL: 0x0000000300000000 + MSTATUS_SXL: 0x0000000C00000000 + MSTATUS64_SD: 0x8000000000000000 + SSTATUS_UIE: 0x00000001 + SSTATUS_SIE: 0x00000002 + SSTATUS_UPIE: 0x00000010 + SSTATUS_SPIE: 0x00000020 + SSTATUS_SPP: 0x00000100 + SSTATUS_FS: 0x00006000 + SSTATUS_XS: 0x00018000 + SSTATUS_SUM: 0x00040000 + SSTATUS_MXR: 0x00080000 + SSTATUS32_SD: 0x80000000 + SSTATUS_UXL: 0x0000000300000000 + SSTATUS64_SD: 0x8000000000000000 + DCSR_CAUSE_NONE: 0 + DCSR_CAUSE_SWBP: 1 + DCSR_CAUSE_HWBP: 2 + DCSR_CAUSE_DEBUGINT: 3 + DCSR_CAUSE_STEP: 4 + DCSR_CAUSE_HALT: 5 + MCONTROL_TYPE_NONE: 0 + MCONTROL_TYPE_MATCH: 2 + MCONTROL_ACTION_DEBUG_EXCEPTION: 0 + MCONTROL_ACTION_DEBUG_MODE: 1 + MCONTROL_ACTION_TRACE_START: 2 + MCONTROL_ACTION_TRACE_STOP: 3 + MCONTROL_ACTION_TRACE_EMIT: 4 + MCONTROL_MATCH_EQUAL: 0 + MCONTROL_MATCH_NAPOT: 1 + MCONTROL_MATCH_GE: 2 + MCONTROL_MATCH_LT: 3 + MCONTROL_MATCH_MASK_LOW: 4 + MCONTROL_MATCH_MASK_HIGH: 5 + SIP_SSIP: MIP_SSIP + SIP_STIP: MIP_STIP + PRV_U: 0 + PRV_S: 1 + PRV_H: 2 + PRV_M: 3 + SATP32_MODE: 0x80000000 + SATP32_ASID: 0x7FC00000 + SATP32_PPN: 0x003FFFFF + SATP64_MODE: 0xF000000000000000 + SATP64_ASID: 0x0FFFF00000000000 + SATP64_PPN: 0x00000FFFFFFFFFFF + SATP_MODE_OFF: 0 + SATP_MODE_SV32: 0x1 + SATP_MODE_SV39: 8 + SATP_MODE_SV48: 9 + SATP_MODE_SV57: 10 + SATP_MODE_SV64: 11 + PMP_R: 0x01 + PMP_W: 0x02 + PMP_X: 0x04 + PMP_A: 0x18 + PMP_L: 0x80 + PMP_SHIFT: 2 + PMP_TOR: 0x08 + PMP_NA4: 0x10 + PMP_NAPOT: 0x18 + IRQ_S_SOFT: 1 + IRQ_H_SOFT: 2 + IRQ_M_SOFT: 3 + IRQ_S_TIMER: 5 + IRQ_H_TIMER: 6 + IRQ_M_TIMER: 7 + IRQ_S_EXT: 9 + IRQ_H_EXT: 10 + IRQ_M_EXT: 11 + IRQ_COP: 12 + IRQ_HOST: 13 + DEFAULT_RSTVEC: 0x00001000 + CLINT_BASE: 0x02000000 + CLINT_SIZE: 0x000c0000 + EXT_IO_BASE: 0x40000000 + DRAM_BASE: 0x80000000 + PTE_V: 0x001 + PTE_R: 0x002 + PTE_W: 0x004 + PTE_X: 0x008 + PTE_U: 0x010 + PTE_G: 0x020 + PTE_A: 0x040 + PTE_D: 0x080 + PTE_SOFT: 0x300 + PTE_PPN_SHIFT: 10 + RISCV_PGSHIFT: 12 + MATCH_BEQ: 0x63 + MASK_BEQ: 0x707f + MATCH_BNE: 0x1063 + MASK_BNE: 0x707f + MATCH_BLT: 0x4063 + MASK_BLT: 0x707f + MATCH_BGE: 0x5063 + MASK_BGE: 0x707f + MATCH_BLTU: 0x6063 + MASK_BLTU: 0x707f + MATCH_BGEU: 0x7063 + MASK_BGEU: 0x707f + MATCH_JALR: 0x67 + MASK_JALR: 0x707f + MATCH_JAL: 0x6f + MASK_JAL: 0x7f + MATCH_LUI: 0x37 + MASK_LUI: 0x7f + MATCH_AUIPC: 0x17 + MASK_AUIPC: 0x7f + MATCH_ADDI: 0x13 + MASK_ADDI: 0x707f + MATCH_SLLI: 0x1013 + MASK_SLLI: 0xfc00707f + MATCH_SLTI: 0x2013 + MASK_SLTI: 0x707f + MATCH_SLTIU: 0x3013 + MASK_SLTIU: 0x707f + MATCH_XORI: 0x4013 + MASK_XORI: 0x707f + MATCH_SRLI: 0x5013 + MASK_SRLI: 0xfc00707f + MATCH_SRAI: 0x40005013 + MASK_SRAI: 0xfc00707f + MATCH_ORI: 0x6013 + MASK_ORI: 0x707f + MATCH_ANDI: 0x7013 + MASK_ANDI: 0x707f + MATCH_ADD: 0x33 + MASK_ADD: 0xfe00707f + MATCH_SUB: 0x40000033 + MASK_SUB: 0xfe00707f + MATCH_SLL: 0x1033 + MASK_SLL: 0xfe00707f + MATCH_SLT: 0x2033 + MASK_SLT: 0xfe00707f + MATCH_SLTU: 0x3033 + MASK_SLTU: 0xfe00707f + MATCH_XOR: 0x4033 + MASK_XOR: 0xfe00707f + MATCH_SRL: 0x5033 + MASK_SRL: 0xfe00707f + MATCH_SRA: 0x40005033 + MASK_SRA: 0xfe00707f + MATCH_OR: 0x6033 + MASK_OR: 0xfe00707f + MATCH_AND: 0x7033 + MASK_AND: 0xfe00707f + MATCH_ADDIW: 0x1b + MASK_ADDIW: 0x707f + MATCH_SLLIW: 0x101b + MASK_SLLIW: 0xfe00707f + MATCH_SRLIW: 0x501b + MASK_SRLIW: 0xfe00707f + MATCH_SRAIW: 0x4000501b + MASK_SRAIW: 0xfe00707f + MATCH_ADDW: 0x3b + MASK_ADDW: 0xfe00707f + MATCH_SUBW: 0x4000003b + MASK_SUBW: 0xfe00707f + MATCH_SLLW: 0x103b + MASK_SLLW: 0xfe00707f + MATCH_SRLW: 0x503b + MASK_SRLW: 0xfe00707f + MATCH_SRAW: 0x4000503b + MASK_SRAW: 0xfe00707f + MATCH_LB: 0x3 + MASK_LB: 0x707f + MATCH_LH: 0x1003 + MASK_LH: 0x707f + MATCH_LW: 0x2003 + MASK_LW: 0x707f + MATCH_LD: 0x3003 + MASK_LD: 0x707f + MATCH_LBU: 0x4003 + MASK_LBU: 0x707f + MATCH_LHU: 0x5003 + MASK_LHU: 0x707f + MATCH_LWU: 0x6003 + MASK_LWU: 0x707f + MATCH_SB: 0x23 + MASK_SB: 0x707f + MATCH_SH: 0x1023 + MASK_SH: 0x707f + MATCH_SW: 0x2023 + MASK_SW: 0x707f + MATCH_SD: 0x3023 + MASK_SD: 0x707f + MATCH_FENCE: 0xf + MASK_FENCE: 0x707f + MATCH_FENCE_I: 0x100f + MASK_FENCE_I: 0x707f + MATCH_MUL: 0x2000033 + MASK_MUL: 0xfe00707f + MATCH_MULH: 0x2001033 + MASK_MULH: 0xfe00707f + MATCH_MULHSU: 0x2002033 + MASK_MULHSU: 0xfe00707f + MATCH_MULHU: 0x2003033 + MASK_MULHU: 0xfe00707f + MATCH_DIV: 0x2004033 + MASK_DIV: 0xfe00707f + MATCH_DIVU: 0x2005033 + MASK_DIVU: 0xfe00707f + MATCH_REM: 0x2006033 + MASK_REM: 0xfe00707f + MATCH_REMU: 0x2007033 + MASK_REMU: 0xfe00707f + MATCH_MULW: 0x200003b + MASK_MULW: 0xfe00707f + MATCH_DIVW: 0x200403b + MASK_DIVW: 0xfe00707f + MATCH_DIVUW: 0x200503b + MASK_DIVUW: 0xfe00707f + MATCH_REMW: 0x200603b + MASK_REMW: 0xfe00707f + MATCH_REMUW: 0x200703b + MASK_REMUW: 0xfe00707f + MATCH_AMOADD_W: 0x202f + MASK_AMOADD_W: 0xf800707f + MATCH_AMOXOR_W: 0x2000202f + MASK_AMOXOR_W: 0xf800707f + MATCH_AMOOR_W: 0x4000202f + MASK_AMOOR_W: 0xf800707f + MATCH_AMOAND_W: 0x6000202f + MASK_AMOAND_W: 0xf800707f + MATCH_AMOMIN_W: 0x8000202f + MASK_AMOMIN_W: 0xf800707f + MATCH_AMOMAX_W: 0xa000202f + MASK_AMOMAX_W: 0xf800707f + MATCH_AMOMINU_W: 0xc000202f + MASK_AMOMINU_W: 0xf800707f + MATCH_AMOMAXU_W: 0xe000202f + MASK_AMOMAXU_W: 0xf800707f + MATCH_AMOSWAP_W: 0x800202f + MASK_AMOSWAP_W: 0xf800707f + MATCH_LR_W: 0x1000202f + MASK_LR_W: 0xf9f0707f + MATCH_SC_W: 0x1800202f + MASK_SC_W: 0xf800707f + MATCH_AMOADD_D: 0x302f + MASK_AMOADD_D: 0xf800707f + MATCH_AMOXOR_D: 0x2000302f + MASK_AMOXOR_D: 0xf800707f + MATCH_AMOOR_D: 0x4000302f + MASK_AMOOR_D: 0xf800707f + MATCH_AMOAND_D: 0x6000302f + MASK_AMOAND_D: 0xf800707f + MATCH_AMOMIN_D: 0x8000302f + MASK_AMOMIN_D: 0xf800707f + MATCH_AMOMAX_D: 0xa000302f + MASK_AMOMAX_D: 0xf800707f + MATCH_AMOMINU_D: 0xc000302f + MASK_AMOMINU_D: 0xf800707f + MATCH_AMOMAXU_D: 0xe000302f + MASK_AMOMAXU_D: 0xf800707f + MATCH_AMOSWAP_D: 0x800302f + MASK_AMOSWAP_D: 0xf800707f + MATCH_LR_D: 0x1000302f + MASK_LR_D: 0xf9f0707f + MATCH_SC_D: 0x1800302f + MASK_SC_D: 0xf800707f + MATCH_ECALL: 0x73 + MASK_ECALL: 0xffffffff + MATCH_EBREAK: 0x100073 + MASK_EBREAK: 0xffffffff + MATCH_URET: 0x200073 + MASK_URET: 0xffffffff + MATCH_SRET: 0x10200073 + MASK_SRET: 0xffffffff + MATCH_MRET: 0x30200073 + MASK_MRET: 0xffffffff + MATCH_DRET: 0x7b200073 + MASK_DRET: 0xffffffff + MATCH_SFENCE_VMA: 0x12000073 + MASK_SFENCE_VMA: 0xfe007fff + MATCH_WFI: 0x10500073 + MASK_WFI: 0xffffffff + MATCH_CSRRW: 0x1073 + MASK_CSRRW: 0x707f + MATCH_CSRRS: 0x2073 + MASK_CSRRS: 0x707f + MATCH_CSRRC: 0x3073 + MASK_CSRRC: 0x707f + MATCH_CSRRWI: 0x5073 + MASK_CSRRWI: 0x707f + MATCH_CSRRSI: 0x6073 + MASK_CSRRSI: 0x707f + MATCH_CSRRCI: 0x7073 + MASK_CSRRCI: 0x707f + MATCH_FADD_S: 0x53 + MASK_FADD_S: 0xfe00007f + MATCH_FSUB_S: 0x8000053 + MASK_FSUB_S: 0xfe00007f + MATCH_FMUL_S: 0x10000053 + MASK_FMUL_S: 0xfe00007f + MATCH_FDIV_S: 0x18000053 + MASK_FDIV_S: 0xfe00007f + MATCH_FSGNJ_S: 0x20000053 + MASK_FSGNJ_S: 0xfe00707f + MATCH_FSGNJN_S: 0x20001053 + MASK_FSGNJN_S: 0xfe00707f + MATCH_FSGNJX_S: 0x20002053 + MASK_FSGNJX_S: 0xfe00707f + MATCH_FMIN_S: 0x28000053 + MASK_FMIN_S: 0xfe00707f + MATCH_FMAX_S: 0x28001053 + MASK_FMAX_S: 0xfe00707f + MATCH_FSQRT_S: 0x58000053 + MASK_FSQRT_S: 0xfff0007f + MATCH_FADD_D: 0x2000053 + MASK_FADD_D: 0xfe00007f + MATCH_FSUB_D: 0xa000053 + MASK_FSUB_D: 0xfe00007f + MATCH_FMUL_D: 0x12000053 + MASK_FMUL_D: 0xfe00007f + MATCH_FDIV_D: 0x1a000053 + MASK_FDIV_D: 0xfe00007f + MATCH_FSGNJ_D: 0x22000053 + MASK_FSGNJ_D: 0xfe00707f + MATCH_FSGNJN_D: 0x22001053 + MASK_FSGNJN_D: 0xfe00707f + MATCH_FSGNJX_D: 0x22002053 + MASK_FSGNJX_D: 0xfe00707f + MATCH_FMIN_D: 0x2a000053 + MASK_FMIN_D: 0xfe00707f + MATCH_FMAX_D: 0x2a001053 + MASK_FMAX_D: 0xfe00707f + MATCH_FCVT_S_D: 0x40100053 + MASK_FCVT_S_D: 0xfff0007f + MATCH_FCVT_D_S: 0x42000053 + MASK_FCVT_D_S: 0xfff0007f + MATCH_FSQRT_D: 0x5a000053 + MASK_FSQRT_D: 0xfff0007f + MATCH_FADD_Q: 0x6000053 + MASK_FADD_Q: 0xfe00007f + MATCH_FSUB_Q: 0xe000053 + MASK_FSUB_Q: 0xfe00007f + MATCH_FMUL_Q: 0x16000053 + MASK_FMUL_Q: 0xfe00007f + MATCH_FDIV_Q: 0x1e000053 + MASK_FDIV_Q: 0xfe00007f + MATCH_FSGNJ_Q: 0x26000053 + MASK_FSGNJ_Q: 0xfe00707f + MATCH_FSGNJN_Q: 0x26001053 + MASK_FSGNJN_Q: 0xfe00707f + MATCH_FSGNJX_Q: 0x26002053 + MASK_FSGNJX_Q: 0xfe00707f + MATCH_FMIN_Q: 0x2e000053 + MASK_FMIN_Q: 0xfe00707f + MATCH_FMAX_Q: 0x2e001053 + MASK_FMAX_Q: 0xfe00707f + MATCH_FCVT_S_Q: 0x40300053 + MASK_FCVT_S_Q: 0xfff0007f + MATCH_FCVT_Q_S: 0x46000053 + MASK_FCVT_Q_S: 0xfff0007f + MATCH_FCVT_D_Q: 0x42300053 + MASK_FCVT_D_Q: 0xfff0007f + MATCH_FCVT_Q_D: 0x46100053 + MASK_FCVT_Q_D: 0xfff0007f + MATCH_FSQRT_Q: 0x5e000053 + MASK_FSQRT_Q: 0xfff0007f + MATCH_FLE_S: 0xa0000053 + MASK_FLE_S: 0xfe00707f + MATCH_FLT_S: 0xa0001053 + MASK_FLT_S: 0xfe00707f + MATCH_FEQ_S: 0xa0002053 + MASK_FEQ_S: 0xfe00707f + MATCH_FLE_D: 0xa2000053 + MASK_FLE_D: 0xfe00707f + MATCH_FLT_D: 0xa2001053 + MASK_FLT_D: 0xfe00707f + MATCH_FEQ_D: 0xa2002053 + MASK_FEQ_D: 0xfe00707f + MATCH_FLE_Q: 0xa6000053 + MASK_FLE_Q: 0xfe00707f + MATCH_FLT_Q: 0xa6001053 + MASK_FLT_Q: 0xfe00707f + MATCH_FEQ_Q: 0xa6002053 + MASK_FEQ_Q: 0xfe00707f + MATCH_FCVT_W_S: 0xc0000053 + MASK_FCVT_W_S: 0xfff0007f + MATCH_FCVT_WU_S: 0xc0100053 + MASK_FCVT_WU_S: 0xfff0007f + MATCH_FCVT_L_S: 0xc0200053 + MASK_FCVT_L_S: 0xfff0007f + MATCH_FCVT_LU_S: 0xc0300053 + MASK_FCVT_LU_S: 0xfff0007f + MATCH_FMV_X_W: 0xe0000053 + MASK_FMV_X_W: 0xfff0707f + MATCH_FCLASS_S: 0xe0001053 + MASK_FCLASS_S: 0xfff0707f + MATCH_FCVT_W_D: 0xc2000053 + MASK_FCVT_W_D: 0xfff0007f + MATCH_FCVT_WU_D: 0xc2100053 + MASK_FCVT_WU_D: 0xfff0007f + MATCH_FCVT_L_D: 0xc2200053 + MASK_FCVT_L_D: 0xfff0007f + MATCH_FCVT_LU_D: 0xc2300053 + MASK_FCVT_LU_D: 0xfff0007f + MATCH_FMV_X_D: 0xe2000053 + MASK_FMV_X_D: 0xfff0707f + MATCH_FCLASS_D: 0xe2001053 + MASK_FCLASS_D: 0xfff0707f + MATCH_FCVT_W_Q: 0xc6000053 + MASK_FCVT_W_Q: 0xfff0007f + MATCH_FCVT_WU_Q: 0xc6100053 + MASK_FCVT_WU_Q: 0xfff0007f + MATCH_FCVT_L_Q: 0xc6200053 + MASK_FCVT_L_Q: 0xfff0007f + MATCH_FCVT_LU_Q: 0xc6300053 + MASK_FCVT_LU_Q: 0xfff0007f + MATCH_FMV_X_Q: 0xe6000053 + MASK_FMV_X_Q: 0xfff0707f + MATCH_FCLASS_Q: 0xe6001053 + MASK_FCLASS_Q: 0xfff0707f + MATCH_FCVT_S_W: 0xd0000053 + MASK_FCVT_S_W: 0xfff0007f + MATCH_FCVT_S_WU: 0xd0100053 + MASK_FCVT_S_WU: 0xfff0007f + MATCH_FCVT_S_L: 0xd0200053 + MASK_FCVT_S_L: 0xfff0007f + MATCH_FCVT_S_LU: 0xd0300053 + MASK_FCVT_S_LU: 0xfff0007f + MATCH_FMV_W_X: 0xf0000053 + MASK_FMV_W_X: 0xfff0707f + MATCH_FCVT_D_W: 0xd2000053 + MASK_FCVT_D_W: 0xfff0007f + MATCH_FCVT_D_WU: 0xd2100053 + MASK_FCVT_D_WU: 0xfff0007f + MATCH_FCVT_D_L: 0xd2200053 + MASK_FCVT_D_L: 0xfff0007f + MATCH_FCVT_D_LU: 0xd2300053 + MASK_FCVT_D_LU: 0xfff0007f + MATCH_FMV_D_X: 0xf2000053 + MASK_FMV_D_X: 0xfff0707f + MATCH_FCVT_Q_W: 0xd6000053 + MASK_FCVT_Q_W: 0xfff0007f + MATCH_FCVT_Q_WU: 0xd6100053 + MASK_FCVT_Q_WU: 0xfff0007f + MATCH_FCVT_Q_L: 0xd6200053 + MASK_FCVT_Q_L: 0xfff0007f + MATCH_FCVT_Q_LU: 0xd6300053 + MASK_FCVT_Q_LU: 0xfff0007f + MATCH_FMV_Q_X: 0xf6000053 + MASK_FMV_Q_X: 0xfff0707f + MATCH_FLW: 0x2007 + MASK_FLW: 0x707f + MATCH_FLD: 0x3007 + MASK_FLD: 0x707f + MATCH_FLQ: 0x4007 + MASK_FLQ: 0x707f + MATCH_FSW: 0x2027 + MASK_FSW: 0x707f + MATCH_FSD: 0x3027 + MASK_FSD: 0x707f + MATCH_FSQ: 0x4027 + MASK_FSQ: 0x707f + MATCH_FMADD_S: 0x43 + MASK_FMADD_S: 0x600007f + MATCH_FMSUB_S: 0x47 + MASK_FMSUB_S: 0x600007f + MATCH_FNMSUB_S: 0x4b + MASK_FNMSUB_S: 0x600007f + MATCH_FNMADD_S: 0x4f + MASK_FNMADD_S: 0x600007f + MATCH_FMADD_D: 0x2000043 + MASK_FMADD_D: 0x600007f + MATCH_FMSUB_D: 0x2000047 + MASK_FMSUB_D: 0x600007f + MATCH_FNMSUB_D: 0x200004b + MASK_FNMSUB_D: 0x600007f + MATCH_FNMADD_D: 0x200004f + MASK_FNMADD_D: 0x600007f + MATCH_FMADD_Q: 0x6000043 + MASK_FMADD_Q: 0x600007f + MATCH_FMSUB_Q: 0x6000047 + MASK_FMSUB_Q: 0x600007f + MATCH_FNMSUB_Q: 0x600004b + MASK_FNMSUB_Q: 0x600007f + MATCH_FNMADD_Q: 0x600004f + MASK_FNMADD_Q: 0x600007f + MATCH_C_NOP: 0x1 + MASK_C_NOP: 0xffff + MATCH_C_ADDI16SP: 0x6101 + MASK_C_ADDI16SP: 0xef83 + MATCH_C_JR: 0x8002 + MASK_C_JR: 0xf07f + MATCH_C_JALR: 0x9002 + MASK_C_JALR: 0xf07f + MATCH_C_EBREAK: 0x9002 + MASK_C_EBREAK: 0xffff + MATCH_C_LD: 0x6000 + MASK_C_LD: 0xe003 + MATCH_C_SD: 0xe000 + MASK_C_SD: 0xe003 + MATCH_C_ADDIW: 0x2001 + MASK_C_ADDIW: 0xe003 + MATCH_C_LDSP: 0x6002 + MASK_C_LDSP: 0xe003 + MATCH_C_SDSP: 0xe002 + MASK_C_SDSP: 0xe003 + MATCH_C_ADDI4SPN: 0x0 + MASK_C_ADDI4SPN: 0xe003 + MATCH_C_FLD: 0x2000 + MASK_C_FLD: 0xe003 + MATCH_C_LW: 0x4000 + MASK_C_LW: 0xe003 + MATCH_C_FLW: 0x6000 + MASK_C_FLW: 0xe003 + MATCH_C_FSD: 0xa000 + MASK_C_FSD: 0xe003 + MATCH_C_SW: 0xc000 + MASK_C_SW: 0xe003 + MATCH_C_FSW: 0xe000 + MASK_C_FSW: 0xe003 + MATCH_C_ADDI: 0x1 + MASK_C_ADDI: 0xe003 + MATCH_C_JAL: 0x2001 + MASK_C_JAL: 0xe003 + MATCH_C_LI: 0x4001 + MASK_C_LI: 0xe003 + MATCH_C_LUI: 0x6001 + MASK_C_LUI: 0xe003 + MATCH_C_SRLI: 0x8001 + MASK_C_SRLI: 0xec03 + MATCH_C_SRAI: 0x8401 + MASK_C_SRAI: 0xec03 + MATCH_C_ANDI: 0x8801 + MASK_C_ANDI: 0xec03 + MATCH_C_SUB: 0x8c01 + MASK_C_SUB: 0xfc63 + MATCH_C_XOR: 0x8c21 + MASK_C_XOR: 0xfc63 + MATCH_C_OR: 0x8c41 + MASK_C_OR: 0xfc63 + MATCH_C_AND: 0x8c61 + MASK_C_AND: 0xfc63 + MATCH_C_SUBW: 0x9c01 + MASK_C_SUBW: 0xfc63 + MATCH_C_ADDW: 0x9c21 + MASK_C_ADDW: 0xfc63 + MATCH_C_J: 0xa001 + MASK_C_J: 0xe003 + MATCH_C_BEQZ: 0xc001 + MASK_C_BEQZ: 0xe003 + MATCH_C_BNEZ: 0xe001 + MASK_C_BNEZ: 0xe003 + MATCH_C_SLLI: 0x2 + MASK_C_SLLI: 0xe003 + MATCH_C_FLDSP: 0x2002 + MASK_C_FLDSP: 0xe003 + MATCH_C_LWSP: 0x4002 + MASK_C_LWSP: 0xe003 + MATCH_C_FLWSP: 0x6002 + MASK_C_FLWSP: 0xe003 + MATCH_C_MV: 0x8002 + MASK_C_MV: 0xf003 + MATCH_C_ADD: 0x9002 + MASK_C_ADD: 0xf003 + MATCH_C_FSDSP: 0xa002 + MASK_C_FSDSP: 0xe003 + MATCH_C_SWSP: 0xc002 + MASK_C_SWSP: 0xe003 + MATCH_C_FSWSP: 0xe002 + MASK_C_FSWSP: 0xe003 + MATCH_CUSTOM0: 0xb + MASK_CUSTOM0: 0x707f + MATCH_CUSTOM0_RS1: 0x200b + MASK_CUSTOM0_RS1: 0x707f + MATCH_CUSTOM0_RS1_RS2: 0x300b + MASK_CUSTOM0_RS1_RS2: 0x707f + MATCH_CUSTOM0_RD: 0x400b + MASK_CUSTOM0_RD: 0x707f + MATCH_CUSTOM0_RD_RS1: 0x600b + MASK_CUSTOM0_RD_RS1: 0x707f + MATCH_CUSTOM0_RD_RS1_RS2: 0x700b + MASK_CUSTOM0_RD_RS1_RS2: 0x707f + MATCH_CUSTOM1: 0x2b + MASK_CUSTOM1: 0x707f + MATCH_CUSTOM1_RS1: 0x202b + MASK_CUSTOM1_RS1: 0x707f + MATCH_CUSTOM1_RS1_RS2: 0x302b + MASK_CUSTOM1_RS1_RS2: 0x707f + MATCH_CUSTOM1_RD: 0x402b + MASK_CUSTOM1_RD: 0x707f + MATCH_CUSTOM1_RD_RS1: 0x602b + MASK_CUSTOM1_RD_RS1: 0x707f + MATCH_CUSTOM1_RD_RS1_RS2: 0x702b + MASK_CUSTOM1_RD_RS1_RS2: 0x707f + MATCH_CUSTOM2: 0x5b + MASK_CUSTOM2: 0x707f + MATCH_CUSTOM2_RS1: 0x205b + MASK_CUSTOM2_RS1: 0x707f + MATCH_CUSTOM2_RS1_RS2: 0x305b + MASK_CUSTOM2_RS1_RS2: 0x707f + MATCH_CUSTOM2_RD: 0x405b + MASK_CUSTOM2_RD: 0x707f + MATCH_CUSTOM2_RD_RS1: 0x605b + MASK_CUSTOM2_RD_RS1: 0x707f + MATCH_CUSTOM2_RD_RS1_RS2: 0x705b + MASK_CUSTOM2_RD_RS1_RS2: 0x707f + MATCH_CUSTOM3: 0x7b + MASK_CUSTOM3: 0x707f + MATCH_CUSTOM3_RS1: 0x207b + MASK_CUSTOM3_RS1: 0x707f + MATCH_CUSTOM3_RS1_RS2: 0x307b + MASK_CUSTOM3_RS1_RS2: 0x707f + MATCH_CUSTOM3_RD: 0x407b + MASK_CUSTOM3_RD: 0x707f + MATCH_CUSTOM3_RD_RS1: 0x607b + MASK_CUSTOM3_RD_RS1: 0x707f + MATCH_CUSTOM3_RD_RS1_RS2: 0x707b + MASK_CUSTOM3_RD_RS1_RS2: 0x707f + CSR_FFLAGS: 0x1 + CSR_FRM: 0x2 + CSR_FCSR: 0x3 + CSR_CYCLE: 0xc00 + CSR_TIME: 0xc01 + CSR_INSTRET: 0xc02 + CSR_HEDELEG: 0x602 + CSR_HPMCOUNTER3: 0xc03 + CSR_HPMCOUNTER4: 0xc04 + CSR_HPMCOUNTER5: 0xc05 + CSR_HPMCOUNTER6: 0xc06 + CSR_HPMCOUNTER7: 0xc07 + CSR_HPMCOUNTER8: 0xc08 + CSR_HPMCOUNTER9: 0xc09 + CSR_HPMCOUNTER10: 0xc0a + CSR_HPMCOUNTER11: 0xc0b + CSR_HPMCOUNTER12: 0xc0c + CSR_HPMCOUNTER13: 0xc0d + CSR_HPMCOUNTER14: 0xc0e + CSR_HPMCOUNTER15: 0xc0f + CSR_HPMCOUNTER16: 0xc10 + CSR_HPMCOUNTER17: 0xc11 + CSR_HPMCOUNTER18: 0xc12 + CSR_HPMCOUNTER19: 0xc13 + CSR_HPMCOUNTER20: 0xc14 + CSR_HPMCOUNTER21: 0xc15 + CSR_HPMCOUNTER22: 0xc16 + CSR_HPMCOUNTER23: 0xc17 + CSR_HPMCOUNTER24: 0xc18 + CSR_HPMCOUNTER25: 0xc19 + CSR_HPMCOUNTER26: 0xc1a + CSR_HPMCOUNTER27: 0xc1b + CSR_HPMCOUNTER28: 0xc1c + CSR_HPMCOUNTER29: 0xc1d + CSR_HPMCOUNTER30: 0xc1e + CSR_HPMCOUNTER31: 0xc1f + CSR_VSATP: 0x280 + CSR_HSTATUS: 0x600 + CSR_SSTATUS: 0x100 + CSR_SIE: 0x104 + CSR_STVEC: 0x105 + CSR_SCOUNTEREN: 0x106 + CSR_SSCRATCH: 0x140 + CSR_SEPC: 0x141 + CSR_SCAUSE: 0x142 + CSR_STVAL: 0x143 + CSR_SIP: 0x144 + CSR_SATP: 0x180 + CSR_SEDELEG: 0x102 + CSR_MSTATUS: 0x300 + CSR_MSTATUSH: 0x310 + CSR_MISA: 0x301 + CSR_MEDELEG: 0x302 + CSR_MIDELEG: 0x303 + CSR_MIE: 0x304 + CSR_MTVEC: 0x305 + CSR_MCOUNTEREN: 0x306 + CSR_MSCRATCH: 0x340 + CSR_MEPC: 0x341 + CSR_MCAUSE: 0x342 + CSR_MTVAL: 0x343 + CSR_MIP: 0x344 + CSR_PMPCFG0: 0x3a0 + CSR_PMPCFG1: 0x3a1 + CSR_PMPCFG2: 0x3a2 + CSR_PMPCFG3: 0x3a3 + CSR_PMPADDR0: 0x3b0 + CSR_PMPADDR1: 0x3b1 + CSR_PMPADDR2: 0x3b2 + CSR_PMPADDR3: 0x3b3 + CSR_PMPADDR4: 0x3b4 + CSR_PMPADDR5: 0x3b5 + CSR_PMPADDR6: 0x3b6 + CSR_PMPADDR7: 0x3b7 + CSR_PMPADDR8: 0x3b8 + CSR_PMPADDR9: 0x3b9 + CSR_PMPADDR10: 0x3ba + CSR_PMPADDR11: 0x3bb + CSR_PMPADDR12: 0x3bc + CSR_PMPADDR13: 0x3bd + CSR_PMPADDR14: 0x3be + CSR_PMPADDR15: 0x3bf + CSR_TSELECT: 0x7a0 + CSR_TDATA1: 0x7a1 + CSR_TDATA2: 0x7a2 + CSR_TDATA3: 0x7a3 + CSR_DCSR: 0x7b0 + CSR_DPC: 0x7b1 + CSR_DSCRATCH: 0x7b2 + CSR_MCYCLE: 0xb00 + CSR_MINSTRET: 0xb02 + CSR_MHPMCOUNTER3: 0xb03 + CSR_MHPMCOUNTER4: 0xb04 + CSR_MHPMCOUNTER5: 0xb05 + CSR_MHPMCOUNTER6: 0xb06 + CSR_MHPMCOUNTER7: 0xb07 + CSR_MHPMCOUNTER8: 0xb08 + CSR_MHPMCOUNTER9: 0xb09 + CSR_MHPMCOUNTER10: 0xb0a + CSR_MHPMCOUNTER11: 0xb0b + CSR_MHPMCOUNTER12: 0xb0c + CSR_MHPMCOUNTER13: 0xb0d + CSR_MHPMCOUNTER14: 0xb0e + CSR_MHPMCOUNTER15: 0xb0f + CSR_MHPMCOUNTER16: 0xb10 + CSR_MHPMCOUNTER17: 0xb11 + CSR_MHPMCOUNTER18: 0xb12 + CSR_MHPMCOUNTER19: 0xb13 + CSR_MHPMCOUNTER20: 0xb14 + CSR_MHPMCOUNTER21: 0xb15 + CSR_MHPMCOUNTER22: 0xb16 + CSR_MHPMCOUNTER23: 0xb17 + CSR_MHPMCOUNTER24: 0xb18 + CSR_MHPMCOUNTER25: 0xb19 + CSR_MHPMCOUNTER26: 0xb1a + CSR_MHPMCOUNTER27: 0xb1b + CSR_MHPMCOUNTER28: 0xb1c + CSR_MHPMCOUNTER29: 0xb1d + CSR_MHPMCOUNTER30: 0xb1e + CSR_MHPMCOUNTER31: 0xb1f + CSR_MHPMEVENT3: 0x323 + CSR_MHPMEVENT4: 0x324 + CSR_MHPMEVENT5: 0x325 + CSR_MHPMEVENT6: 0x326 + CSR_MHPMEVENT7: 0x327 + CSR_MHPMEVENT8: 0x328 + CSR_MHPMEVENT9: 0x329 + CSR_MHPMEVENT10: 0x32a + CSR_MHPMEVENT11: 0x32b + CSR_MHPMEVENT12: 0x32c + CSR_MHPMEVENT13: 0x32d + CSR_MHPMEVENT14: 0x32e + CSR_MHPMEVENT15: 0x32f + CSR_MHPMEVENT16: 0x330 + CSR_MHPMEVENT17: 0x331 + CSR_MHPMEVENT18: 0x332 + CSR_MHPMEVENT19: 0x333 + CSR_MHPMEVENT20: 0x334 + CSR_MHPMEVENT21: 0x335 + CSR_MHPMEVENT22: 0x336 + CSR_MHPMEVENT23: 0x337 + CSR_MHPMEVENT24: 0x338 + CSR_MHPMEVENT25: 0x339 + CSR_MHPMEVENT26: 0x33a + CSR_MHPMEVENT27: 0x33b + CSR_MHPMEVENT28: 0x33c + CSR_MHPMEVENT29: 0x33d + CSR_MHPMEVENT30: 0x33e + CSR_MHPMEVENT31: 0x33f + CSR_MVENDORID: 0xf11 + CSR_MARCHID: 0xf12 + CSR_MIMPID: 0xf13 + CSR_MHARTID: 0xf14 + CSR_CYCLEH: 0xc80 + CSR_TIMEH: 0xc81 + CSR_INSTRETH: 0xc82 + CSR_HPMCOUNTER3H: 0xc83 + CSR_HPMCOUNTER4H: 0xc84 + CSR_HPMCOUNTER5H: 0xc85 + CSR_HPMCOUNTER6H: 0xc86 + CSR_HPMCOUNTER7H: 0xc87 + CSR_HPMCOUNTER8H: 0xc88 + CSR_HPMCOUNTER9H: 0xc89 + CSR_HPMCOUNTER10H: 0xc8a + CSR_HPMCOUNTER11H: 0xc8b + CSR_HPMCOUNTER12H: 0xc8c + CSR_HPMCOUNTER13H: 0xc8d + CSR_HPMCOUNTER14H: 0xc8e + CSR_HPMCOUNTER15H: 0xc8f + CSR_HPMCOUNTER16H: 0xc90 + CSR_HPMCOUNTER17H: 0xc91 + CSR_HPMCOUNTER18H: 0xc92 + CSR_HPMCOUNTER19H: 0xc93 + CSR_HPMCOUNTER20H: 0xc94 + CSR_HPMCOUNTER21H: 0xc95 + CSR_HPMCOUNTER22H: 0xc96 + CSR_HPMCOUNTER23H: 0xc97 + CSR_HPMCOUNTER24H: 0xc98 + CSR_HPMCOUNTER25H: 0xc99 + CSR_HPMCOUNTER26H: 0xc9a + CSR_HPMCOUNTER27H: 0xc9b + CSR_HPMCOUNTER28H: 0xc9c + CSR_HPMCOUNTER29H: 0xc9d + CSR_HPMCOUNTER30H: 0xc9e + CSR_HPMCOUNTER31H: 0xc9f + CSR_MCYCLEH: 0xb80 + CSR_MINSTRETH: 0xb82 + CSR_MHPMCOUNTER3H: 0xb83 + CSR_MHPMCOUNTER4H: 0xb84 + CSR_MHPMCOUNTER5H: 0xb85 + CSR_MHPMCOUNTER6H: 0xb86 + CSR_MHPMCOUNTER7H: 0xb87 + CSR_MHPMCOUNTER8H: 0xb88 + CSR_MHPMCOUNTER9H: 0xb89 + CSR_MHPMCOUNTER10H: 0xb8a + CSR_MHPMCOUNTER11H: 0xb8b + CSR_MHPMCOUNTER12H: 0xb8c + CSR_MHPMCOUNTER13H: 0xb8d + CSR_MHPMCOUNTER14H: 0xb8e + CSR_MHPMCOUNTER15H: 0xb8f + CSR_MHPMCOUNTER16H: 0xb90 + CSR_MHPMCOUNTER17H: 0xb91 + CSR_MHPMCOUNTER18H: 0xb92 + CSR_MHPMCOUNTER19H: 0xb93 + CSR_MHPMCOUNTER20H: 0xb94 + CSR_MHPMCOUNTER21H: 0xb95 + CSR_MHPMCOUNTER22H: 0xb96 + CSR_MHPMCOUNTER23H: 0xb97 + CSR_MHPMCOUNTER24H: 0xb98 + CSR_MHPMCOUNTER25H: 0xb99 + CSR_MHPMCOUNTER26H: 0xb9a + CSR_MHPMCOUNTER27H: 0xb9b + CSR_MHPMCOUNTER28H: 0xb9c + CSR_MHPMCOUNTER29H: 0xb9d + CSR_MHPMCOUNTER30H: 0xb9e + CSR_MHPMCOUNTER31H: 0xb9f + CAUSE_MISALIGNED_FETCH: 0x0 + CAUSE_FETCH_ACCESS: 0x1 + CAUSE_ILLEGAL_INSTRUCTION: 0x2 + CAUSE_BREAKPOINT: 0x3 + CAUSE_MISALIGNED_LOAD: 0x4 + CAUSE_LOAD_ACCESS: 0x5 + CAUSE_MISALIGNED_STORE: 0x6 + CAUSE_STORE_ACCESS: 0x7 + CAUSE_USER_ECALL: 0x8 + CAUSE_SUPERVISOR_ECALL: 0x9 + CAUSE_HYPERVISOR_ECALL: 0xa + CAUSE_MACHINE_ECALL: 0xb + CAUSE_FETCH_PAGE_FAULT: 0xc + CAUSE_LOAD_PAGE_FAULT: 0xd + CAUSE_STORE_PAGE_FAULT: 0xf + CSR_MENTROPY: 0xF15 + CSR_MNOISE: 0x7A9 + DCSR_XDEBUGVER: (3U<<30) + DCSR_NDRESET: (1<<29) + DCSR_FULLRESET: (1<<28) + DCSR_EBREAKM: (1<<15) + DCSR_EBREAKH: (1<<14) + DCSR_EBREAKS: (1<<13) + DCSR_EBREAKU: (1<<12) + DCSR_STOPCYCLE: (1<<10) + DCSR_STOPTIME: (1<<9) + DCSR_CAUSE: (7<<6) + DCSR_DEBUGINT: (1<<5) + DCSR_HALT: (1<<3) + DCSR_STEP: (1<<2) + DCSR_PRV: (3<<0) + MCONTROL_SELECT: (1<<19) + MCONTROL_TIMING: (1<<18) + MCONTROL_ACTION: (0x3f<<12) + MCONTROL_CHAIN: (1<<11) + MCONTROL_MATCH: (0xf<<7) + MCONTROL_M: (1<<6) + MCONTROL_H: (1<<5) + MCONTROL_S: (1<<4) + MCONTROL_U: (1<<3) + MCONTROL_EXECUTE: (1<<2) + MCONTROL_STORE: (1<<1) + MCONTROL_LOAD: (1<<0) + MIP_SSIP: (1 << IRQ_S_SOFT) + MIP_HSIP: (1 << IRQ_H_SOFT) + MIP_MSIP: (1 << IRQ_M_SOFT) + MIP_STIP: (1 << IRQ_S_TIMER) + MIP_HTIP: (1 << IRQ_H_TIMER) + MIP_MTIP: (1 << IRQ_M_TIMER) + MIP_SEIP: (1 << IRQ_S_EXT) + MIP_HEIP: (1 << IRQ_H_EXT) + MIP_MEIP: (1 << IRQ_M_EXT) + RISCV_PGSIZE: (1 << RISCV_PGSHIFT) + +PMP_MACROS: + PMPCFG_BIT_SET: 1 + PMPCFG_BIT_NOT_SET: 0 + PMPCFG_ONLY_R_SET: 0x01 + PMPCFG_ONLY_X_SET: 0x04 + PMPCFG_ONLY_RW_SET: 0x03 + PMPCFG_ONLY_RX_SET: 0x05 + PMPCFG_ONLY_RWX_SET: 0x07 + PMPCFG_OFF_MODE: 0x00 + PMPCFG_TOR_MODE: 0x08 + PMPCFG_NA4_MODE: 0x10 + PMPCFG_NAPOT_MODE: 0x18 + PMPCFG_R_BIT: 0x01 + PMPCFG_W_BIT: 0x02 + PMPCFG_X_BIT: 0x04 + PMPCFG_RWX_BIT: 0x07 + PMPCFG_A_BIT: 0x18 + PMPCFG_RW_BIT: 0x60 + PMPCFG_L_BIT: 0x80 + PMPCFG_ALL_BIT: 0xFF + +PMP_helper_Coverpoints: + NAPOT_REGION_ADDRESS_MATCH: ((rs1_val + imm_val) ^ (pmpaddr1<<2)) & ~(((pmpaddr1 ^ (pmpaddr1+1))<<2) | 3) ==0 and ((rs1_val+imm_val+access_len-1 ) ^ (pmpaddr1<<2)) & ~(((pmpaddr1 ^ (pmpaddr1+1))<<2) | 3) ==0 + NAPOT_PRIORITY_REGION_MATCH: ((rs1_val + imm_val) ^ (pmpaddr3<<2)) & ~(((pmpaddr3 ^ (pmpaddr3+1))<<2) | 3) ==0 and ((rs1_val+imm_val+access_len-1 ) ^ (pmpaddr3<<2)) & ~(((pmpaddr3 ^ (pmpaddr3+1))<<2) | 3) ==0 + NAPOT_PRIORITY_2_REGION_MATCH: ((rs1_val + imm_val) ^ (pmpaddr1<<2)) & ~(((pmpaddr1 ^ (pmpaddr1+1))<<2) | 3) ==0 and ((rs1_val+imm_val+access_len-1 ) ^ (pmpaddr1<<2)) & ~(((pmpaddr1 ^ (pmpaddr1+1))<<2) | 3) ==0 + TOR_REGION_ADDRESS_MATCH: (rs1_val + imm_val >= (pmpaddr1 << 2)) and (rs1_val + imm_val < (pmpaddr2 << 2)) + TOR_PRIORITY_REGION_MATCH: (rs1_val + imm_val >= (pmpaddr2 << 2)) and (rs1_val + imm_val < (pmpaddr3 << 2)) + TOR_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2)) + NA4_REGION_ADDRESS_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2)) + NA4_PRIORITY_REGION_MATCH: (rs1_val + imm_val == (pmpaddr3 << 2)) + NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2)) + +SV32_MACROS: + LEVEL_1_JUMP_SIZE: (0x400000 - 4) + LEVEL_0_JUMP_SIZE: (0x1000-4) + read: "RWX" + writ: "rx" + va_data_sv32: (0x91400000) + +PMM_MACROS: + PMM_MASK: 0x300000000 + PMM_MASK_SV57: 0x200000000 + PMM_MASK_SV48: 0x300000000 + PMM_MASK_DISABLED: 0x000000000 diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 0b5cca2ec..051254b65 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -189,14 +189,37 @@ Mend_PMP: ;\ or _PAR, _PAR, _PR ;\ SREG _PAR, 0(_TR1); -#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ - .if (level==1) ;\ - LA(_TR1, rvtest_Sroot_pg_tbl) ;\ - .endif ;\ - .if (level==0) ;\ - LA(_TR1, rvtest_slvl1_pg_tbl) ;\ - .endif ;\ - PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) +#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\ + srli _PAR, _PAR, 12 ;\ + slli _PAR, _PAR, 10 ;\ + or _PAR, _PAR, _PR ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + LI(_TR0, ((VA>>22)&0x3FF)<<2) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + LI(_TR0, ((VA>>12)&0x3FF)<<2) ;\ + .endif ;\ + add _TR1, _TR1, _TR0 ;\ + SREG _PAR, 0(_TR1); + +// More Robust version of PTE_SETUP_32 to setup a PTE for a PA using Va +// in a single line. +//args: PA: Label of Physical Address, PERMS: permissions in hex +//args: VA: Virtual Address in hex, level: Level to store at +#define PTE_SETUP_RV32_New(PA_LBL, PERMS, VA, level) ;\ + LA(a0, PA_LBL) ;\ + LI(a1, PERMS) ;\ + PTE_SETUP_RV32(a0, a1, t0, t1, VA, level) ;\ + +#define SAVE_AREA_SETUP(VA, PA_LBL, _REG_NAME) ;\ + LI (t0, VA) ;\ + LA (t1, PA_LBL) ;\ + sub t0, t0, t1 ;\ + LREG t1, _REG_NAME##_bgn_off+0*sv_area_sz(sp) ;\ + add t2, t1, t0 ;\ + SREG t2, _REG_NAME##_bgn_off+1*sv_area_sz(sp) ;\ #define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ .if (level==2) ;\ From b1f23c3ce6345c46feb7e44fa40834135aa250a0 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 18 Oct 2024 10:54:55 +0500 Subject: [PATCH 03/19] RVMODEL_HALT label added --- riscv-test-suite/env/test_macros.h | 2 ++ .../vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S | 2 +- .../vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S | 2 +- .../vm_sv32_software_update/pmp_check_on_pa_S_mode.S | 2 +- .../vm_sv32_software_update/pmp_check_on_pa_U_mode.S | 2 +- .../vm_sv32_software_update/pmp_check_on_pte_S_mode.S | 2 +- .../vm_sv32_software_update/pmp_check_on_pte_U_mode.S | 2 +- .../vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S | 4 +++- .../vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_misaligned_S_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_misaligned_U_mode.S | 2 +- .../rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S | 2 +- .../rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S | 2 +- .../vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S | 2 +- .../vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S | 2 +- .../vm_sv32_software_update/vm_reserved_pte_S_mode.S | 2 +- .../vm_sv32_software_update/vm_reserved_pte_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_sum_set_S_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S | 2 +- 24 files changed, 27 insertions(+), 23 deletions(-) diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 051254b65..52ca0de89 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -21,6 +21,8 @@ #define LEVEL3 0x03 #define LEVEL4 0x04 +#define ALL_F_S 0xFFFFFFFF + #define sv39 0x00 #define sv48 0x01 #define sv57 0x02 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S index f02cc4aea..3bd631b6d 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S @@ -293,7 +293,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S index 890e69ade..ec3566491 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S @@ -293,7 +293,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S index 3d1ca4b27..085d33da4 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S @@ -238,7 +238,7 @@ Then, Region 3 till 0xFFFFFFFF with RWX and as a TOR Region above rvtest_data_1_ #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S index c58649896..7515aee9e 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S @@ -238,7 +238,7 @@ Then, Region 3 till 0xFFFFFFFF with RWX and as a TOR Region above rvtest_data_1_ #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S index f6cb0c663..08837d15a 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S @@ -237,7 +237,7 @@ After this region till 0xFFFFFFFF, RWX permissions via TOR #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S index f5edae29c..74ff1f2d5 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S @@ -237,7 +237,7 @@ After this region till 0xFFFFFFFF, RWX permissions via TOR #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S index 8244af564..35ef7da9d 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S @@ -51,6 +51,8 @@ // Total Expected Faults: 14 // ---------------------------------------------------------------------------------------------------------------------- +//TODO: instead of using two different tests, use a single test for hart/software update. + #include "model_test.h" #include "arch_test.h" @@ -307,7 +309,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S index 6b4a1fe0e..9aaccc4cc 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S @@ -307,7 +307,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S index fbf6ae1dd..42c676b5f 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S @@ -308,7 +308,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S index 4a79714c6..ea8099335 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S @@ -328,7 +328,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S index ec43f6fe9..d5620b251 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S @@ -338,7 +338,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S index 9a89f4052..29457beba 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S @@ -214,7 +214,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S index 95207e64d..600165c8a 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S @@ -215,7 +215,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S index 788fa4c9f..44a660af2 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S @@ -190,7 +190,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 12 //misaligned page diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S index a65b84f84..792bb955f 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S @@ -189,7 +189,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 12 //misaligned page diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S index 58c8aae13..aa161ac71 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S @@ -233,7 +233,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S index 1b06d9910..329ce5314 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S @@ -233,7 +233,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S index 44a08ed20..0f17ead98 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S @@ -192,7 +192,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S index 5de93fb8b..b017e6bd3 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S @@ -192,7 +192,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S index e7acfd2af..10f1a2bae 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S @@ -242,7 +242,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S index 25827854c..f73ce47a5 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S @@ -242,7 +242,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S index 7d32d10d2..227805e57 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S @@ -358,7 +358,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S index 4648eeab0..d693522fb 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S @@ -338,7 +338,7 @@ main: #endif //--------------------------------------------------------------------------------------------------------------------------------- RVTEST_CODE_END - +RVMODEL_HALT RVTEST_DATA_BEGIN .align 22 From cd30e600144b9feaffc43a80f2b06a038585545a Mon Sep 17 00:00:00 2001 From: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> Date: Thu, 24 Oct 2024 13:42:01 +0500 Subject: [PATCH 04/19] Update test.yml Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> --- .github/workflows/test.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index d5e9fb7e4..6e17772bc 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -135,7 +135,7 @@ jobs: - name: Config and run riscof for RV${{ matrix.xlen }} run: | cd riscof-plugins/rv${{ matrix.xlen }} - riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/ --env ../../riscv-test-suite/env + riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/privilege --env ../../riscv-test-suite/env #Check the existance of the riscof work folder, and add the PATH to environment variable - name: Check size and determine upload path @@ -173,4 +173,4 @@ jobs: name: riscof-artifact-rv${{ matrix.xlen }} path: ${{ env.upload_path }} compression-level: 6 - overwrite: true \ No newline at end of file + overwrite: true From 7fcd0373c8ca36befd4a958a87809cb6cc6949a6 Mon Sep 17 00:00:00 2001 From: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> Date: Thu, 24 Oct 2024 13:50:58 +0500 Subject: [PATCH 05/19] Update test.yml Signed-off-by: Muhammad Hammad Bashir <139617104+MuhammadHammad001@users.noreply.github.com> --- .github/workflows/test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 6e17772bc..3f38e9695 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -147,7 +147,7 @@ jobs: if [ -d "$work_folder" ]; then folder_size=$(du -sm "$work_folder" | cut -f1) echo "Folder size: ${folder_size} MB" - if [ "$folder_size" -gt 1000 ]; then + if [ "$folder_size" -gt 100000 ]; then echo "Size exceeds 1 GB. Checking if report exists." if [ -f "$report_file" ]; then echo "Uploading RISCOF generated report only." From b27a8e07d461b8e41e75051a52142ff487547da5 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Thu, 24 Oct 2024 14:57:19 +0500 Subject: [PATCH 06/19] alignment added for 4KB page boundry --- .../privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S | 2 +- .../privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S | 2 +- .../privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S | 2 +- .../vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S | 2 +- .../vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S | 2 +- .../privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_misaligned_S_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_misaligned_U_mode.S | 1 + .../rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S | 1 + .../rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S | 1 + .../vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S | 1 + .../vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_sum_set_S_mode.S | 1 + .../privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S | 1 + 21 files changed, 21 insertions(+), 6 deletions(-) diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S index 085d33da4..c1a58e94c 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S @@ -306,7 +306,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S index 7515aee9e..bdde6274a 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S @@ -306,7 +306,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S index 08837d15a..5841cde76 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S @@ -280,7 +280,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S index 74ff1f2d5..acd951aa7 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S @@ -280,7 +280,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S index 35ef7da9d..4f6db6458 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S @@ -352,7 +352,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S index 9aaccc4cc..a7148478c 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S @@ -344,7 +344,7 @@ rvtest_data_1_l0: //--------------------------------------------------------------------------------------------------------------------------------- #ifdef rvtest_strap_routine -.align 12 //complete the 4KB permission memory range +.align 12 rvtest_slvl1_pg_tbl: RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) #endif diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S index 42c676b5f..1316f8864 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S @@ -351,6 +351,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S index ea8099335..3dd17d376 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S @@ -371,6 +371,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S index d5620b251..e67ce9ad6 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S @@ -381,6 +381,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S index 29457beba..065d5b221 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S @@ -257,6 +257,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S index 600165c8a..ba8442050 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S @@ -258,6 +258,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S index 44a660af2..2012aa237 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S @@ -233,6 +233,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S index 792bb955f..5fe80ad22 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S @@ -232,6 +232,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S index aa161ac71..780ce0461 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S @@ -276,6 +276,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S index 329ce5314..6f0341098 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S @@ -276,6 +276,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S index 0f17ead98..956b47ff8 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S @@ -235,6 +235,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S index b017e6bd3..5a879f1d7 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S @@ -235,6 +235,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S index 10f1a2bae..a0142752d 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S @@ -285,6 +285,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S index f73ce47a5..49ab686af 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S @@ -285,6 +285,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S index 227805e57..7ba5a32f0 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S @@ -401,6 +401,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S index d693522fb..9227af039 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S @@ -381,6 +381,7 @@ rvtest_slvl1_pg_tbl: #endif RVTEST_DATA_END +.align 12 RVMODEL_DATA_BEGIN rvtest_sig_begin: sig_begin_canary: From bc0d2b93c51c34256c48f866994d4e56f1fc319b Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 25 Oct 2024 14:09:39 +0500 Subject: [PATCH 07/19] model_test.h updated --- .github/workflows/test.yml | 2 +- .../rv32/sail_cSim/env/model_test.h | 30 +++++++++---------- .../rv32/spike_simple/env/model_test.h | 30 +++++++++---------- 3 files changed, 30 insertions(+), 32 deletions(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 3f38e9695..a110878be 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -135,7 +135,7 @@ jobs: - name: Config and run riscof for RV${{ matrix.xlen }} run: | cd riscof-plugins/rv${{ matrix.xlen }} - riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/privilege --env ../../riscv-test-suite/env + riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m --env ../../riscv-test-suite/env #Check the existance of the riscof work folder, and add the PATH to environment variable - name: Check size and determine upload path diff --git a/riscof-plugins/rv32/sail_cSim/env/model_test.h b/riscof-plugins/rv32/sail_cSim/env/model_test.h index 94f54405d..0cccc1692 100644 --- a/riscof-plugins/rv32/sail_cSim/env/model_test.h +++ b/riscof-plugins/rv32/sail_cSim/env/model_test.h @@ -12,25 +12,23 @@ .word 4; //RV_COMPLIANCE_HALT -#define RVMODEL_HALT ;\ -li x1, 1 ;\ -1: ;\ - sw x1, tohost, t2 ;\ - j 1b ;\ +#define RVMODEL_HALT \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t5; \ + j write_tohost; #define RVMODEL_BOOT -//RV_COMPLIANCE_DATA_BEGIN -#define RVMODEL_DATA_BEGIN ;\ -RVMODEL_DATA_SECTION ;\ -.align 4 ;\ -.global begin_signature ;\ -begin_signature: - -//RV_COMPLIANCE_DATA_END -#define RVMODEL_DATA_END \ -.global end_signature; end_signature: +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN \ + RVMODEL_DATA_SECTION \ + .align 4;\ + .global begin_signature; begin_signature: +//RV_COMPLIANCE_DATA_END +#define RVMODEL_DATA_END \ + .align 4; .global end_signature; end_signature: //RVTEST_IO_INIT #define RVMODEL_IO_INIT @@ -54,4 +52,4 @@ RVMODEL_DATA_SECTION ;\ #define RVMODEL_CLEAR_MEXT_INT -#endif // _COMPLIANCE_MODEL_H +#endif // _COMPLIANCE_MODEL_H \ No newline at end of file diff --git a/riscof-plugins/rv32/spike_simple/env/model_test.h b/riscof-plugins/rv32/spike_simple/env/model_test.h index 53c6e8cab..d7cc7b29d 100644 --- a/riscof-plugins/rv32/spike_simple/env/model_test.h +++ b/riscof-plugins/rv32/spike_simple/env/model_test.h @@ -1,11 +1,5 @@ #ifndef _COMPLIANCE_MODEL_H #define _COMPLIANCE_MODEL_H -#if XLEN == 64 - #define ALIGNMENT 3 -#else - #define ALIGNMENT 2 -#endif - #define RVMODEL_DATA_SECTION \ .pushsection .tohost,"aw",@progbits; \ .align 8; .global tohost; tohost: .dword 0; \ @@ -17,22 +11,23 @@ .word 4; //RV_COMPLIANCE_HALT -#define RVMODEL_HALT ;\ -li x1, 1 ;\ -1: ;\ - sw x1, tohost, t2 ;\ - j 1b ;\ +#define RVMODEL_HALT \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t5; \ + j write_tohost; #define RVMODEL_BOOT //RV_COMPLIANCE_DATA_BEGIN #define RVMODEL_DATA_BEGIN \ RVMODEL_DATA_SECTION \ - .align ALIGNMENT;\ + .align 4;\ .global begin_signature; begin_signature: //RV_COMPLIANCE_DATA_END #define RVMODEL_DATA_END \ + .align 4;\ .global end_signature; end_signature: //RVTEST_IO_INIT @@ -48,13 +43,18 @@ li x1, 1 ;\ //RVTEST_IO_ASSERT_DFPR_EQ #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) -#define RVMODEL_SET_MSW_INT +#define RVMODEL_SET_MSW_INT \ + li t1, 1; \ + li t2, 0x2000000; \ + sw t1, 0(t2); -#define RVMODEL_CLEAR_MSW_INT +#define RVMODEL_CLEAR_MSW_INT \ + li t2, 0x2000000; \ + sw x0, 0(t2); #define RVMODEL_CLEAR_MTIMER_INT #define RVMODEL_CLEAR_MEXT_INT -#endif // _COMPLIANCE_MODEL_H +#endif // _COMPLIANCE_MODEL_H \ No newline at end of file From d98ed3339f0360ba9d91e99fb40b40795ce15731 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 25 Oct 2024 21:01:03 +0500 Subject: [PATCH 08/19] removed hardware update tests and added its covergroups in a single file --- coverage/rv32_vm_sv32_hart_upd.cgf | 97 ----- .../rv32_vm_sv32.cgf} | 98 +++++ .../pmp_check_on_pa_S_mode.S | 0 .../pmp_check_on_pa_U_mode.S | 0 .../pmp_check_on_pte_S_mode.S | 0 .../pmp_check_on_pte_U_mode.S | 0 .../vm_A_and_D_S_mode.S} | 0 .../vm_A_and_D_U_mode.S} | 0 .../vm_U_Bit_set_U_mode.S | 0 .../vm_U_Bit_unset_S_mode.S | 0 .../vm_U_Bit_unset_U_mode.S | 0 .../vm_invalid_pte_S_mode.S | 0 .../vm_invalid_pte_U_mode.S | 0 .../vm_misaligned_S_mode.S | 0 .../vm_misaligned_U_mode.S | 0 .../vm_mxr_S_mode.S | 0 .../vm_mxr_U_mode.S | 0 .../vm_nleaf_pte_level0_S_mode.S | 0 .../vm_nleaf_pte_level0_U_mode.S | 0 .../vm_reserved_pte_S_mode.S | 0 .../vm_reserved_pte_U_mode.S | 0 .../vm_sum_set_S_mode.S | 0 .../vm_sum_unset_S_mode.S | 0 .../vm_A_and_D_hart_upd_S_mode.S | 358 ------------------ .../vm_A_and_D_hart_upd_U_mode.S | 358 ------------------ 25 files changed, 98 insertions(+), 813 deletions(-) delete mode 100644 coverage/rv32_vm_sv32_hart_upd.cgf rename coverage/{rv32_vm_sv32_soft_upd.cgf => sv32/rv32_vm_sv32.cgf} (88%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/pmp_check_on_pa_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/pmp_check_on_pa_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/pmp_check_on_pte_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/pmp_check_on_pte_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S => vm_sv32/vm_A_and_D_S_mode.S} (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S => vm_sv32/vm_A_and_D_U_mode.S} (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_U_Bit_set_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_U_Bit_unset_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_U_Bit_unset_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_invalid_pte_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_invalid_pte_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_misaligned_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_misaligned_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_mxr_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_mxr_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_nleaf_pte_level0_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_nleaf_pte_level0_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_reserved_pte_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_reserved_pte_U_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_sum_set_S_mode.S (100%) rename riscv-test-suite/rv32i_m/privilege/{vm_sv32_software_update => vm_sv32}/vm_sum_unset_S_mode.S (100%) delete mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S delete mode 100644 riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S diff --git a/coverage/rv32_vm_sv32_hart_upd.cgf b/coverage/rv32_vm_sv32_hart_upd.cgf deleted file mode 100644 index 5765f93a7..000000000 --- a/coverage/rv32_vm_sv32_hart_upd.cgf +++ /dev/null @@ -1,97 +0,0 @@ -a_and_d_bit_hart_upd_S_mode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - op_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - csr_comb: - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - #CASES at LEVEL 1 - # Test Case:1 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 1 - 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 -> D bit set and A bit set and RWX set -> NO FAULT -- LEVEL 1 - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case:3 -> D bit set but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 - 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:4 -> No D bit unset but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 - #CASES at LEVEL 0 - # Test Case:5 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 - # Test Case:6 -> D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 - # Test Case:7 -> D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 - # Test Case:8 -> No D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 - #Faults check at LEVEL 1 and LEVEL 0 - #Test Case:1 --> successfull page table walk - 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:2 --> successfull page table walk - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:3 --> successfull page table walk - 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:4 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:5 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 - #Test Case:6 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1 and len_dptw == 2': 0 - #Test Case:7 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 - #Test Case:8 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 - -a_and_d_bit_hart_upd_U_mode: - config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # LEVEL 1 Test Cases: - # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 2: Both A and D bits set, RWX set --> No fault. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 - # LEVEL 0 Test Cases: - # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 - # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 - # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 - # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 - # Fault Checks: - # Test Case 1: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 2: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 3: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 4: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 5: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 - # Test Case 6: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1 and len_dptw == 2': 0 - # Test Case 7: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 - # Test Case 8: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 diff --git a/coverage/rv32_vm_sv32_soft_upd.cgf b/coverage/sv32/rv32_vm_sv32.cgf similarity index 88% rename from coverage/rv32_vm_sv32_soft_upd.cgf rename to coverage/sv32/rv32_vm_sv32.cgf index 0864ed1c5..5224244a9 100644 --- a/coverage/rv32_vm_sv32_soft_upd.cgf +++ b/coverage/sv32/rv32_vm_sv32.cgf @@ -761,3 +761,101 @@ U_bit_unset_in_SMode: 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0 and mcause == 15': 0 #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +a_and_d_bit_hart_upd_S_mode: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + #Check that the satp is active --> in S mode & also check that SV32 is configured + 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + #CASES at LEVEL 1 + # Test Case:1 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 1 + 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:2 -> D bit set and A bit set and RWX set -> NO FAULT -- LEVEL 1 + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case:3 -> D bit set but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 + 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case:4 -> No D bit unset but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 + #CASES at LEVEL 0 + # Test Case:5 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 + # Test Case:6 -> D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 + # Test Case:7 -> D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 + # Test Case:8 -> No D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 + #Faults check at LEVEL 1 and LEVEL 0 + #Test Case:1 --> successfull page table walk + 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:2 --> successfull page table walk + 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:3 --> successfull page table walk + 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:4 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + #Test Case:5 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 + #Test Case:6 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1 and len_dptw == 2': 0 + #Test Case:7 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 + #Test Case:8 --> successfull page table walk + 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 + +a_and_d_bit_hart_upd_U_mode: + config: + # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. + 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + # LEVEL 1 Test Cases: + # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 2: Both A and D bits set, RWX set --> No fault. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 + # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 + # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 + # LEVEL 0 Test Cases: + # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 + # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 + # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 + # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 + # Fault Checks: + # Test Case 1: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 2: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 3: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 4: Successful page table walk at Level 1. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 + # Test Case 5: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 + # Test Case 6: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1 and len_dptw == 2': 0 + # Test Case 7: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 + # Test Case 8: Successful page table walk at Level 0. + 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pa_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/pmp_check_on_pte_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_A_and_D_soft_upd_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_set_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_set_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_set_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_U_Bit_unset_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_invalid_pte_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_misaligned_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_mxr_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_nleaf_pte_level0_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_reserved_pte_U_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_set_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_set_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_set_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_unset_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32_software_update/vm_sum_unset_S_mode.S rename to riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_unset_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S deleted file mode 100644 index 3bd631b6d..000000000 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_S_mode.S +++ /dev/null @@ -1,358 +0,0 @@ -// ---------------------------------------------------------------------------------------------------------------------- -// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: -// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 -// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid -// ---------------------------------------------------------------------------------------------------------------------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ---------------------------------------------------------------------------------------------------------------------- -// Test Explanation: -// RISC-V Privileged Architecture ISA Manual -- Section 10.3 -// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. -// -// Access and Dirty Bit Test in S-Mode with Hardware Update -// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. -// Future updates will align with ISA version 1.13. -// -// Test cases are as follows: -// ---------------------------------------------------------------------------------------------------------------------- -// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: HART updates the PTE by setting the D-bit. No fault should occur. -// -// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: No fault should occur. -// -// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: HART updates the PTE by setting the A-bit. No fault should occur. -// -// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. -// -// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: HART updates the PTE by setting the D-bit. No fault should occur. -// -// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: No fault should occur. -// -// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: HART updates the PTE by setting the A-bit. No fault should occur. -// -// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in S-Mode. -// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. -// -// Total Expected Faults: 0 -// ---------------------------------------------------------------------------------------------------------------------- - -#include "model_test.h" - -#include "arch_test.h" - -RVTEST_ISA("RV32I_Zicsr") - -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_hart_upd_S_mode) - -RVTEST_SIGBASE( x13,signature_x13_1) -// ------------------------------------------------------------------------------------------------------------ -// Macro to test RWX (read, write, execute) permissions. -// ------------------------------------------------------------------------------------------------------------ -.macro VERIFICATION_RWX ADDRESS, level - LA(a5, \ADDRESS) // Fetch the address to be checked - addi a2, a2, 16 // 16 stored in a2 for starting point - - // Check store on the address. - sw a2, 20(a5) - SREG a2, 0(s11) - nop - addi s11, s11, REGWIDTH - - lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - SREG a4, 0(s11) - nop - addi s11, s11, REGWIDTH - - //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions - //else jump to the end of the 4MB page to check the permissions - // Check if level is equal to zero (4KB page) - addi a2, a2, 16 // update the counter for execute - LI( t1, \level) - beqz t1, 1f // Forward reference to avoid label redefinition - - // 4MB - 4 = 4,194,300 bytes - // Access the last four bytes which contain the jr instruction - LI (t0, (0x400000 - 4)) - srli a5, a5, 22 - slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) - add t0, a5, t0 - jalr ra, t0, 0 - SREG a2, 0(s11) - nop - addi s11, s11, REGWIDTH - j 2f - -1: // 4KB - 4 = 4,092 bytes - LI (t0, (0x1000-4)) - srli a5, a5, 12 - slli a5, a5, 12 - add t0, a5, t0 - jalr ra, t0, 0 - SREG a2, 0(s11) - nop - addi s11, s11, REGWIDTH - -2: // end_macro - // execution test sig update - nop -.endm - -// ------------------------------------------------------------------------------------------------------------ -// Macro to run the test -// ------------------------------------------------------------------------------------------------------------ -.macro TEST_CASES_RUNNER LOWER_MODE, VA, level - RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode - .align 2 - - //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) - VERIFICATION_RWX \VA, \level - nop - nop - - RVTEST_GOTO_MMODE // Switching back to M mode - -.endm - -main: -#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine - LI a4, 0xceed - RVTEST_SIGUPD(x13,a4) -#endif -#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine - LI a4, 0xbeed - RVTEST_SIGUPD(x13,a4) -#endif - - ALL_MEM_PMP // set the PMP permissions for the whole memory - csrw satp, zero // write satp with all zeros (bare mode) - -//--------------------------------------------------------------------------------------------------------------------------------- -// Virtual addresses definition section for the code, data, sig, vmem, test sections -//--------------------------------------------------------------------------------------------------------------------------------- - - // test section VAs - .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 - .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 - .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 - - // code, data, sig, vmem section VAs - .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin - .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) - .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 - .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin - -// PTE setup for Code Region - PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) - sfence.vma -// PTE setup for Data Region - PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) - sfence.vma -// PTE setup for Signature Region - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) - PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) - sfence.vma -// register setup for the signature save in virtualization mode - LI (t0, va_rvtest_sig_begin) - LA (t1, rvtest_sig_begin) - sub t0, t0, t1 // (VA-PA) Note: VA > PA - add s11, x13, t0 // Translation of Signature reg - -//--------------------------------------------------------------------------------------------------------------------------------- -// Save area logic -//--------------------------------------------------------------------------------------------------------------------------------- - LI (t0, va_rvtest_data_begin) - LA (t1, rvtest_data_begin) - sub t0, t0, t1 - addi t3, t0, sv_area_sz - csrr sp, mscratch - add t1,sp,t3 - csrw sscratch, t1 - csrr sp, mscratch - - //save area setup for code region - SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) - //save area setup for data region - SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) - //save area setup for sig region - SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) - //save area setup for vmem region - SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) - -//--------------------------------------------------------------------------------------------------------------------------------- -// Test Cases Start from here -//--------------------------------------------------------------------------------------------------------------------------------- - - - SATP_SETUP_SV32 // set the SATP for virtualization - sfence.vma // flush the TLB -//--------------------------------------------------------------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------------------------------------------- -// TESTS AT LEVEL 1 -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 1: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A| PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 2: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 3: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 4: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------------------------------------------- -// TESTS AT LEVEL 0 -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 5: D bit is unset and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL0 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 6: D bit is set and A bit set | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL0 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 7: D bit is set and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL0 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 8: D bit is unset and A bit unset | Test in S-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Smode, va_data, LEVEL0 - -#endif -//--------------------------------------------------------------------------------------------------------------------------------- -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 22 - -//--------------------------------------------------------------------------------------------------------------------------------- -// PHYSICAL ADDRESS REGIONS FOR TESTING -//--------------------------------------------------------------------------------------------------------------------------------- -//Physical Address region under testing for LEVEL 1 -- Aligned by 22 -rvtest_data_1_l1: - nop //nops are added so if there is a trap - addi ra, ra, REGWIDTH - jr ra // return back if the access fault - nop - .word 0xbeefcaf1 // Random word - .word 0xbeefcaf2 // Random word - .rept ((1 << 20) - 7) // (2^22 - 7) nops - nop - .endr - jr ra // return back if successful access - -//Physical Address region under testing for LEVEL 0 -- Aligned by 10 -rvtest_data_1_l0: - nop // trap return back skip - addi ra, ra, REGWIDTH - jr ra //jump back for the trap on level 1 - nop - .word 0xbeefcaf1 // Random word - .word 0xbeefcaf2 // Random word - .rept ((1 << 10) - 7) // (2^12 - 7) nops - nop - .endr - jr ra - -//--------------------------------------------------------------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------------------------------------------- - -#ifdef rvtest_strap_routine -.align 12 //complete the 4KB permission memory range -rvtest_slvl1_pg_tbl: - RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) -#endif - -RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - -// test signatures initialization -signature_x13_1: - .fill 256*(XLEN/32),4,0xcafebeef - -// trap signatures initialization -#ifdef rvtest_mtrap_routine -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S deleted file mode 100644 index ec3566491..000000000 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32_hardware_update/vm_A_and_D_hart_upd_U_mode.S +++ /dev/null @@ -1,358 +0,0 @@ -// ---------------------------------------------------------------------------------------------------------------------- -// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: -// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 -// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid -// ---------------------------------------------------------------------------------------------------------------------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ---------------------------------------------------------------------------------------------------------------------- -// Test Explanation: -// RISC-V Privileged Architecture ISA Manual -- Section 10.3 -// This test verifies the functioning of the A (Accessed) and D (Dirty) bits in the SV-32 virtual memory system. -// -// Access and Dirty Bit Test in U-Mode with Hardware Update -// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. -// Future updates will align with ISA version 1.13. -// -// Test cases are as follows: -// ---------------------------------------------------------------------------------------------------------------------- -// 1. D-bit unset, A-bit set at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: HART updates the PTE by setting the D-bit. No fault should occur. -// -// 2. D-bit set, A-bit set at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: No fault should occur. -// -// 3. D-bit set, A-bit unset at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: HART updates the PTE by setting the A-bit. No fault should occur. -// -// 4. D-bit unset, A-bit unset at level 1, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. -// -// 5. D-bit unset, A-bit set at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: HART updates the PTE by setting the D-bit. No fault should occur. -// -// 6. D-bit set, A-bit set at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: No fault should occur. -// -// 7. D-bit set, A-bit unset at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: HART updates the PTE by setting the A-bit. No fault should occur. -// -// 8. D-bit unset, A-bit unset at level 0, RWX permissions (read, write, execute page): -// Action: Access the page in U-Mode. -// Expected: HART updates the PTE by setting both the D-bit and the A-bit. No fault should occur. -// -// Total Expected Faults: 0 -// ---------------------------------------------------------------------------------------------------------------------- - -#include "model_test.h" - -#include "arch_test.h" - -RVTEST_ISA("RV32I_Zicsr") - -# Test code region -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_hart_upd_U_mode) - -RVTEST_SIGBASE( x13,signature_x13_1) -// ------------------------------------------------------------------------------------------------------------ -// Macro to test RWX (read, write, execute) permissions. -// ------------------------------------------------------------------------------------------------------------ -.macro VERIFICATION_RWX ADDRESS, level - LA(a5, \ADDRESS) // Fetch the address to be checked - addi a2, a2, 16 // 16 stored in a2 for starting point - - // Check store on the address. - sw a2, 20(a5) - SREG a2, 0(s11) - nop - addi s11, s11, REGWIDTH - - lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) - SREG a4, 0(s11) - nop - addi s11, s11, REGWIDTH - - //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions - //else jump to the end of the 4MB page to check the permissions - // Check if level is equal to zero (4KB page) - addi a2, a2, 16 // update the counter for execute - LI( t1, \level) - beqz t1, 1f // Forward reference to avoid label redefinition - - // 4MB - 4 = 4,194,300 bytes - // Access the last four bytes which contain the jr instruction - LI (t0, (0x400000 - 4)) - srli a5, a5, 22 - slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) - add t0, a5, t0 - jalr ra, t0, 0 - SREG a2, 0(s11) - nop - addi s11, s11, REGWIDTH - j 2f - -1: // 4KB - 4 = 4,092 bytes - LI (t0, (0x1000-4)) - srli a5, a5, 12 - slli a5, a5, 12 - add t0, a5, t0 - jalr ra, t0, 0 - SREG a2, 0(s11) - nop - addi s11, s11, REGWIDTH - -2: // end_macro - // execution test sig update - nop -.endm - -// ------------------------------------------------------------------------------------------------------------ -// Macro to run the test -// ------------------------------------------------------------------------------------------------------------ -.macro TEST_CASES_RUNNER LOWER_MODE, VA, level - RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode - .align 2 - - //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) - VERIFICATION_RWX \VA, \level - nop - nop - - RVTEST_GOTO_MMODE // Switching back to M mode - -.endm - -main: -#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine - LI a4, 0xceed - RVTEST_SIGUPD(x13,a4) -#endif -#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine - LI a4, 0xbeed - RVTEST_SIGUPD(x13,a4) -#endif - - ALL_MEM_PMP // set the PMP permissions for the whole memory - csrw satp, zero // write satp with all zeros (bare mode) - -//--------------------------------------------------------------------------------------------------------------------------------- -// Virtual addresses definition section for the code, data, sig, vmem, test sections -//--------------------------------------------------------------------------------------------------------------------------------- - - // test section VAs - .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 - .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 - .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 - - // code, data, sig, vmem section VAs - .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin - .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) - .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 - .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin - -// PTE setup for Code Region - PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_U | PTE_V), va_rvtest_code_begin, LEVEL1) - sfence.vma -// PTE setup for Data Region - PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_U | PTE_V), va_rvtest_data_begin, LEVEL1) - sfence.vma -// PTE setup for Signature Region - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) - PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) - sfence.vma -// register setup for the signature save in virtualization mode - LI (t0, va_rvtest_sig_begin) - LA (t1, rvtest_sig_begin) - sub t0, t0, t1 // (VA-PA) Note: VA > PA - add s11, x13, t0 // Translation of Signature reg - -//--------------------------------------------------------------------------------------------------------------------------------- -// Save area logic -//--------------------------------------------------------------------------------------------------------------------------------- - LI (t0, va_rvtest_data_begin) - LA (t1, rvtest_data_begin) - sub t0, t0, t1 - addi t3, t0, sv_area_sz - csrr sp, mscratch - add t1,sp,t3 - csrw sscratch, t1 - csrr sp, mscratch - - //save area setup for code region - SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) - //save area setup for data region - SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) - //save area setup for sig region - SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) - //save area setup for vmem region - SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) - -//--------------------------------------------------------------------------------------------------------------------------------- -// Test Cases Start from here -//--------------------------------------------------------------------------------------------------------------------------------- - - - SATP_SETUP_SV32 // set the SATP for virtualization - sfence.vma // flush the TLB -//--------------------------------------------------------------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------------------------------------------- -// TESTS AT LEVEL 1 -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 1 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 1: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_A| PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 2 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 2: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 3 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 3: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4MB PAGE Region 4 under test at level 1 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 4: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL1 - -//--------------------------------------------------------------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------------------------------------------- -// TESTS AT LEVEL 0 -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 1 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 5: D bit is unset and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL0 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 2 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 6: D bit is set and A bit set | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL0 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 3 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 7: D bit is set and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL0 - -//--------------------------------------------------------------------------------------------------------------------------------- -// 4KB PAGE Region 4 under test at level 0 -- R,W,X permissions given to the region -//--------------------------------------------------------------------------------------------------------------------------------- - // Test case 8: D bit is unset and A bit unset | Test in U-Mode | RWX bit set | expected = NO Fault - PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) - PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) - sfence.vma - - TEST_CASES_RUNNER Umode, va_data, LEVEL0 - -#endif -//--------------------------------------------------------------------------------------------------------------------------------- -RVTEST_CODE_END -RVMODEL_HALT -RVTEST_DATA_BEGIN -.align 22 - -//--------------------------------------------------------------------------------------------------------------------------------- -// PHYSICAL ADDRESS REGIONS FOR TESTING -//--------------------------------------------------------------------------------------------------------------------------------- -//Physical Address region under testing for LEVEL 1 -- Aligned by 22 -rvtest_data_1_l1: - nop //nops are added so if there is a trap - addi ra, ra, REGWIDTH - jr ra // return back if the access fault - nop - .word 0xbeefcaf1 // Random word - .word 0xbeefcaf2 // Random word - .rept ((1 << 20) - 7) // (2^22 - 7) nops - nop - .endr - jr ra // return back if successful access - -//Physical Address region under testing for LEVEL 0 -- Aligned by 10 -rvtest_data_1_l0: - nop // trap return back skip - addi ra, ra, REGWIDTH - jr ra //jump back for the trap on level 1 - nop - .word 0xbeefcaf1 // Random word - .word 0xbeefcaf2 // Random word - .rept ((1 << 10) - 7) // (2^12 - 7) nops - nop - .endr - jr ra - -//--------------------------------------------------------------------------------------------------------------------------------- -//--------------------------------------------------------------------------------------------------------------------------------- - -#ifdef rvtest_strap_routine -.align 12 //complete the 4KB permission memory range -rvtest_slvl1_pg_tbl: - RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) -#endif - -RVTEST_DATA_END -.align 12 //complete the 4KB permission memory range -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - -// test signatures initialization -signature_x13_1: - .fill 256*(XLEN/32),4,0xcafebeef - -// trap signatures initialization -#ifdef rvtest_mtrap_routine -mtrap_sigptr: - .fill 64*(XLEN/32),4,0xdeadbeef -#endif - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END From b1671a4d7782c55a35261e2c99f42de28b2ec2e3 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 25 Oct 2024 21:22:53 +0500 Subject: [PATCH 09/19] model_test updated --- .../rv32/sail_cSim/env/model_test.h | 35 ++++++++++++------- .../rv32/spike_simple/env/model_test.h | 29 +++++++-------- 2 files changed, 37 insertions(+), 27 deletions(-) diff --git a/riscof-plugins/rv32/sail_cSim/env/model_test.h b/riscof-plugins/rv32/sail_cSim/env/model_test.h index 0cccc1692..decd48c1b 100644 --- a/riscof-plugins/rv32/sail_cSim/env/model_test.h +++ b/riscof-plugins/rv32/sail_cSim/env/model_test.h @@ -1,5 +1,11 @@ #ifndef _COMPLIANCE_MODEL_H #define _COMPLIANCE_MODEL_H +#if XLEN == 64 + #define ALIGNMENT 3 +#else + #define ALIGNMENT 2 +#endif + #define RVMODEL_DATA_SECTION \ .pushsection .tohost,"aw",@progbits; \ @@ -12,23 +18,26 @@ .word 4; //RV_COMPLIANCE_HALT -#define RVMODEL_HALT \ - li x1, 1; \ - write_tohost: \ - sw x1, tohost, t5; \ - j write_tohost; +#define RVMODEL_HALT ;\ +li x1, 1 ;\ +1: ;\ + sw x1, tohost, t2 ;\ + j 1b ;\ #define RVMODEL_BOOT -//RV_COMPLIANCE_DATA_BEGIN -#define RVMODEL_DATA_BEGIN \ - RVMODEL_DATA_SECTION \ - .align 4;\ - .global begin_signature; begin_signature: - -//RV_COMPLIANCE_DATA_END +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN ;\ +RVMODEL_DATA_SECTION ;\ +.align ALIGNMENT;\ +.global begin_signature ;\ +begin_signature: + +//RV_COMPLIANCE_DATA_END #define RVMODEL_DATA_END \ - .align 4; .global end_signature; end_signature: +.align ALIGNMENT;\ +.global end_signature; end_signature: + //RVTEST_IO_INIT #define RVMODEL_IO_INIT diff --git a/riscof-plugins/rv32/spike_simple/env/model_test.h b/riscof-plugins/rv32/spike_simple/env/model_test.h index d7cc7b29d..79c3c4700 100644 --- a/riscof-plugins/rv32/spike_simple/env/model_test.h +++ b/riscof-plugins/rv32/spike_simple/env/model_test.h @@ -1,5 +1,11 @@ #ifndef _COMPLIANCE_MODEL_H #define _COMPLIANCE_MODEL_H +#if XLEN == 64 + #define ALIGNMENT 3 +#else + #define ALIGNMENT 2 +#endif + #define RVMODEL_DATA_SECTION \ .pushsection .tohost,"aw",@progbits; \ .align 8; .global tohost; tohost: .dword 0; \ @@ -11,23 +17,23 @@ .word 4; //RV_COMPLIANCE_HALT -#define RVMODEL_HALT \ - li x1, 1; \ - write_tohost: \ - sw x1, tohost, t5; \ - j write_tohost; +#define RVMODEL_HALT ;\ +li x1, 1 ;\ +1: ;\ + sw x1, tohost, t2 ;\ + j 1b ;\ #define RVMODEL_BOOT //RV_COMPLIANCE_DATA_BEGIN #define RVMODEL_DATA_BEGIN \ RVMODEL_DATA_SECTION \ - .align 4;\ + .align ALIGNMENT;\ .global begin_signature; begin_signature: //RV_COMPLIANCE_DATA_END #define RVMODEL_DATA_END \ - .align 4;\ +.align ALIGNMENT;\ .global end_signature; end_signature: //RVTEST_IO_INIT @@ -43,14 +49,9 @@ //RVTEST_IO_ASSERT_DFPR_EQ #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) -#define RVMODEL_SET_MSW_INT \ - li t1, 1; \ - li t2, 0x2000000; \ - sw t1, 0(t2); +#define RVMODEL_SET_MSW_INT -#define RVMODEL_CLEAR_MSW_INT \ - li t2, 0x2000000; \ - sw x0, 0(t2); +#define RVMODEL_CLEAR_MSW_INT #define RVMODEL_CLEAR_MTIMER_INT From 69ab3e68c7513cbbe74cc8bd63fcfb82d026c94b Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 25 Oct 2024 21:35:48 +0500 Subject: [PATCH 10/19] increase the size limit to 10GB --- .github/workflows/test.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a110878be..580f2a642 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -148,7 +148,7 @@ jobs: folder_size=$(du -sm "$work_folder" | cut -f1) echo "Folder size: ${folder_size} MB" if [ "$folder_size" -gt 100000 ]; then - echo "Size exceeds 1 GB. Checking if report exists." + echo "Size exceeds 10 GB. Checking if report exists." if [ -f "$report_file" ]; then echo "Uploading RISCOF generated report only." echo "upload_path=$report_file" >> $GITHUB_ENV From 7714b2f0b8bc4fd8ffaf19e3416a7e884d18d559 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Wed, 13 Nov 2024 03:10:33 +0500 Subject: [PATCH 11/19] Update Coverpoints to use translator -> optimized and more readable --- coverage/sv32/rv32_vm_sv32.cgf | 861 +++--------------- .../vm_sv32/pmp_check_on_pa_S_mode.S | 2 +- .../vm_sv32/pmp_check_on_pa_U_mode.S | 2 +- .../vm_sv32/pmp_check_on_pte_S_mode.S | 2 +- .../vm_sv32/pmp_check_on_pte_U_mode.S | 2 +- .../privilege/vm_sv32/vm_A_and_D_S_mode.S | 15 +- .../privilege/vm_sv32/vm_A_and_D_U_mode.S | 15 +- .../privilege/vm_sv32/vm_invalid_pte_S_mode.S | 2 +- .../privilege/vm_sv32/vm_invalid_pte_U_mode.S | 2 +- .../privilege/vm_sv32/vm_misaligned_S_mode.S | 2 +- .../privilege/vm_sv32/vm_misaligned_U_mode.S | 2 +- .../rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S | 2 +- .../rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S | 2 +- .../vm_sv32/vm_nleaf_pte_level0_S_mode.S | 2 +- .../vm_sv32/vm_nleaf_pte_level0_U_mode.S | 2 +- .../vm_sv32/vm_reserved_pte_S_mode.S | 2 +- .../vm_sv32/vm_reserved_pte_U_mode.S | 2 +- 17 files changed, 178 insertions(+), 741 deletions(-) diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf index 5224244a9..c76de241e 100644 --- a/coverage/sv32/rv32_vm_sv32.cgf +++ b/coverage/sv32/rv32_vm_sv32.cgf @@ -1,663 +1,238 @@ -a_and_d_bit_soft_upd_S_mode: +#If A and D are not set, then hardware will update it atomically with the access and no faults! +a_and_d_bit_hart_upd: config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. - "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 - op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # LEVEL 1 Test Cases: - # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 2: Both A and D bits set, RWX set --> No fault. - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 - # LEVEL 0 Test Cases: - # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 - # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 - # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 - # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 - # Fault Checks: - # Test Case 1: Store Page Fault, successful page table walk for load, fetch. - 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - 'mode == "S" and mnemonic == "sw" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 - # Test Case 2: Successful page table walk at Level 1. - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 - #Test Case 3: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("RWX", iptw1cont) == 1 and get_pte_prop("AD", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 4: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("DRWX", iptw1cont) == 1 and get_pte_prop("A", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - # Test Case 5: Store Page Fault, successful page table walk for load, fetch. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 - 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 - # Test Case 6: Successful page table walk at Level 0. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1 and len_dptw == 2': 0 - #Test Case 7: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("RWX", iptw1cont) == 0 and get_pte_prop("DRWX", iptw0cont) == 1 and get_pte_prop("A", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 8: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("RWX", iptw1cont) == 0 and get_pte_prop("RWX", iptw0cont) == 1 and get_pte_prop("AD", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -a_and_d_bit_soft_upd_U_mode: - config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def HARDWARE_UPDATE_A_D=True; mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # LEVEL 1 Test Cases: - # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 2: Both A and D bits set, RWX set --> No fault. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 - # LEVEL 0 Test Cases: - # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 - # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 - # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 - # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 - # Fault Checks: - # Test Case 1: Store Page Fault, successful page table walk for load, fetch. - 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - 'mode == "U" and mnemonic == "sw" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 - # Test Case 2: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 - #Test Case 3: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("RWUX", iptw1cont) == 1 and get_pte_prop("AD", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 4: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("DRWUX", iptw1cont) == 1 and get_pte_prop("A", iptw1cont) == 0 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - # Test Case 5: Store Page Fault, successful page table walk for load, fetch. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 - 'mode == "U" and mnemonic == "sw" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and mcause == ${CAUSE_STORE_PAGE_FAULT}': 0 - # Test Case 6: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1 and len_dptw == 2': 0 - #Test Case 7: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("RWUX", iptw1cont) == 0 and get_pte_prop("DRWUX", iptw0cont) == 1 and get_pte_prop("A", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 8: expected: Load-page-fault, Store-page-fault, Fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - 'mode == "M" and get_pte_prop("RWUX", iptw1cont) == 0 and get_pte_prop("RWUX", iptw0cont) == 1 and get_pte_prop("AD", iptw0cont) == 0 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -pmp_check_pa_S_mode: - config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. - "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 - op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - # Region of Interest -> Test Section has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg - '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_TOR_MODE}': 0 + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # LEVEL 1 Test Cases: - # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 - # LEVEL 0 Test Cases: - # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 - # Fault Checks: - # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]}': 0 - 'mode == "M" and mnemonic == "jal" and mcause == 1': 0 + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw0cont) == 1': 0 + #Faults check at LEVEL 1 and LEVEL 0 + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw0cont) == 1 and len_dptw == 2': 0 -pmp_check_pa_U_mode: +#If A and D are not set, then hardware will NOT update it and we will get a respective fault ! +a_and_d_bit_soft_upd: config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def HARDWARE_UPDATE_A_D=True; mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - # Region of Interest -> Test Section has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg - '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_TOR_MODE}': 0 + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # LEVEL 1 Test Cases: - # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 - # LEVEL 0 Test Cases: - # Test Case 1: A bit set, D bit set, RWX set, NO PMP Permissions on PA --> Load-access-fault, Store-access-fault, Fetch-access-fault. - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 - # Fault Checks: - # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]}': 0 - 'mode == "M" and mnemonic == "jal" and mcause == 1': 0 + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop({"AdRWX", "ADRWX", "aDRWX", "adRWX"}, dptw0cont) == 1': 0 + #Faults check at LEVEL 1 + #Successful Accesses Cases + 'mode == {"S", "U"} and get_pte_prop({"AdRWX", "ADRWX"}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + #Load, Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop({"aDRWX", "adRWX"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}': 0 + #Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("AdRWX", dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + #Fetch Page Faults + 'mode == "M" and get_pte_prop({"aDRWX", "adRWX"}, iptw1cont) == 1 and iptw0cont == None and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + #Faults check at LEVEL 0 + #Successful Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AdRWX", "ADRWX"}, dptw0cont) == 1 and len_dptw == 2': 0 + #Load, Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"aDRWX", "adRWX"}, dptw0cont) == 1 and mcause == {15, 13}': 0 + #Store Fault Accesses Cases + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("AdRWX", dptw0cont) == 1 and mcause == 15': 0 + #Fetch Page Faults + 'mode == "M" and get_pte_prop("rwx", iptw1cont) == 1 and get_pte_prop({"aDRWX", "adRWX"}, iptw0cont) == 1 and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 -pmp_check_pte_U_mode: +#Check that when PA has no PMP Permissions, it should give Load, Store and Fetch access Faults. +pmp_check_pa: config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - # Region of Interest -> Page Table Entry has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg - '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_NA4_MODE}': 0 + 'mode == {"S", "U"} and ((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + 'mode == {"S", "U"} and (pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_TOR_MODE}': 0 val_comb: - #Note: No way to check the PTW since we will get the access fault before we are able to check the PTW, therefore, no coverpoints! - #For this case, the only way to verify that the Virtual Memory is enabled is by checking the satp register. + 'mode == {"S", "U"} and get_pte_prop({"AuDRWX", "AUDRWX"}{[$1]}, dptw1cont) == 1 and dptw0cont == None': 0 #Level 1 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"AuDRWX", "AUDRWX"}{[$1]}, dptw0cont) == 1': 0 #Level 0 # Fault Checks: - # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]} and len_dptw == 0': 0 - 'mode == "M" and mnemonic == "jal" and mcause == 1 and len_iptw == 0': 0 + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$2]}': 0 + 'mode == "M" and mnemonic == "jal" and mcause == ${CAUSE_FETCH_ACCESS}': 0 -pmp_check_pte_S_mode: +#Check that when PA has no PMP Permissions, it should give Load, Store and Fetch access Faults. +pmp_check_pte: config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - # Region of Interest -> Page Table Entry has No PMP RWX permissions set | ONLY TOR is selected in pmpcfg - '(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_NA4_MODE}': 0 + 'mode == {"S", "U"} and ((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + 'mode == {"S", "U"} and ((pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT}) == ${PMPCFG_NA4_MODE}': 0 val_comb: #Note: No way to check the PTW since we will get the access fault before we are able to check the PTW, therefore, no coverpoints! #For this case, the only way to verify that the Virtual Memory is enabled is by checking the satp register. # Fault Checks: - # Test Case 1 and 2: Load-access-fault, Store-access-fault, Fetch-access-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$1]} and len_dptw == 0': 0 - 'mode == "M" and mnemonic == "jal" and mcause == 1 and len_iptw == 0': 0 + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and mcause == {7, 5}{[$2]}': 0 + 'mode == "M" and mnemonic == "jal" and mcause == ${CAUSE_FETCH_ACCESS}': 0 -invalid_pte_SMode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # Test Case:1 -> No V bit set but RWX set -> load, store, fetch page fault - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0': 0 - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 - '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 - 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -invalid_pte_UMode: +#if the Valid bit is not set, then there should be load, store, fetch page fault +invalid_pte: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # Test Case:1 -> No V bit set but RWX set -> load, store, fetch page fault - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0': 0 - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("V", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("V", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 - '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == {"S", "U"} and get_pte_prop("RWXv", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXv", dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("RWXv", dptw1cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXv", dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 -misaligned_superpage_SMode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_dptw == 1': 0 - # Test Case:1 -> All permissions given for RWX -> still we will get RWX fault because of the misaligned super page. - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None': 0 - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 - 'mode == "M" and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -misaligned_superpage_UMode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "U" and len_dptw == 1': 0 - # Test Case:1 -> All permissions given for RWX -> still we will get RWX fault because of the misaligned super page. - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None': 0 - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 - 'mode == "M" and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -MXR_bit_SMode: +#Test Section (PA of our test VA) is misaligned -> We will get a Load, Store, Fetch Page Fault +misaligned_superpage: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - #CHECK THE SUM BIT IS SET in MSTATUS: - '(mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_{i,d}ptw == {1,2}': 0 - # Test Case:1 - 'mode == "S" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and {i, d}ptw0cont == None': 0 - # Test Case:10 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 - #Checks for Loads, Store, fetch Faults start from here - #Test Case 1: expected: store-page-fault - 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #Test Case 2: expected: store-page-fault, load-page-fault -> No MXR set with No R, so expected load page fault - 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == 15': 0 - #Test Case 3: expected: load-page-fault, store-page-fault -> No MXR set with No R, so expected load page fault - 'mode == "S" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 + 'mode == {"S", "U"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 #Make sure we get a page table walk level 1 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 -MXR_bit_UMode: +# If MXR bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault +MXR_bit: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - #CHECK THE SUM BIT IS SET in MSTATUS: '(mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "U" and len_{i,d}ptw == {1,2}': 0 - # Test Case:1 - 'mode == "U" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and {i, d}ptw0cont == None': 0 - # Test Case:10 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 - #Checks for Loads, Store, fetch Faults start from here - #Test Case 1: expected: store-page-fault - 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #Test Case 2: expected: store-page-fault, load-page-fault -> No MXR set with No R, so expected load page fault - 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == 15': 0 - #Test Case 3: expected: load-page-fault, store-page-fault -> No MXR set with No R, so expected load page fault - 'mode == "U" and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - -nonleaf_pte_level0_SMode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_dptw == 2': 0 - # Test Case:1 - 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $1ptw0cont) == 0': 0 - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $2ptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 - 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -nonleaf_pte_level0_UMode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "U" and len_dptw == 2': 0 - # Test Case:1 - 'mode == "U" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $1ptw0cont) == 0': 0 - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $2ptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 - 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + 'mode == {"S", "U"} and get_pte_prop("rwX", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwX", dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("rwX", dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("rwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) == ${MSTATUS_MXR}) and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwX", dptw0cont) == 1 and mcause == 15': 0 + 'mode == {"S", "U"} and ((mstatus & ${MSTATUS_MXR}) != ${MSTATUS_MXR}) and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwX", dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 -reserved_pte_perm_SMode: +#If a PTE at Level 0 has no RWX permissions i.e., similar to non leaf pte then give a load, store, fetch page fault +nonleaf_pte_level0: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_dptw == {1,2}': 0 - # Test Case:1 - 'mode == "S" and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 - 'mode == "S" and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:3 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0': 0 - # Test Case:4 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0': 0 - - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault, page-fault-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 4: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 - '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwx", dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("rwx", dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 -reserved_pte_perm_UMode: +#If reserved PTE permissions are chosen, then get a load, store and fetch page fault +reserved_pte_perm: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "U" and len_dptw == {1,2}': 0 - # Test Case:1 - 'mode == "U" and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 - 'mode == "U" and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:3 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0': 0 - # Test Case:4 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0': 0 - - #checks for load, store and page faults begin from here. - #Test Case 1: expected: load-page-fault, store-page-fault, page-fault-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("WX", dptw1cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault, page-fault-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("W", dptw1cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("WX", dptw0cont) == 1 and get_pte_prop("R", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 4: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("W", dptw0cont) == 1 and get_pte_prop("RX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 - '(${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - # #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 + 'mode == {"S", "U"} and get_pte_prop({"rWX", "rWx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"rWX", "rWx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop({"rWX", "rWx"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 + 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"rWX", "rWx"}, dptw0cont) == 1 and mcause == {15, 13}{[$2]}': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 +#If SUM bit is set, then User mode pages can be accessed in the Supervisor mode. U_bit_sum_set_in_SMode: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured + op_comb: 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + csr_comb: '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - #CHECK THE SUM BIT IS SET in MSTATUS: '(mstatus & ${MSTATUS_SUM}) == ${MSTATUS_SUM}': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_{i,d}ptw == {1,2}': 0 - # Test Case:1 - 'mode == "S" and get_pte_prop("URWX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case:2 - 'mode == "S" and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:3 - 'mode == "S" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:4 - 'mode == "S" and get_pte_prop("URW", dptw1cont) == 1 and get_pte_prop("X", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:5 - 'mode == "S" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:6 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URWX", dptw0cont) == 1': 0 - # Test Case:7 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 - # Test Case:8 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0': 0 - # Test Case:9 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URW", dptw0cont) == 1 and get_pte_prop("X", dptw0cont) == 0': 0 - # Test Case:10 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0': 0 - #Checks for the load, store and fetch page faults begin here - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "S" and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "S" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw0cont) == 1': 0 + #Fault Check + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UrwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop({"URwX", "URwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("UrwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URwX", "URwx"}, dptw0cont) == 1 and mcause == 15': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0 and mcause == 15': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0 and mcause == 15': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 +#If SUM bit is set, then User mode pages can be accessed in the Supervisor mode. U_bit_no_sum_set_in_SMode: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - csr_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured + op_comb: 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) + csr_comb: '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - #CHECK THE SUM BIT IS SET in MSTATUS: '(mstatus & ${MSTATUS_SUM}) != ${MSTATUS_SUM}': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_{i,d}ptw == {1,2}': 0 - # Test Case:1 - 'mode == "S" and get_pte_prop("URWX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case:2 - 'mode == "S" and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:3 - 'mode == "S" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:4 - 'mode == "S" and get_pte_prop("URW", dptw1cont) == 1 and get_pte_prop("X", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:5 - 'mode == "S" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:6 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URWX", dptw0cont) == 1': 0 - # Test Case:7 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0': 0 - # Test Case:8 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0': 0 - # Test Case:9 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URW", dptw0cont) == 1 and get_pte_prop("X", dptw0cont) == 0': 0 - # Test Case:10 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0': 0 - #Checks for Loads, Store, fetch Faults start from here - #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 5: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "S" and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "S" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw0cont) == 1': 0 + #Fault Check + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop({"UrwX", "URwX", "URwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"UrwX", "URwX", "URwx"}, dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 +#If U bit is set in U mode, then page should be accessed successfully. U_bit_set_in_UMode: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 csr_comb: - #Set up checks (Mostly M Mode) - #Check that the satp is active --> in U mode & also check that SV32 is configured 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # Testing Checks (Mostly U Mode) - # '(mnemonic == "sw" and (get_pte_prop("U", get_addr("vm_en"), rs1_val+imm_val, get_addr("rvtest_slvl1_pg_tbl")) == 1)) if ieva is not None else False': 0 - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "U" and len_{i,d}ptw == {1,2}': 0 - #---------------------------------------------------------------------------------------------- - # Test Cases for Level 1 - #---------------------------------------------------------------------------------------------- - #We expect that the U bit is set at the level 1, we are going to use the cross comb such that the - # U bit is set for the PTE at level 1 (U Mode) and the RWX is set - # Nothing is available for the PTE at the level 0 - # Side Note: This is done by the jalr instruction only at level 1 because we have no instruction at level 1 in the test - # except the jalr :( - # Test Case:1 - 'mode == "U" and get_pte_prop("URWX", {i, d}ptw1cont) == 1 and $1ptw0cont == None': 0 - # Test Case:2 - 'mode == "U" and get_pte_prop("UX", {i, d}ptw1cont) == 1 and get_pte_prop("RW", $1ptw1cont) == 0 and $1ptw0cont == None': 0 - # Test Case:3 - 'mode == "U" and get_pte_prop("URX", {i, d}ptw1cont) == 1 and get_pte_prop("W", $1ptw1cont) == 0 and $1ptw0cont == None': 0 - # Test Case:4 - 'mode == "U" and get_pte_prop("URW", dptw1cont) == 1 and get_pte_prop("X", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:5 - 'mode == "U" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None': 0 - #---------------------------------------------------------------------------------------------- - # Test Cases for Level 0 - #---------------------------------------------------------------------------------------------- - #We expect that the U bit is set at the level 0, we are going to use the cross comb such that the - # The RWX is zero meaning that it is a pointer to level 0!!! - # U bit is set for the PTE at level 1 (U Mode) and the RWX is set - # Test Case:6 - 'mode == "U" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("URWX", $1ptw0cont) == 1': 0 - # Test Case:7 - 'mode == "U" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("UX", $1ptw0cont) == 1 and get_pte_prop("RW", $1ptw0cont) == 0': 0 - # Test Case:8 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0': 0 - # Test Case:9 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URW", dptw0cont) == 1 and get_pte_prop("X", dptw0cont) == 0': 0 - # Test Case:10 - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0': 0 - #---------------------------------------------------------------------------------------------- - - #Now, we going to check that we get the required load, store, execute page faults for the ptes - #Load and stores can be checked using the same condition - #We set the U bit equal to zero and set the RWX equal to 1 but still get page fault because of no U bit in U mode - - #---------------------------------------------------------------------------------------------- - # Test Cases for Level 1 - #---------------------------------------------------------------------------------------------- - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("UX", dptw1cont) == 1 and get_pte_prop("RW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "U" and mnemonic == "sw" and get_pte_prop("URX", dptw1cont) == 1 and get_pte_prop("W", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "U" and mnemonic == "sw" and get_pte_prop("UR", dptw1cont) == 1 and get_pte_prop("WX", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "U" and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "U" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URWX", "UrwX", "URwX", "URWx", "URwx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("UrwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "U" and mnemonic == "sw" and get_pte_prop({"URwX", "URwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("UrwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "U" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"URwX", "URwx"}, dptw0cont) == 1 and mcause == 15': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - - #---------------------------------------------------------------------------------------------- - # Test Cases for Level 0 - #---------------------------------------------------------------------------------------------- - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UX", dptw0cont) == 1 and get_pte_prop("RW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "U" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("URX", dptw0cont) == 1 and get_pte_prop("W", dptw0cont) == 0 and mcause == 15': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "U" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("UR", dptw0cont) == 1 and get_pte_prop("WX", dptw0cont) == 0 and mcause == 15': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 U_bit_unset_in_UMode: @@ -666,49 +241,15 @@ U_bit_unset_in_UMode: mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 csr_comb: - #Check that the satp is active --> in U mode & also check that SV32 is configured 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "U" and len_{i,d}ptw == {1,2}': 0 - # Test Case:1 -> RWX with NO U - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("U", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 -> X with NO U - 'mode == "U" and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("URW", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:3 -> RX with NO U - 'mode == "U" and get_pte_prop("RX", dptw1cont) == 1 and get_pte_prop("UW", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:4 -> RW with NO U - 'mode == "U" and get_pte_prop("RW", dptw1cont) == 1 and get_pte_prop("UX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:5 -> R with NO U - 'mode == "U" and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:6 -> RWX with NO U - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("U", dptw0cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1': 0 - # Test Case:7 -> X with NO U - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("URW", dptw0cont) == 0': 0 - # Test Case:8 -> RX with NO U - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RX", dptw0cont) == 1 and get_pte_prop("UW", dptw0cont) == 0': 0 - # Test Case:9 -> X with NO U - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RW", dptw0cont) == 1 and get_pte_prop("UX", dptw0cont) == 0': 0 - # Test Case:10-> R with NO U - 'mode == "U" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0': 0 - #Checks for Loads, Store, fetch Faults start from here - #Test Case 2: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("URW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RX", dptw1cont) == 1 and get_pte_prop("UW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 5: expected: load-page-fault, store-page-fault, fetch-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "U" and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "U" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("URW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RX", dptw0cont) == 1 and get_pte_prop("UW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "U" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 U_bit_unset_in_SMode: @@ -717,145 +258,15 @@ U_bit_unset_in_SMode: mnemonics: "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 csr_comb: - #Check that the satp is active --> in U mode & also check that SV32 is configured 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: - # Check that the page table walk length is equal to the required walk set by the ISA. For both the {i}nstruction and {d}ata access. - 'mode == "S" and len_{i,d}ptw == {1,2}': 0 - # Test Case:1 - 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 1 and get_pte_prop("U", $1ptw1cont) == 0 and $1ptw0cont == None': 0 - # Test Case:2 - 'mode == "S" and get_pte_prop("X", {i, d}ptw1cont) == 1 and get_pte_prop("URW", $1ptw1cont) == 0 and $1ptw0cont == None': 0 - # Test Case:3 - 'mode == "S" and get_pte_prop("RX", {i, d}ptw1cont) == 1 and get_pte_prop("UW", $1ptw1cont) == 0 and $1ptw0cont == None': 0 - # Test Case:4 - 'mode == "S" and get_pte_prop("RW", dptw1cont) == 1 and get_pte_prop("UX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:5 - 'mode == "S" and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:6 - 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RWX", $1ptw0cont) == 1 and get_pte_prop("U", $1ptw0cont) == 0 ': 0 - # Test Case:7 - 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("X", $1ptw0cont) == 1 and get_pte_prop("URW", $1ptw0cont) == 0': 0 - # Test Case:8 - 'mode == "S" and get_pte_prop("RWX", {i, d}ptw1cont) == 0 and get_pte_prop("RX", $1ptw0cont) == 1 and get_pte_prop("UW", $1ptw0cont) == 0': 0 - # Test Case:9 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RW", dptw0cont) == 1 and get_pte_prop("UX", dptw0cont) == 0': 0 - # Test Case:10 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0': 0 - #Checks for Load, store, fetch page faults start from here - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("X", dptw1cont) == 1 and get_pte_prop("URW", dptw1cont) == 0 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("RX", dptw1cont) == 1 and get_pte_prop("UW", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("R", dptw1cont) == 1 and get_pte_prop("UWX", dptw1cont) == 0 and dptw0cont == None and mcause == 15': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l1(address space with No U Bit) + 4MB - 4 in the case of level 1 + 'mode == "S" and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "S" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRWX", "urwX", "uRwX", "uRWx", "uRwx"}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("urwX", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop({"uRwX", "uRwx"}, dptw1cont) == 1 and dptw0cont == None and mcause == 15': 0 + 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("urwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 + 'mode == "S" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRwX", "uRwx"}, dptw0cont) == 1 and mcause == 15': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - #Test Case 2: expected: load-page-fault, store-page-fault - 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("X", dptw0cont) == 1 and get_pte_prop("URW", dptw0cont) == 0 and mcause == {15, 13}{[$1]}': 0 - #Test Case 3: expected: store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RX", dptw0cont) == 1 and get_pte_prop("UW", dptw0cont) == 0 and mcause == 15': 0 - #Test Case 5: expected: fetch-page-fault, store-page-fault - 'mode == "S" and mnemonic == "sw" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("R", dptw0cont) == 1 and get_pte_prop("UWX", dptw0cont) == 0 and mcause == 15': 0 - #fetch-page-fault check -> mtval value should be equal to the virtual address va_data_1_l0(address space with no U bit) + 4KB - 4 in the case of level 0 - 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - -a_and_d_bit_hart_upd_S_mode: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - op_comb: - #Check that the satp is active --> in S mode & also check that SV32 is configured - 'mode == "S" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - csr_comb: - #The ppn of rvtest_Sroot_pg_tbl should be equal to the satp lower 22 bits (when the satp is active) - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - #CASES at LEVEL 1 - # Test Case:1 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 1 - 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:2 -> D bit set and A bit set and RWX set -> NO FAULT -- LEVEL 1 - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case:3 -> D bit set but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 - 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case:4 -> No D bit unset but A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 1 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 - #CASES at LEVEL 0 - # Test Case:5 -> No D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 - # Test Case:6 -> D bit set and A bit set and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1': 0 - # Test Case:7 -> D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 - # Test Case:8 -> No D bit set and A bit unset and RWX set -> NO FAULT and PTE update -- LEVEL 0 - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 - #Faults check at LEVEL 1 and LEVEL 0 - #Test Case:1 --> successfull page table walk - 'mode == "S" and get_pte_prop("ARWX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:2 --> successfull page table walk - 'mode == "S" and get_pte_prop("ADRWX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:3 --> successfull page table walk - 'mode == "S" and get_pte_prop("DRWX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:4 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - #Test Case:5 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ARWX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 - #Test Case:6 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("ADRWX", dptw0cont) == 1 and len_dptw == 2': 0 - #Test Case:7 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("DRWX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 - #Test Case:8 --> successfull page table walk - 'mode == "S" and get_pte_prop("RWX", dptw1cont) == 0 and get_pte_prop("RWX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 - -a_and_d_bit_hart_upd_U_mode: - config: - # Ensure that the ISA is 32-bit, and the supported extensions include I and Zicsr. - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; - mnemonics: - # Verify that the following instructions are tested: sw, csrrc, csrrs, csrrw, lw, jalr. - "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 - op_comb: - # Check if the `satp` is active in Supervisor mode (S) and verify that the SV32 paging scheme is configured. - 'mode == "U" and (satp >> 31) == ${SATP_MODE_SV32}': 0 - csr_comb: - # Ensure that the Physical Page Number (PPN) of `rvtest_Sroot_pg_tbl` matches the lower 22 bits of the `satp` register when `satp` is active. - '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 - val_comb: - # LEVEL 1 Test Cases: - # Test Case 1: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 2: Both A and D bits set, RWX set --> No fault. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None': 0 - # Test Case 3: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None': 0 - # Test Case 4: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None': 0 - # LEVEL 0 Test Cases: - # Test Case 5: A bit set, D bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0': 0 - # Test Case 6: Both A and D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1': 0 - # Test Case 7: D bit set, A bit not set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0': 0 - # Test Case 8: Neither A nor D bits set, RWX set --> No fault, and the PTE should be updated. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0': 0 - # Fault Checks: - # Test Case 1: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("ARWUX", dptw1cont) == 1 and get_pte_prop("D", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 2: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("ADRWUX", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 3: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("DRWUX", dptw1cont) == 1 and get_pte_prop("A", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 4: Successful page table walk at Level 1. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 1 and get_pte_prop("AD", dptw1cont) == 0 and dptw0cont == None and len_dptw == 1': 0 - # Test Case 5: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ARWUX", dptw0cont) == 1 and get_pte_prop("D", dptw0cont) == 0 and len_dptw == 2': 0 - # Test Case 6: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("ADRWUX", dptw0cont) == 1 and len_dptw == 2': 0 - # Test Case 7: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("DRWUX", dptw0cont) == 1 and get_pte_prop("A", dptw0cont) == 0 and len_dptw == 2': 0 - # Test Case 8: Successful page table walk at Level 0. - 'mode == "U" and get_pte_prop("RWUX", dptw1cont) == 0 and get_pte_prop("RWUX", dptw0cont) == 1 and get_pte_prop("AD", dptw0cont) == 0 and len_dptw == 2': 0 + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S index c1a58e94c..173770638 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S @@ -37,7 +37,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa_S_mode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S index bdde6274a..4258538a4 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S @@ -37,7 +37,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa_U_mode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pa) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S index 5841cde76..c07982092 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S @@ -37,7 +37,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte_S_mode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S index acd951aa7..28c8b2254 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S @@ -37,7 +37,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte_U_mode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS; mac PMP_MACROS",pmp_check_pte) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S index 4f6db6458..b0ffeab68 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S @@ -66,8 +66,13 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN +/* + ! If the hardware updates the A and D bit, Please add " def HARDWARE_UPDATE_A_D=True; " in the RVTEST_CASE + SOFTWARE_UPDATE_A_D=True is defined here by default, replace when using the hardware update +*/ + #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd_S_mode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def SOFTWARE_UPDATE_A_D=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", a_and_d_bit_soft_upd, a_and_d_bit_hart_upd) RVTEST_SIGBASE( x13,signature_x13_1) // ------------------------------------------------------------------------------------------------------------ @@ -238,8 +243,10 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) sfence.vma + #endif TEST_CASES_RUNNER Smode, va_data, LEVEL1 @@ -250,8 +257,10 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL1) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) sfence.vma + #endif TEST_CASES_RUNNER Smode, va_data, LEVEL1 @@ -286,9 +295,11 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) sfence.vma + #endif TEST_CASES_RUNNER Smode, va_data, LEVEL0 @@ -300,9 +311,11 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_V), va_data, LEVEL0) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) sfence.vma + #endif TEST_CASES_RUNNER Smode, va_data, LEVEL0 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S index a7148478c..6ec4ef4c7 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S @@ -64,8 +64,13 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN +/* + ! If the hardware updates the A and D bit, Please add " def HARDWARE_UPDATE_A_D=True; " in the RVTEST_CASE + SOFTWARE_UPDATE_A_D=True is defined here by default, replace when using the hardware update +*/ + #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd_U_mode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def SOFTWARE_UPDATE_A_D=True; def TEST_CASE_1=True; mac SV32_MACROS",a_and_d_bit_soft_upd, a_and_d_bit_hart_upd) RVTEST_SIGBASE( x13,signature_x13_1) // ------------------------------------------------------------------------------------------------------------ @@ -236,8 +241,10 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) sfence.vma + #endif TEST_CASES_RUNNER Umode, va_data, LEVEL1 @@ -248,8 +255,10 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL1) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l1, LEVEL1) sfence.vma + #endif TEST_CASES_RUNNER Umode, va_data, LEVEL1 @@ -284,9 +293,11 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D |PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) sfence.vma + #endif TEST_CASES_RUNNER Umode, va_data, LEVEL0 @@ -298,9 +309,11 @@ main: PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_X| PTE_W| PTE_R| PTE_U | PTE_V), va_data, LEVEL0) sfence.vma + #ifdef SOFTWARE_UPDATE_A_D PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_U | PTE_V), va_return_page_l0, LEVEL0) sfence.vma + #endif TEST_CASES_RUNNER Umode, va_data, LEVEL0 diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S index 065d5b221..8182e5ee6 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S @@ -37,7 +37,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",invalid_pte_SMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",invalid_pte) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S index ba8442050..7a5136595 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S @@ -38,7 +38,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", invalid_pte_UMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", invalid_pte) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S index 2012aa237..b8df0ee6c 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S @@ -32,7 +32,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage_SMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S index 5fe80ad22..5d366bc7a 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S @@ -32,7 +32,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage_UMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",misaligned_superpage) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S index 780ce0461..bd61564a1 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S @@ -40,7 +40,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit_SMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S index 6f0341098..b646b63ee 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S @@ -40,7 +40,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit_UMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",MXR_bit) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S index 956b47ff8..83e43f743 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S @@ -32,7 +32,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0_SMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S index 5a879f1d7..eaf8bf5b6 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S @@ -32,7 +32,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0_UMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",nonleaf_pte_level0) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S index a0142752d..f2c9dc3ca 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S @@ -38,7 +38,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm_SMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S index 49ab686af..c46db6aa9 100644 --- a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S @@ -38,7 +38,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm_UMode) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- From a079bb263b04dde4028efee134f3a4e42799a5ca Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 15 Nov 2024 04:15:46 +0500 Subject: [PATCH 12/19] Move the Virtual Memory SV-32 Tests to follow directory structure --- .../{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pa_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pa_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pte_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pte_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_A_and_D_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_A_and_D_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_U_Bit_set_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_U_Bit_unset_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_U_Bit_unset_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_invalid_pte_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_invalid_pte_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_misaligned_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_misaligned_U_mode.S | 0 .../rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_mxr_S_mode.S | 0 .../rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_mxr_U_mode.S | 0 .../vm_sv32 => vm_sv32/src}/vm_nleaf_pte_level0_S_mode.S | 0 .../vm_sv32 => vm_sv32/src}/vm_nleaf_pte_level0_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_reserved_pte_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_reserved_pte_U_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_sum_set_S_mode.S | 0 .../{privilege/vm_sv32 => vm_sv32/src}/vm_sum_unset_S_mode.S | 0 21 files changed, 0 insertions(+), 0 deletions(-) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pa_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pa_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pte_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/pmp_check_on_pte_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_A_and_D_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_A_and_D_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_U_Bit_set_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_U_Bit_unset_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_U_Bit_unset_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_invalid_pte_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_invalid_pte_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_misaligned_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_misaligned_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_mxr_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_mxr_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_nleaf_pte_level0_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_nleaf_pte_level0_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_reserved_pte_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_reserved_pte_U_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_sum_set_S_mode.S (100%) rename riscv-test-suite/rv32i_m/{privilege/vm_sv32 => vm_sv32/src}/vm_sum_unset_S_mode.S (100%) diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pa_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/pmp_check_on_pte_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_A_and_D_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_set_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_set_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_U_Bit_unset_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_U_Bit_unset_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_invalid_pte_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_misaligned_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_mxr_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_mxr_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_nleaf_pte_level0_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_reserved_pte_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_set_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S diff --git a/riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S similarity index 100% rename from riscv-test-suite/rv32i_m/privilege/vm_sv32/vm_sum_unset_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S From 496c5f6bb3ccda8f6e237102ad68dad341713b6b Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Thu, 21 Nov 2024 23:43:07 +0500 Subject: [PATCH 13/19] Move the PMP Covergroups to follow directory structure --- coverage/rv32_pmp.cgf | 836 ------------------------------------------ coverage/rv64_pmp.cgf | 836 ------------------------------------------ 2 files changed, 1672 deletions(-) delete mode 100644 coverage/rv32_pmp.cgf delete mode 100644 coverage/rv64_pmp.cgf diff --git a/coverage/rv32_pmp.cgf b/coverage/rv32_pmp.cgf deleted file mode 100644 index 1b65ddc5d..000000000 --- a/coverage/rv32_pmp.cgf +++ /dev/null @@ -1,836 +0,0 @@ -# This coverpoint checks the coverage of Lock bit test. -# req = The old value of the pmpcfgs and pmpaddrs should be equal to the new one since the Lock bit is set and the new write try will fail. -pmp_cfg_locked_write_unrelated: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw}" : 0 - csr_comb: - # (Lock bit set) and (req) and (old_value_pmpcfg != 0) - (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$2%4]} & 0x80 == 0x80) and (((old("pmpcfg$2") ^ pmpcfg$2) >> $3 & 0xFF) == 0x00) and old("pmpcfg$2") != 0: 0 - (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$1%4]} & 0x80 == 0x80) and (old("pmpaddr$1") == (pmpaddr$1)) and (pmpcfg$2 != 0): 0 - -#This coverpoint checks the coverage of pmp-CSR-access.cgf (PMP CSRs accesses in different modes) -#Checks pmpcgf and pmpaddr are only accessible in M mode and gets fault in S and U mode when accessed. -PMP_access_permission: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw}" : 0 - csr_comb: - #Check successful update for pmpcfg in M Mode - mode == 'M' and ((old("pmpcfg{0 ... 3}") != (pmpcfg$1)) and pmpcfg$1 != 0x0): 0 - #Check successful update for pmpaddr in M Mode - mode == 'M' and ((old("pmpaddr{0 ... 15}") != (pmpaddr$1)) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode - #Check for fault for pmpcfg, pmpaddr in S, U Mode - mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault - -# This coverpoint checks the coverage for the pmp-NAPOT-R.S -# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. -PMP_NAPOT_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-X.S -# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. -PMP_NAPOT_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-RW.S -# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. -PMP_NAPOT_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-RX.S -# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. -PMP_NAPOT_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-RWX.S -# R,W,X bit is set for pmpcfg, so there should be NO access fault. -PMP_NAPOT_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - val_comb: - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-R.S -# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. -PMP_TOR_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x89) and ${TOR_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-X.S -# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. -PMP_TOR_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8C) and ${TOR_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-RW.S -# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. -PMP_TOR_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-RX.S -# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. -PMP_TOR_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-RWX.S -# R,W,X bit is set for pmpcfg, so there should be NO access fault. -PMP_TOR_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - val_comb: - #Check the tor region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-R.S -# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. -PMP_NA4_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-X.S -# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. -PMP_NA4_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit not set, W bit not set, X bit set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-RW.S -# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. -PMP_NA4_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-RX.S -# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. -PMP_NA4_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-RWX.S -# R,W,X bit is set for pmpcfg, so there should be NO access fault. -PMP_NA4_rwx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - val_comb: - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x97) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_r_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R permission -- NAPOT region selected -# R succeeds while we get Store fault and fetch access fault -PMP_NAPOT_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x99) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_x_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets X permission -- NAPOT region selected -# fetch succeeds while we get read access fault and store access fault -PMP_NAPOT_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets RW permission -- NAPOT region selected -# load, store succeeds while we get fetch access fault -PMP_NAPOT_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R X permission -- NAPOT region selected -# load, fetch succeeds while we get store access fault -PMP_NAPOT_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_r_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R permission -- TOR region selected -# R succeeds while we get Store fault and fetch access fault -PMP_TOR_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x89) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_x_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets X permission -- TOR region selected -# X succeeds while we get load and store access faults -PMP_TOR_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rw_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets RW permission -- TOR region selected -# R,W succeeds while we get fetch access fault -PMP_TOR_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rx_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R X permission -- TOR region selected -# R,X succeeds while we get store access faults -PMP_TOR_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_r_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R permission -- NA4 region selected -# R succeeds while we get store and fetch access fault -PMP_NA4_priority_r: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x91) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_x_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets X permission -- NA4 region selected -# X succeeds while we get load and store access fault -PMP_NA4_priority_x: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x94) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rw_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets RW permission -- NA4 region selected -# R,W succeeds while we get fetch access fault -PMP_NA4_priority_rw: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x93) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rx_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R X permission -- NA4 region selected -# R,X succeeds while we get store access fault -PMP_NA4_priority_rx: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x95) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_r_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R permission -- NAPOT region selected -# R succeeds while we get Store fault and fetch access fault -PMP_NAPOT_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_x_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets X permission -- NAPOT region selected -# X succeeds while we get load and store access fault -PMP_NAPOT_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NAPOT region selected -# R,W succeeds while we get fetch access fault -PMP_NAPOT_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NAPOT region selected -# R,X succeeds while we get store access fault -PMP_NAPOT_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_r_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R permission -- TOR region selected -# R succeeds while we get store and fetch access fault -PMP_TOR_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x89) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_x_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets X permission -- TOR region selected -# X succeeds while we get load and store access fault -PMP_TOR_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rw_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets RW permission -- TOR region selected -# R,W succeeds while we get fetch access fault -PMP_TOR_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rx_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R X permission -- TOR region selected -# R, X succeeds while we get store access fault -PMP_TOR_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_r_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R permission -- NA4 region selected -# R succeeds while we get store and fetch access fault -PMP_NA4_priority_r_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rw_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NA4 region selected -# R,W succeeds while we get fetch access fault -PMP_NA4_priority_rw_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_x_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets X permission -- NA4 region selected -# X succeeds while we get load and store access fault -PMP_NA4_priority_x_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw instruction - mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rx_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NA4 region selected -# R,X succeeds while we get store access fault -PMP_NA4_priority_rx_level_2: - config: - - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw instruction - mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 diff --git a/coverage/rv64_pmp.cgf b/coverage/rv64_pmp.cgf deleted file mode 100644 index 616dbad5f..000000000 --- a/coverage/rv64_pmp.cgf +++ /dev/null @@ -1,836 +0,0 @@ -# This coverpoint checks the coverage of Lock bit test. -# req = The old value of the pmpcfgs and pmpaddrs should be equal to the new one since the Lock bit is set and the new write try will fail. -pmp_cfg_locked_write_unrelated: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw}" : 0 - csr_comb: - # (Lock bit set) and (req) and (old_value_pmpcfg != 0) - (old("pmpaddr{0 ... 15}") ^ (pmpaddr$1) == 0x00) and (pmpcfg{0,2}{[$1/8]} >> {[($1%8)*8]} & 0x80 == 0x80): 0 - (pmpcfg{0, 2} >> {[($1%8)*8]} & 0x80 == 0x80) and ((old("pmpcfg$1") & (0xFF << $2)) ^ (pmpcfg$1 & (0xFF << $2)) == 0x00) and old("pmpcfg$1") != 0: 0 - -#This coverpoint checks the coverage of pmp-CSR-access.cgf (PMP CSRs accesses in different modes) -#Checks pmpcgf and pmpaddr are only accessible in M mode and gets fault in S and U mode when accessed. -PMP_access_permission: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw}" : 0 - csr_comb: - #Check successful update for pmpcfg in M Mode - mode == 'M' and (((old("pmpcfg{0 , 2}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0 #pmpcfg successfully updated in M mode - #Check successful update for pmpaddr in M Mode - mode == 'M' and (((old("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode - #Check for fault for pmpcfg, pmpaddr in S, U Mode - mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault - -# This coverpoint checks the coverage for the pmp-NAPOT-R.S -# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. -PMP_NAPOT_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-X.S -# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. -PMP_NAPOT_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-RW.S -# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. -PMP_NAPOT_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-RX.S -# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. -PMP_NAPOT_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NAPOT-RWX.S -# R,W,X bit is set for pmpcfg, so there should be NO access fault. -PMP_NAPOT_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - val_comb: - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-R.S -# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. -PMP_TOR_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x89) and ${TOR_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-X.S -# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. -PMP_TOR_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8C) and ${TOR_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-RW.S -# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. -PMP_TOR_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-RX.S -# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. -PMP_TOR_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the tor region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-TOR-RWX.S -# R,W,X bit is set for pmpcfg, so there should be NO access fault. -PMP_TOR_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - val_comb: - #Check the tor region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-R.S -# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. -PMP_NA4_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-X.S -# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. -PMP_NA4_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit not set, W bit not set, X bit set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-RW.S -# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. -PMP_NA4_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-RX.S -# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. -PMP_NA4_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the pmp-NA4-RWX.S -# R,W,X bit is set for pmpcfg, so there should be NO access fault. -PMP_NA4_rwx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - val_comb: - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x97) and ${NA4_REGION_ADDRESS_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_r_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R permission -- NAPOT region selected -# R succeeds while we get Store fault and fetch access fault -PMP_NAPOT_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x99) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_x_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets X permission -- NAPOT region selected -# fetch succeeds while we get read access fault and store access fault -PMP_NAPOT_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets RW permission -- NAPOT region selected -# load, store succeeds while we get fetch access fault -PMP_NAPOT_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R X permission -- NAPOT region selected -# load, fetch succeeds while we get store access fault -PMP_NAPOT_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_r_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R permission -- TOR region selected -# R succeeds while we get Store fault and fetch access fault -PMP_TOR_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x89) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_x_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets X permission -- TOR region selected -# X succeeds while we get load and store access faults -PMP_TOR_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rw_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets RW permission -- TOR region selected -# R,W succeeds while we get fetch access fault -PMP_TOR_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rx_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R X permission -- TOR region selected -# R,X succeeds while we get store access faults -PMP_TOR_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and ${TOR_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_r_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R permission -- NA4 region selected -# R succeeds while we get store and fetch access fault -PMP_NA4_priority_r: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x91) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_x_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets X permission -- NA4 region selected -# X succeeds while we get load and store access fault -PMP_NA4_priority_x: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x94) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rw_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets RW permission -- NA4 region selected -# R,W succeeds while we get fetch access fault -PMP_NA4_priority_rw: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x93) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rx_priority.S -# This is a priority test. -# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0 --> high priority entry gets R X permission -- NA4 region selected -# R,X succeeds while we get store access fault -PMP_NA4_priority_rx: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the na4 region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x95) and ${NA4_PRIORITY_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_r_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R permission -- NAPOT region selected -# R succeeds while we get Store fault and fetch access fault -PMP_NAPOT_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_x_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets X permission -- NAPOT region selected -# X succeeds while we get load and store access fault -PMP_NAPOT_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NAPOT region selected -# R,W succeeds while we get fetch access fault -PMP_NAPOT_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NAPOT region selected -# R,X succeeds while we get store access fault -PMP_NAPOT_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_r_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R permission -- TOR region selected -# R succeeds while we get store and fetch access fault -PMP_TOR_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x89) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_x_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets X permission -- TOR region selected -# X succeeds while we get load and store access fault -PMP_TOR_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rw_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets RW permission -- TOR region selected -# R,W succeeds while we get fetch access fault -PMP_TOR_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_TOR_rx_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R X permission -- TOR region selected -# R, X succeeds while we get store access fault -PMP_TOR_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_r_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R permission -- NA4 region selected -# R succeeds while we get store and fetch access fault -PMP_NA4_priority_r_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rw_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NA4 region selected -# R,W succeeds while we get fetch access fault -PMP_NA4_priority_rw_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 - val_comb: - #Check for execute fault - mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_x_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets X permission -- NA4 region selected -# X succeeds while we get load and store access fault -PMP_NA4_priority_x_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check for load fault on lb, lh, lw, ld instruction - mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 - -# This coverpoint checks the coverage for the PMP_NA4_rx_priority_level_2.S -# This is a priority test. -# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected -# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected -# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NA4 region selected -# R,X succeeds while we get store access fault -PMP_NA4_priority_rx_level_2: - config: - - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; - mnemonics: - "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 - csr_comb: - # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set - "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 - # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set - "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 - # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set - "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 - val_comb: - #Check for store fault on sb , sh, sw, sd instruction - mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 - #Check the napot region is accessed at least once - '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 From 77477c4724272326db7e215d5e41322a231ab0af Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Thu, 21 Nov 2024 23:44:33 +0500 Subject: [PATCH 14/19] Move the PMP Covergroups to follow directory structure --- coverage/pmp/rv32_pmp.cgf | 836 ++++++++++++++++++++++++++++++++++++++ coverage/pmp/rv64_pmp.cgf | 836 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 1672 insertions(+) create mode 100644 coverage/pmp/rv32_pmp.cgf create mode 100644 coverage/pmp/rv64_pmp.cgf diff --git a/coverage/pmp/rv32_pmp.cgf b/coverage/pmp/rv32_pmp.cgf new file mode 100644 index 000000000..1b65ddc5d --- /dev/null +++ b/coverage/pmp/rv32_pmp.cgf @@ -0,0 +1,836 @@ +# This coverpoint checks the coverage of Lock bit test. +# req = The old value of the pmpcfgs and pmpaddrs should be equal to the new one since the Lock bit is set and the new write try will fail. +pmp_cfg_locked_write_unrelated: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw}" : 0 + csr_comb: + # (Lock bit set) and (req) and (old_value_pmpcfg != 0) + (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$2%4]} & 0x80 == 0x80) and (((old("pmpcfg$2") ^ pmpcfg$2) >> $3 & 0xFF) == 0x00) and old("pmpcfg$2") != 0: 0 + (pmpcfg{{0 ... 15} >> 2} >> {0, 8, 16, 24}{[$1%4]} & 0x80 == 0x80) and (old("pmpaddr$1") == (pmpaddr$1)) and (pmpcfg$2 != 0): 0 + +#This coverpoint checks the coverage of pmp-CSR-access.cgf (PMP CSRs accesses in different modes) +#Checks pmpcgf and pmpaddr are only accessible in M mode and gets fault in S and U mode when accessed. +PMP_access_permission: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw}" : 0 + csr_comb: + #Check successful update for pmpcfg in M Mode + mode == 'M' and ((old("pmpcfg{0 ... 3}") != (pmpcfg$1)) and pmpcfg$1 != 0x0): 0 + #Check successful update for pmpaddr in M Mode + mode == 'M' and ((old("pmpaddr{0 ... 15}") != (pmpaddr$1)) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode + #Check for fault for pmpcfg, pmpaddr in S, U Mode + mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault + +# This coverpoint checks the coverage for the pmp-NAPOT-R.S +# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. +PMP_NAPOT_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-X.S +# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. +PMP_NAPOT_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-RW.S +# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. +PMP_NAPOT_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-RX.S +# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. +PMP_NAPOT_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-RWX.S +# R,W,X bit is set for pmpcfg, so there should be NO access fault. +PMP_NAPOT_rwx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + val_comb: + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-R.S +# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. +PMP_TOR_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x89) and ${TOR_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-X.S +# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. +PMP_TOR_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8C) and ${TOR_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-RW.S +# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. +PMP_TOR_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-RX.S +# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. +PMP_TOR_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-RWX.S +# R,W,X bit is set for pmpcfg, so there should be NO access fault. +PMP_TOR_rwx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + val_comb: + #Check the tor region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-R.S +# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. +PMP_NA4_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-X.S +# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. +PMP_NA4_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit not set, W bit not set, X bit set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-RW.S +# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. +PMP_NA4_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-RX.S +# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. +PMP_NA4_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-RWX.S +# R,W,X bit is set for pmpcfg, so there should be NO access fault. +PMP_NA4_rwx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + val_comb: + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x97) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_r_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R permission -- NAPOT region selected +# R succeeds while we get Store fault and fetch access fault +PMP_NAPOT_priority_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x99) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_x_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets X permission -- NAPOT region selected +# fetch succeeds while we get read access fault and store access fault +PMP_NAPOT_priority_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets RW permission -- NAPOT region selected +# load, store succeeds while we get fetch access fault +PMP_NAPOT_priority_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R X permission -- NAPOT region selected +# load, fetch succeeds while we get store access fault +PMP_NAPOT_priority_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_r_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R permission -- TOR region selected +# R succeeds while we get Store fault and fetch access fault +PMP_TOR_priority_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x89) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_x_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets X permission -- TOR region selected +# X succeeds while we get load and store access faults +PMP_TOR_priority_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rw_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets RW permission -- TOR region selected +# R,W succeeds while we get fetch access fault +PMP_TOR_priority_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rx_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R X permission -- TOR region selected +# R,X succeeds while we get store access faults +PMP_TOR_priority_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_r_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R permission -- NA4 region selected +# R succeeds while we get store and fetch access fault +PMP_NA4_priority_r: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x91) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_x_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets X permission -- NA4 region selected +# X succeeds while we get load and store access fault +PMP_NA4_priority_x: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x94) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rw_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets RW permission -- NA4 region selected +# R,W succeeds while we get fetch access fault +PMP_NA4_priority_rw: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x93) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rx_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R X permission -- NA4 region selected +# R,X succeeds while we get store access fault +PMP_NA4_priority_rx: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x95) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_r_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R permission -- NAPOT region selected +# R succeeds while we get Store fault and fetch access fault +PMP_NAPOT_priority_r_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_x_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets X permission -- NAPOT region selected +# X succeeds while we get load and store access fault +PMP_NAPOT_priority_x_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NAPOT region selected +# R,W succeeds while we get fetch access fault +PMP_NAPOT_priority_rw_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NAPOT region selected +# R,X succeeds while we get store access fault +PMP_NAPOT_priority_rx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_r_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R permission -- TOR region selected +# R succeeds while we get store and fetch access fault +PMP_TOR_priority_r_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x89) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_x_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets X permission -- TOR region selected +# X succeeds while we get load and store access fault +PMP_TOR_priority_x_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rw_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets RW permission -- TOR region selected +# R,W succeeds while we get fetch access fault +PMP_TOR_priority_rw_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rx_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R X permission -- TOR region selected +# R, X succeeds while we get store access fault +PMP_TOR_priority_rx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_r_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R permission -- NA4 region selected +# R succeeds while we get store and fetch access fault +PMP_NA4_priority_r_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rw_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NA4 region selected +# R,W succeeds while we get fetch access fault +PMP_NA4_priority_rw_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_x_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets X permission -- NA4 region selected +# X succeeds while we get load and store access fault +PMP_NA4_priority_x_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw instruction + mnemonic == {'lb', 'lh', 'lw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rx_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NA4 region selected +# R,X succeeds while we get store access fault +PMP_NA4_priority_rx_level_2: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg3 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw instruction + mnemonic == {'sb', 'sh', 'sw'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"lw", "lh", "lb", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 diff --git a/coverage/pmp/rv64_pmp.cgf b/coverage/pmp/rv64_pmp.cgf new file mode 100644 index 000000000..616dbad5f --- /dev/null +++ b/coverage/pmp/rv64_pmp.cgf @@ -0,0 +1,836 @@ +# This coverpoint checks the coverage of Lock bit test. +# req = The old value of the pmpcfgs and pmpaddrs should be equal to the new one since the Lock bit is set and the new write try will fail. +pmp_cfg_locked_write_unrelated: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw}" : 0 + csr_comb: + # (Lock bit set) and (req) and (old_value_pmpcfg != 0) + (old("pmpaddr{0 ... 15}") ^ (pmpaddr$1) == 0x00) and (pmpcfg{0,2}{[$1/8]} >> {[($1%8)*8]} & 0x80 == 0x80): 0 + (pmpcfg{0, 2} >> {[($1%8)*8]} & 0x80 == 0x80) and ((old("pmpcfg$1") & (0xFF << $2)) ^ (pmpcfg$1 & (0xFF << $2)) == 0x00) and old("pmpcfg$1") != 0: 0 + +#This coverpoint checks the coverage of pmp-CSR-access.cgf (PMP CSRs accesses in different modes) +#Checks pmpcgf and pmpaddr are only accessible in M mode and gets fault in S and U mode when accessed. +PMP_access_permission: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw}" : 0 + csr_comb: + #Check successful update for pmpcfg in M Mode + mode == 'M' and (((old("pmpcfg{0 , 2}") ^ (pmpcfg$1)) != 0x00) and pmpcfg$1 != 0x0): 0 #pmpcfg successfully updated in M mode + #Check successful update for pmpaddr in M Mode + mode == 'M' and (((old("pmpaddr{0 ... 15}") ^ (pmpaddr$1)) != 0x00) and pmpaddr$1 != 0x0): 0 #pmpaddr successfully updated in M mode + #Check for fault for pmpcfg, pmpaddr in S, U Mode + mode == {'S', 'U'} and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0 #check for illegal instruction fault + +# This coverpoint checks the coverage for the pmp-NAPOT-R.S +# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. +PMP_NAPOT_r: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-X.S +# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. +PMP_NAPOT_x: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-RW.S +# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. +PMP_NAPOT_rw: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-RX.S +# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. +PMP_NAPOT_rx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NAPOT-RWX.S +# R,W,X bit is set for pmpcfg, so there should be NO access fault. +PMP_NAPOT_rwx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + val_comb: + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-R.S +# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. +PMP_TOR_r: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x89) and ${TOR_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-X.S +# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. +PMP_TOR_x: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8C) and ${TOR_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-RW.S +# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. +PMP_TOR_rw: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8B) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-RX.S +# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. +PMP_TOR_rx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the tor region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8D) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-TOR-RWX.S +# R,W,X bit is set for pmpcfg, so there should be NO access fault. +PMP_TOR_rwx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 16) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + val_comb: + #Check the tor region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 16) & 0x9F == 0x8F) and ${NAPOT_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-R.S +# R bit is set for pmpcfg but wx is not set for the region, so there should be store and fetch access fault. +PMP_NA4_r: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-X.S +# X bit is set for pmpcfg but RW is not set for the region, so there should be load and store access fault. +PMP_NA4_x: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit not set, W bit not set, X bit set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-RW.S +# RW bit is set for pmpcfg but X is not set for the region, so there should be fetch access fault. +PMP_NA4_rw: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-RX.S +# RX bit is set for pmpcfg but W is not set for the region, so there should be store access fault. +PMP_NA4_rx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the pmp-NA4-RWX.S +# R,W,X bit is set for pmpcfg, so there should be NO access fault. +PMP_NA4_rwx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + val_comb: + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x97) and ${NA4_REGION_ADDRESS_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_r_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R permission -- NAPOT region selected +# R succeeds while we get Store fault and fetch access fault +PMP_NAPOT_priority_r: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x99) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_x_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets X permission -- NAPOT region selected +# fetch succeeds while we get read access fault and store access fault +PMP_NAPOT_priority_x: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets RW permission -- NAPOT region selected +# load, store succeeds while we get fetch access fault +PMP_NAPOT_priority_rw: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R X permission -- NAPOT region selected +# load, fetch succeeds while we get store access fault +PMP_NAPOT_priority_rx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_r_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R permission -- TOR region selected +# R succeeds while we get Store fault and fetch access fault +PMP_TOR_priority_r: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x89) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_x_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets X permission -- TOR region selected +# X succeeds while we get load and store access faults +PMP_TOR_priority_x: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8C) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rw_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets RW permission -- TOR region selected +# R,W succeeds while we get fetch access fault +PMP_TOR_priority_rw: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8B) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rx_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R X permission -- TOR region selected +# R,X succeeds while we get store access faults +PMP_TOR_priority_rx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x8D) and ${TOR_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_r_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R permission -- NA4 region selected +# R succeeds while we get store and fetch access fault +PMP_NA4_priority_r: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x91) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_x_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets X permission -- NA4 region selected +# X succeeds while we get load and store access fault +PMP_NA4_priority_x: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x94) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rw_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets RW permission -- NA4 region selected +# R,W succeeds while we get fetch access fault +PMP_NA4_priority_rw: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x93) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rx_priority.S +# This is a priority test. +# pmpcfg3 --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0 --> high priority entry gets R X permission -- NA4 region selected +# R,X succeeds while we get store access fault +PMP_NA4_priority_rx: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the na4 region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 24) & 0x9F == 0x95) and ${NA4_PRIORITY_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_r_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R permission -- NAPOT region selected +# R succeeds while we get Store fault and fetch access fault +PMP_NAPOT_priority_r_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x99) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_x_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets X permission -- NAPOT region selected +# X succeeds while we get load and store access fault +PMP_NAPOT_priority_x_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9C) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rw_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NAPOT region selected +# R,W succeeds while we get fetch access fault +PMP_NAPOT_priority_rw_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9B) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NAPOT_rx_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NAPOT region selected +# R,X succeeds while we get store access fault +PMP_NAPOT_priority_rx_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NAPOT Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NAPOT_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x9D) and ${NAPOT_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_r_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R permission -- TOR region selected +# R succeeds while we get store and fetch access fault +PMP_TOR_priority_r_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x89) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_x_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets X permission -- TOR region selected +# X succeeds while we get load and store access fault +PMP_TOR_priority_x_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8C) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rw_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets RW permission -- TOR region selected +# R,W succeeds while we get fetch access fault +PMP_TOR_priority_rw_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8B) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_TOR_rx_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R X permission -- TOR region selected +# R, X succeeds while we get store access fault +PMP_TOR_priority_rx_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, TOR Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x8D) and ${TOR_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_r_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R permission -- NA4 region selected +# R succeeds while we get store and fetch access fault +PMP_NA4_priority_r_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_R_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x91) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rw_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets RW permission -- NA4 region selected +# R,W succeeds while we get fetch access fault +PMP_NA4_priority_rw_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit not set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RW_SET}": 0 + val_comb: + #Check for execute fault + mode == 'M' and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_FETCH_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x93) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_x_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets X permission -- NA4 region selected +# X succeeds while we get load and store access fault +PMP_NA4_priority_x_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit is set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_X_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check for load fault on lb, lh, lw, ld instruction + mnemonic == {'lb', 'lh', 'lw', 'ld'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_LOAD_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x94) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 + +# This coverpoint checks the coverage for the PMP_NA4_rx_priority_level_2.S +# This is a priority test. +# pmpcfg3[31:24] --> low priority entry gets RWX permission -- TOR region selected +# pmpcfg0[31:24] --> high priority entry gets permission -- TOR region selected +# pmpcfg0[15:8] --> highest priority entry gets R X permission -- NA4 region selected +# R,X succeeds while we get store access fault +PMP_NA4_priority_rx_level_2: + config: + - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; + mnemonics: + "{csrrs, csrrw, ld, sd, lw, sw, lb, sb, lh, sh}" : 0 + csr_comb: + # Low priority entry -- Check Lock bit is set, R bit is set, W bit is set, X bit is set, TOR Mode is set + "(pmpcfg2 >> 56) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_ONLY_RWX_SET}": 0 + # High priority entry -- Check Lock bit is set, R bit not set, W bit not set, X bit not set, TOR Mode is set + "(pmpcfg0 >> 24) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_TOR_MODE}+${PMPCFG_BIT_NOT_SET}": 0 + # Higest priority entry -- Check Lock bit is set, R bit is set, W bit not set, X bit is set, NA4 Mode is set + "(pmpcfg0 >> 8) & ${PMPCFG_ALL_BIT} == ${PMPCFG_L_BIT}+${PMPCFG_NA4_MODE}+${PMPCFG_ONLY_RX_SET}": 0 + val_comb: + #Check for store fault on sb , sh, sw, sd instruction + mnemonic == {'sb', 'sh', 'sw', 'sd'} and mode_change == {'M to M', 'U to M', 'S to M'} and (mcause == ${CAUSE_STORE_ACCESS}): 0 + #Check the napot region is accessed at least once + '(mnemonic == {"ld", "lw", "lh", "lb", "sd", "sw", "sh", "sb"}) and ((pmpcfg0 >> 8) & 0x9F == 0x95) and ${NA4_PRIORITY_2_REGION_MATCH}': 0 From d689026f91eaa066be86b7e10b5787614d045ab0 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 22 Nov 2024 10:17:51 +0500 Subject: [PATCH 15/19] Covergroup for MPRV test added --- coverage/sv32/rv32_vm_sv32.cgf | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf index c76de241e..d5f3c6d61 100644 --- a/coverage/sv32/rv32_vm_sv32.cgf +++ b/coverage/sv32/rv32_vm_sv32.cgf @@ -118,6 +118,26 @@ misaligned_superpage: 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 +# If MVPV bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault +MPRV_bit: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jalr}": 0 + op_comb: + 'mode == "M" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #check mstatus has: case1: MPP& U in MPP and case2: MPP& S in MPP + mstatus == {0x00020000, 0x00020800}: 0 + val_comb: + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw0cont) == 1': 0 + #Fault Checks + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + 'mode == "M" and (mstatus == {0x00020000, 0x00020800}) and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"ADURWXV", "ADuRWXV"}{[$1]}, dptw0cont) == 1 and len_dptw == 2': 0 + + # If MXR bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault MXR_bit: config: @@ -195,7 +215,7 @@ U_bit_sum_set_in_SMode: 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 -#If SUM bit is set, then User mode pages can be accessed in the Supervisor mode. +#If SUM bit is NOT set, then User mode pages can NOT be accessed in the Supervisor mode, get a fault. U_bit_no_sum_set_in_SMode: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; @@ -235,6 +255,7 @@ U_bit_set_in_UMode: 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 +#If U bit is NOT set in U mode, then we will get load, store and fetch page faults. U_bit_unset_in_UMode: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; @@ -252,6 +273,7 @@ U_bit_unset_in_UMode: 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 +#If U bit is NOT set in S mode, then page should be accessed successfully. U_bit_unset_in_SMode: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; From 07dcfa6ad472917ae756cbb232e3642c956cdd7b Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Fri, 22 Nov 2024 10:18:35 +0500 Subject: [PATCH 16/19] MPRV test for S and U mode added --- .../rv32i_m/vm_sv32/src/vm_mprv_S_mode.S | 295 ++++++++++++++++++ .../rv32i_m/vm_sv32/src/vm_mprv_U_mode.S | 293 +++++++++++++++++ 2 files changed, 588 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S new file mode 100644 index 000000000..5b5c6302e --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_S_mode.S @@ -0,0 +1,295 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test in M Mode (with S bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + LI (s7, MSTATUS_MPRV) + csrs mstatus,s7 + LI (s7, 0x1800) //clear previous mode + csrc mstatus,s7 + LI (s7, 0x800) //Smode + csrs mstatus,s7 + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S new file mode 100644 index 000000000..6e124b7eb --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_mode.S @@ -0,0 +1,293 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test in M Mode (with U bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: if VA passed then Load, store successful and (PA)fetch without translation successful + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + LI (s7, MSTATUS_MPRV) + csrs mstatus,s7 + LI (s7, 0x1800) //Set to U Mode + csrc mstatus,s7 + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From d2b365a6b131626964aaf19c9a3436d1a1726df3 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Tue, 3 Dec 2024 03:15:19 +0500 Subject: [PATCH 17/19] tvm, satp, rsw tests added --- coverage/sv32/rv32_vm_sv32.cgf | 53 +++- .../rv32i_m/vm_sv32/src/mstatus_tvm_test.S | 130 +++++++++ .../rv32i_m/vm_sv32/src/satp_access_tests.S | 194 +++++++++++++ .../vm_sv32/src/vm_reserved_rsw_pte_S_mode.S | 273 ++++++++++++++++++ .../vm_sv32/src/vm_reserved_rsw_pte_U_mode.S | 273 ++++++++++++++++++ ..._S_mode.S => vm_reserved_rwx_pte_S_mode.S} | 2 +- ..._U_mode.S => vm_reserved_rwx_pte_U_mode.S} | 2 +- 7 files changed, 923 insertions(+), 4 deletions(-) create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S rename riscv-test-suite/rv32i_m/vm_sv32/src/{vm_reserved_pte_S_mode.S => vm_reserved_rwx_pte_S_mode.S} (99%) rename riscv-test-suite/rv32i_m/vm_sv32/src/{vm_reserved_pte_U_mode.S => vm_reserved_rwx_pte_U_mode.S} (99%) diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf index d5f3c6d61..54669c6cf 100644 --- a/coverage/sv32/rv32_vm_sv32.cgf +++ b/coverage/sv32/rv32_vm_sv32.cgf @@ -175,7 +175,7 @@ nonleaf_pte_level0: 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 #If reserved PTE permissions are chosen, then get a load, store and fetch page fault -reserved_pte_perm: +reserved_rwx_pte_perm: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; mnemonics: @@ -291,4 +291,53 @@ U_bit_unset_in_SMode: 'mode == "S" and mnemonic == {"sw", "lw"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("urwX", dptw0cont) == 1 and mcause == {15, 13}{[$1]}': 0 'mode == "S" and mnemonic == "sw" and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop({"uRwX", "uRwx"}, dptw0cont) == 1 and mcause == 15': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 - 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 \ No newline at end of file + 'mode == "M" and (${va_data_sv32} + ${LEVEL_0_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 + +#Access satp register in all three M, S, U modes and expect illegal instruction expection in U Mode. +satp_access_all_modes: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{csrrc, csrrs, csrrw}": 0 + csr_comb: + #Make sure we have some value in case of satp access in M, S modes + 'mode == "M" and mnemonic == "csrrw" and satp != 0': 0 + 'mode == "M" and mnemonic == "csrrs" and satp != 0': 0 + 'mode == "M" and mnemonic == "csrrc" and satp != 0': 0 + 'mode == "S" and mnemonic == "csrrw" and satp != 0': 0 + 'mode == "S" and mnemonic == "csrrs" and satp != 0': 0 + 'mode == "S" and mnemonic == "csrrc" and satp != 0': 0 + #Make sure we have illegal instruction fault for satp access in U mode + 'mode == "U" and mnemonic == "csrrw" and satp != 0 and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + 'mode == "U" and mnemonic == "csrrs" and satp != 0 and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + 'mode == "U" and mnemonic == "csrrc" and satp != 0 and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + #check all ones + 'mode == "M" and mnemonic == "csrrw" and satp == 0x3FFFFF': 0 + #check walking ones on the PPN Width + 'mode == "M" and mnemonic == "csrrw" and satp == 1 << {0 ... 21}': 0 + +#When mstatus TVM bit is set, accessing satp and sfence.vma in S-Mode should raise illegal instruction fault. +mstatus_tvm: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + csrrw: 0 + csr_comb: + #Make sure we have some value in case of satp access in M mode + 'mode == "M" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and satp != 0': 0 + #Make sure we have illegal instruction fault for satp access in S mode + 'mode == "S" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}': 0 + +#If reserved PTE permissions bits (RSW) are set, then the Page table walk should give no RSW set in return +reserved_rsw_pte_perm: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrw, lw}": 0 + op_comb: + 'mode == {"S", "U"} and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + val_comb: + 'mode == {"S", "U"} and get_pte_prop("RWXAD", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXAD", dptw0cont) == 1': 0 \ No newline at end of file diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S b/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S new file mode 100644 index 000000000..350279292 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/mstatus_tvm_test.S @@ -0,0 +1,130 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// This test verifies the functionality of mstatus.TVM bit with the satp and sfence.vma +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. satp and sfence.vma accessed in M Mode with mstatus.tvm bit set -> Successful +// 2. satp and sfence.vma accessed in S Mode with mstatus.tvm bit set -> illegal instruction exception +// +// Total Expected Faults: 2 +// ---------------------------------------------------------------------------------------------------------------------- + +//TODO: instead of using two different tests, use a single test for hart/software update. + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", mstatus_tvm) + +RVTEST_SIGBASE( x13,signature_x13_1) + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + + #set the mstatus with the TVM bit + LI (t4, MSTATUS_TVM) + csrw mstatus, t4 + csrr t3, mstatus + RVTEST_SIGUPD(x13,t3) + +// ------------------------------------------------------------------------------------------------------------ +// satp access in M Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + li t0, 1 //initial value for t0 = 1 + #successful access + csrw satp, t0 // write satp with some value + csrr t3, satp + RVTEST_SIGUPD(x13,t3) + + #successful access + sfence.vma + nop + nop + +// ------------------------------------------------------------------------------------------------------------ +// satp access in S Mode +// ------------------------------------------------------------------------------------------------------------ + + RVTEST_GOTO_LOWER_MODE Smode + + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + nop + nop + + sfence.vma + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 64*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S new file mode 100644 index 000000000..80028713e --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S @@ -0,0 +1,194 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// This test verifies the functionality of satp register in M, S and U Mode using csrrw, csrrs, csrrc. +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. satp register accessed in M, S Mode -> Successful +// 2. satp register accessed in U Mode -> Illegal Instruction exception +// 3. Walking ones on the PPN of satp -> Successful +// Total Expected Faults: 3 +// ---------------------------------------------------------------------------------------------------------------------- + +//TODO: instead of using two different tests, use a single test for hart/software update. + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", satp_access_all_modes) + +RVTEST_SIGBASE( x13,signature_x13_1) + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +// ------------------------------------------------------------------------------------------------------------ +// satp access in M Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrs satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrc satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + +// ------------------------------------------------------------------------------------------------------------ +// satp access in S Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + + //Go to S mode + RVTEST_GOTO_LOWER_MODE Smode + + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrs satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + csrc satp, t0 // write satp with some value + //read back the value from the satp and store in the signature to make sure they match ! + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + slli t0, t0, 1 //walking ones to have different values in each satp store + + RVTEST_GOTO_MMODE // Switching back to M mode + +// ------------------------------------------------------------------------------------------------------------ +// satp access in U Mode using csrrw, csrrc, csrrs +// ------------------------------------------------------------------------------------------------------------ + + RVTEST_GOTO_LOWER_MODE Umode + + li t0, 1 //initial value for t0 = 1 + csrw satp, t0 // write satp with some value + nop + nop + + csrs satp, t0 // write satp with some value + nop + nop + + csrc satp, t0 // write satp with some value + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +// ------------------------------------------------------------------------------------------------------------ +// PPN Write all zeros, ones and walking ones to the PPN bits of satp register csrw instruction +// ------------------------------------------------------------------------------------------------------------ + csrw satp, zero // All ZEROES + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + + li t0, 0x3FFFFF //All ONES in the PPN + csrw satp, t0 + csrr t1, satp + RVTEST_SIGUPD(x13,t1) + +RVTEST_SIGBASE( x14,signature_x14_1) + +//Walking one test for PPN bits of satp register + li t2, 0 // shift left value + li t3, 22 // max value of shift left (PPN Width) +walking_ones_satp: + li t0, 1 //initial value for t0 = 1 + sll t0, t0, t2 + addi t2, t2, 1 + csrw satp, t0 + csrr t1, satp + RVTEST_SIGUPD(x14,t1) + bne t3, t2, walking_ones_satp + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 64*(XLEN/32),4,0xcafebeef + +// test signatures initialization +signature_x14_1: + .fill 256*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S new file mode 100644 index 000000000..a3e1010c0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S @@ -0,0 +1,273 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. RSW Permissions is Set for the page at level 1 (11): +// Then, in U-Mode, the page is accessed --> required: No affect on these bits, successful page table walk +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to S mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Smode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S new file mode 100644 index 000000000..1290dd2e7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S @@ -0,0 +1,273 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// 1. RSW Permissions is Set for the page at level 1 (11): +// Then, in U-Mode, the page is accessed --> required: No affect on these bits, successful page table walk +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rsw_pte_perm) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switching to U mode + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4KB PAGE Region 1 under test at level 0 -- WX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: Test in U-Mode | RSW bit set | expected = successful page access with no affect on these bits + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V | PTE_SOFT), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Umode, va_data, LEVEL0 + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S similarity index 99% rename from riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S index f2c9dc3ca..f64b55a4c 100644 --- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S @@ -38,7 +38,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S similarity index 99% rename from riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S rename to riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S index c46db6aa9..96ac761d3 100644 --- a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S @@ -38,7 +38,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_pte_perm) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS",reserved_rwx_pte_perm) RVTEST_SIGBASE( x13,signature_x13_1) # --------------------------------------------------------------------------------------------- From 478a3b4608bbe999af313fc9d3e8ae4725232994 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Wed, 4 Dec 2024 11:13:43 +0500 Subject: [PATCH 18/19] Updated the test to dump the correct value for walking ones --- riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S index 80028713e..ab346a9ff 100644 --- a/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/satp_access_tests.S @@ -149,6 +149,7 @@ walking_ones_satp: csrw satp, t0 csrr t1, satp RVTEST_SIGUPD(x14,t1) + addi x14, x14, REGWIDTH bne t3, t2, walking_ones_satp #endif From bb63582da63d3b7974a5fd62b2b475d9438e3608 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Thu, 5 Dec 2024 01:55:04 +0500 Subject: [PATCH 19/19] tests and covergroups for the combination of mprv and sum bit added --- coverage/sv32/rv32_vm_sv32.cgf | 25 +- riscv-test-suite/env/arch_test.h | 10 + .../src/vm_mprv_U_set_sum_set_S_mode.S | 309 ++++++++++++++++++ .../src/vm_mprv_U_set_sum_unset_S_mode.S | 301 +++++++++++++++++ 4 files changed, 643 insertions(+), 2 deletions(-) create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S create mode 100644 riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf index 54669c6cf..f75c8f069 100644 --- a/coverage/sv32/rv32_vm_sv32.cgf +++ b/coverage/sv32/rv32_vm_sv32.cgf @@ -118,7 +118,7 @@ misaligned_superpage: 'mode == {"S", "U"} and mnemonic == {"sw", "lw"} and get_pte_prop("ADRWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {15, 13}{[$2]}': 0 'mode == "M" and (${va_data_sv32} + ${LEVEL_1_JUMP_SIZE}) == mtval and mcause == ${CAUSE_FETCH_PAGE_FAULT}': 0 -# If MVPV bit is set, then make the exec. readable and just give a store page fault else give both load and store page fault +# If MVPV bit is set, then do page table walk in machine mode for loads and stores. MPRV_bit: config: - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; @@ -340,4 +340,25 @@ reserved_rsw_pte_perm: '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 val_comb: 'mode == {"S", "U"} and get_pte_prop("RWXAD", dptw1cont) == 1 and dptw0cont == None': 0 - 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXAD", dptw0cont) == 1': 0 \ No newline at end of file + 'mode == {"S", "U"} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("RWXAD", dptw0cont) == 1': 0 + +# If MVPV bit is set, then do page table walk in machine mode for loads and stores. +MPRV_SUM_bit: + config: + - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; + mnemonics: + "{sw, csrrc, csrrs, csrrw, lw, jal, jalr}": 0 + op_comb: + 'mode == "M" and (satp >> 31) == ${SATP_MODE_SV32}': 0 + csr_comb: + '((satp) & 0x003FFFFF) == get_addr("rvtest_Sroot_pg_tbl") >> 12': 0 + #check mstatus has: Case 1: MPP=S, SUM=1, MPRV=1 Case 2: MPP=S, SUM=0, MPRV=1 + mstatus == {0x00060800, 0x00020800}: 0 + val_comb: + 'mode == "M" and mnemonic == {"lw", "sw"} and old_csr_val("mstatus") == {0x00060800, 0x00020800} and get_pte_prop("ADURWXV", dptw1cont) == 1 and dptw0cont == None': 0 + 'mode == "M" and mnemonic == {"lw", "sw"} and old_csr_val("mstatus") == {0x00060800, 0x00020800} and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV", dptw0cont) == 1': 0 + #Fault Checks + 'mode == "M" and old_csr_val("mstatus") == 0x00060800 and get_pte_prop("ADURWXV", dptw1cont) == 1 and dptw0cont == None and len_dptw == 1': 0 + 'mode == "M" and old_csr_val("mstatus") == 0x00060800 and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV", dptw0cont) == 1 and len_dptw == 2': 0 + 'mode == "M" and old_csr_val("mstatus") == 0x00020800 and get_pte_prop("ADURWXV", dptw1cont) == 1 and dptw0cont == None and mcause == {${CAUSE_LOAD_PAGE_FAULT}, ${CAUSE_STORE_PAGE_FAULT}}': 0 + 'mode == "M" and old_csr_val("mstatus") == 0x00020800 and get_pte_prop("rwx", dptw1cont) == 1 and get_pte_prop("ADURWXV", dptw0cont) == 1 and mcause == {${CAUSE_LOAD_PAGE_FAULT}, ${CAUSE_STORE_PAGE_FAULT}}': 0 \ No newline at end of file diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index 80a150505..32fdf8711 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -1374,6 +1374,11 @@ vmem_adj_\__MODE__\()epc: add T4, T4, sp /* calc address of correct sv_area */ csrr T2, CSR_XEPC /* T4 now pts to trapping sv_area mode */ +#ifdef SKIP_MEPC + addi T3, T3, 0 + j adj_\__MODE__\()epc +#endif + LREG T3, vmem_bgn_off(T4) // see if epc is in the vmem area LREG T6, vmem_seg_siz(T4) add T6, T6, T3 // construct vmem seg end @@ -1421,6 +1426,11 @@ adj_\__MODE__\()epc_rtn: // adj mepc so there is at least 4B of p csrr T2, CSR_XTVAL +#ifdef SKIP_MTVAL + addi T3, T3, 0 + j adj_\__MODE__\()tval +#endif + chk_\__MODE__\()tval: andi T5, T5, EXCPT_CAUSE_MSK // ensures shift amt will be within range LI( T3, SET_REL_TVAL_MSK) // now check if code or data (or sig) region adjustment diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S new file mode 100644 index 000000000..dbb58d87d --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S @@ -0,0 +1,309 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test with the combination of SUM set in mstatus in M Mode (with U bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus and SUM bit is not SET: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#define SKIP_MTVAL +#define SKIP_MEPC + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sfence.vma + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + #Set the required mstatus values for this test (in case of a trap) + SET_REQ_MSTATUS_VAL + + sfence.vma + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + SET_REQ_MSTATUS_VAL + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +.macro SET_REQ_MSTATUS_VAL + LI (s7, MSTATUS_MPRV) + csrs mstatus,s7 + LI (s7, MSTATUS_SUM) //SET the MSTATUS sum bit + csrs mstatus,s7 + LI (s7, 0x1800) //clear previous mode + csrc mstatus,s7 + LI (s7, 0x800) //Smode + csrs mstatus,s7 +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l1, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + //return page PTE + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_return_page_l0, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_R | PTE_W | PTE_X | PTE_V), va_return_page_l0, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S new file mode 100644 index 000000000..127f07714 --- /dev/null +++ b/riscv-test-suite/rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S @@ -0,0 +1,301 @@ +// ---------------------------------------------------------------------------------------------------------------------- +// This test is part of the test plan for the SV-32-based Virtual Memory System, available at: +// https://docs.google.com/spreadsheets/d/1Y8fEu2PnT69w-h8hZc2QQSNKi7DBI0pbXHu2IB8soaQ/edit#gid=0 +// Developed by: Muhammad Hammad Bashir, Allen Baum, Umer Shahid +// ---------------------------------------------------------------------------------------------------------------------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ---------------------------------------------------------------------------------------------------------------------- +// Test Explanation: +// RISC-V Privileged Architecture ISA Manual -- Section 10.3 +// Note: This test is based on RISC-V Privileged ISA version 1.12, which does not include SVADE and SVADU support. +// Future updates will align with ISA version 1.13. +// +// Test cases are as follows: +// ---------------------------------------------------------------------------------------------------------------------- +// ------------------------------------------MPRV test with the combination of SUM unset in mstatus in M Mode (with U bit perms)--------------------------------------------------- +// 1. PTE has RWX Permissions at Level 1(Read, write, execute page) and MPRV bit set in mstatus and SUM bit is not SET: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. +// 2. PTE has RWX Permissions at Level 0(Read, write, execute page) and MPRV bit set in mstatus: +// Then, in M-Mode, the page is accessed --> required: load, store page fault, instruction accesses should be successful. + +// Total Expected Faults :: 0 +//------------------------------------------------------------------------------------------------------------------- + +#define SKIP_MTVAL +#define SKIP_MEPC + +#include "model_test.h" + +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(1,"//check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac SV32_MACROS", MPRV_SUM_bit) + +RVTEST_SIGBASE( x13,signature_x13_1) +# --------------------------------------------------------------------------------------------- +// Test the RWX permissions +.macro VERIFICATION_RWX ADDRESS, level, VM_MODE + LA(a5, \ADDRESS) // Fetch the address to be checked + addi a2, a2, 16 // 16 stored in a2 for starting point + + // Check store on the address. + sfence.vma + sw a2, 20(a5) + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + + #Set the required mstatus values for this test + SET_REQ_MSTATUS_VAL + + sfence.vma + nop + lw a4, 20(a5) // Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY) + SREG a4, 0(s11) + nop + addi s11, s11, REGWIDTH + + //check if level is equal to zero, if it is then jump to the end of the 4KB to check the permissions + //else jump to the end of the 4MB page to check the permissions + // Check if level is equal to zero (4KB page) + addi a2, a2, 16 // update the counter for execute + LI( t1, \level) + beqz t1, 1f // Forward reference to avoid label redefinition + + // 4MB - 4 = 4,194,300 bytes + // Access the last four bytes which contain the jr instruction + LI (t0, (0x400000 - 4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l1) // Fetch the address to be checked + .endif + srli a5, a5, 22 + slli a5, a5, 22 //Clear the lower 21 bits -- offset bits(10) + level 0 bits(12) + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + j 2f + +1: // 4KB - 4 = 4,092 bytes + LI (t0, (0x1000-4)) + .if \VM_MODE == Mmode + LA(a5, rvtest_data_1_l0) // Fetch the address to be checked + .endif + srli a5, a5, 12 + slli a5, a5, 12 + add t0, a5, t0 + jalr ra, t0, 0 + SREG a2, 0(s11) + nop + addi s11, s11, REGWIDTH + +2: // end_macro + // execution test sig update + nop +.endm + +.macro TEST_CASES_RUNNER LOWER_MODE, VA, level + .if \LOWER_MODE == Mmode + SET_REQ_MSTATUS_VAL + .else + RVTEST_GOTO_LOWER_MODE \LOWER_MODE // Switch to the specified lower mode + .endif + + .align 2 + + //JUMP TO LOAD, STORE, EXECUTE CHECK MACRO (SEE ON TOP) + VERIFICATION_RWX \VA, \level, \LOWER_MODE + nop + nop + + RVTEST_GOTO_MMODE // Switching back to M mode + +.endm + +.macro SET_REQ_MSTATUS_VAL + LI (s7, MSTATUS_MPRV) + csrw mstatus,s7 //using csrrw to remove anyother values written on the mstatus register. + LI (s7, MSTATUS_SUM) //Clear the MSTATUS sum bit + csrc mstatus,s7 + LI (s7, 0x1800) //clear previous mode + csrc mstatus,s7 + LI (s7, 0x800) //Smode + csrs mstatus,s7 +.endm + +main: +#ifdef rvtest_mtrap_routine // Verification of existance of rvtest_mtrap_routine + LI a4, 0xceed + RVTEST_SIGUPD(x13,a4) +#endif +#ifdef rvtest_strap_routine // Verification of existance of rvtest_strap_routine + LI a4, 0xbeed + RVTEST_SIGUPD(x13,a4) +#endif + + ALL_MEM_PMP // set the PMP permissions for the whole memory + csrw satp, zero // write satp with all zeros (bare mode) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Virtual addresses definition section for the code, data, sig, vmem, test sections +//--------------------------------------------------------------------------------------------------------------------------------- + + // test section VAs + .set va_data, 0x91400000 // virtual address of rvtest_data_1_l1 and rvtest_data_1_l0 + .set va_return_page_l1, 0x91800000 // virtual address of return_page for the rvtest_data_1_l1 + .set va_return_page_l0, 0x91401000 // virtual address of return_page for the rvtest_data_1_l0 + + // code, data, sig, vmem section VAs + .set va_rvtest_code_begin, 0x9000036c // virtual address of rvtest_code_begin + .set va_rvtest_data_begin, 0x910003fc // virtual address of rvtest_data_begin (for save area) + .set va_rvtest_sig_begin, 0x93014510 // virtual address of signature_x13_1 + .set va_rvtest_vmem_begin, 0x940003F0 // virtual address of rvtest_vmem_begin + +// PTE setup for Code Region + PTE_SETUP_RV32_New(rvtest_code_begin, (PTE_D | PTE_A | PTE_U | PTE_X |PTE_R | PTE_V), va_rvtest_code_begin, LEVEL1) + sfence.vma +// PTE setup for Data Region + PTE_SETUP_RV32_New(rvtest_data_begin, (PTE_D | PTE_U | PTE_A | PTE_X | PTE_W | PTE_R | PTE_V), va_rvtest_data_begin, LEVEL1) + sfence.vma +// PTE setup for Signature Region + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_rvtest_sig_begin, LEVEL1) + PTE_SETUP_RV32_New(rvtest_sig_begin, (PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_V), va_rvtest_sig_begin, LEVEL0) + sfence.vma +// register setup for the signature save in virtualization mode + LI (t0, va_rvtest_sig_begin) + LA (t1, rvtest_sig_begin) + sub t0, t0, t1 // (VA-PA) Note: VA > PA + add s11, x13, t0 // Translation of Signature reg + +//--------------------------------------------------------------------------------------------------------------------------------- +// Save area logic +//--------------------------------------------------------------------------------------------------------------------------------- + LI (t0, va_rvtest_data_begin) + LA (t1, rvtest_data_begin) + sub t0, t0, t1 + addi t3, t0, sv_area_sz + csrr sp, mscratch + add t1,sp,t3 + csrw sscratch, t1 + csrr sp, mscratch + + //save area setup for code region + SAVE_AREA_SETUP(va_rvtest_code_begin, rvtest_code_begin, code) + //save area setup for data region + SAVE_AREA_SETUP(va_rvtest_data_begin, rvtest_data_begin, data) + //save area setup for sig region + SAVE_AREA_SETUP(va_rvtest_sig_begin, rvtest_sig_begin, sig) + //save area setup for vmem region + SAVE_AREA_SETUP(va_rvtest_vmem_begin, rvtest_data_begin, vmem) + +//--------------------------------------------------------------------------------------------------------------------------------- +// Test Cases Start from here +//--------------------------------------------------------------------------------------------------------------------------------- + + SATP_SETUP_SV32 // set the SATP for virtualization + sfence.vma // flush the TLB + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 1 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 1 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 1: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_data_1_l1, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R| PTE_V), va_data, LEVEL1) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL1 + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- +// TESTS AT LEVEL 0 +//--------------------------------------------------------------------------------------------------------------------------------- +// 4MB PAGE Region 1 under test at level 0 -- RWX permissions given to the region +//--------------------------------------------------------------------------------------------------------------------------------- + // Test case 2: MPRV bit set | Test in M-Mode | RWX bit set | expected = No Fault + PTE_SETUP_RV32_New(rvtest_slvl1_pg_tbl, (PTE_V), va_data, LEVEL1) + PTE_SETUP_RV32_New(rvtest_data_1_l0, (PTE_D | PTE_A | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V), va_data, LEVEL0) + sfence.vma + + TEST_CASES_RUNNER Mmode, va_data, LEVEL0 + + + +#endif +//--------------------------------------------------------------------------------------------------------------------------------- +RVTEST_CODE_END +RVMODEL_HALT +RVTEST_DATA_BEGIN +.align 22 + +//--------------------------------------------------------------------------------------------------------------------------------- +// PHYSICAL ADDRESS REGIONS FOR TESTING +//--------------------------------------------------------------------------------------------------------------------------------- +//Physical Address region under testing for LEVEL 1 -- Aligned by 22 +rvtest_data_1_l1: + nop //nops are added so if there is a trap + addi ra, ra, REGWIDTH + jr ra // return back if the access fault + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 20) - 7) // (2^22 - 7) nops + nop + .endr + jr ra // return back if successful access + +//Physical Address region under testing for LEVEL 0 -- Aligned by 10 +rvtest_data_1_l0: + nop // trap return back skip + addi ra, ra, REGWIDTH + jr ra //jump back for the trap on level 1 + nop + .word 0xbeefcaf1 // Random word + .word 0xbeefcaf2 // Random word + .rept ((1 << 10) - 7) // (2^12 - 7) nops + nop + .endr + jr ra + +//--------------------------------------------------------------------------------------------------------------------------------- +//--------------------------------------------------------------------------------------------------------------------------------- + +#ifdef rvtest_strap_routine +.align 12 //complete the 4KB permission memory range +rvtest_slvl1_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,1,PTE_V | PTE_A | PTE_D | PTE_U | PTE_G) +#endif + +RVTEST_DATA_END +.align 12 +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +// test signatures initialization +signature_x13_1: + .fill 128*(XLEN/32),4,0xcafebeef + +// trap signatures initialization +#ifdef rvtest_mtrap_routine +mtrap_sigptr: + .fill 128*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END