From 624448edbf9a35b7e9e12162ec9efd06b768514b Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 15:28:24 -0700 Subject: [PATCH 01/14] minor text improvements to the introduction --- intro.adoc | 20 +++---- riscv-smtdeleg-sstcfg.adoc | 117 ------------------------------------- 2 files changed, 10 insertions(+), 127 deletions(-) delete mode 100644 riscv-smtdeleg-sstcfg.adoc diff --git a/intro.adoc b/intro.adoc index fb28473..56d4511 100644 --- a/intro.adoc +++ b/intro.adoc @@ -1,26 +1,26 @@ [[intro]] == Introduction -Debugging and tracing are essential for developers to identify and rectify software and hardware issues, optimize performance, and ensure robust system functionality. The debugging and tracing extensions in RISC-V ecosystem play a pivotal role in enabling these capabilities, allowing developers to monitor and control the execution of programs during the development, testing and production phases. However, the current RISC-V Debug and trace specification grants the external debugger highest privilege in the system, regardless of the privilege level at which the target system is running. It leads to privilege escalation issues when multiple actors are present. +Debugging and tracing are essential for developers to identify and rectify software and hardware issues, optimize performance, and ensure robust system functionality. The debugging and tracing extensions in the RISC-V ecosystem play a pivotal role in enabling these capabilities, allowing developers to monitor and control the execution of programs during the development, testing and production phases. However, the current RISC-V Debug specification grants the external debugger the highest privilege in the system, regardless of the privilege level at which the target system is running. It leads to privilege escalation issues when multiple actors are present. -This specification defines non-ISA extension <> and ISA extension <> to address the above security issues in the current _The RISC-V Debug Specification_ cite:[dbgspec] and trace specifications cite:[etrace] cite:[ntrace]. +This specification defines <> and <> to address the above security issues in the current _The RISC-V Debug Specification_ cite:[dbgspec] and trace specifications cite:[etrace] cite:[ntrace]. -A summary of the changes introduced by _The RISC-V External Debug Security Specification_ follows.: +A summary of the changes introduced by _The RISC-V External Debug Security Specification_ follows. - *Per-Hart Debug Control:* Introduce per-hart states to control whether external debug is allowed in M-mode and/or supervisor domains cite:[smmtt]. - *Per-Hart Trace Control:* Introduce per-hart states to control whether tracing is allowed in M-mode and/or supervisor domains. - *Non-secure debug:* Add a non-secure debug state to relax security constraints. - - *Debug Mode entry:* External debugger can only halt the hart and enter debug mode when debug is allowed in current privilege mode; all operations are executed with <> instead of M-mode privilege. - - *Memory Access:* Memory access from a hart’s point of view using the Program Buffer or an Abstract Command must be checked by the hart's memory protection mechanisms as if the hart is running at <>; memory access from the Debug Module using System Bus Access must be checked by a system memory protection mechanism, such as IOPMP or WorldGuard. - - *Register Access:* Register access using the Program Buffer or an Abstract Command works as if the hart is running in <> instead of M-mode privilege. The debug CSRs (`dcsr` and `dpc` ) are shadowed in supervisor domains while Smtdeleg/Sstcfg extensions expose the trigger CSRs to supervisor domains through indirect CSR access. - - *Triggers:* Triggers (with action=1) can only fire or match when external debug is allowed in current privilege. + - *Debug Mode entry:* An external debugger can only halt the hart and enter debug mode when debug is allowed in current privilege mode. + - *Memory Access:* Memory access from a hart’s point of view, using the Program Buffer or an Abstract Command, must be checked by the hart's memory protection mechanisms as if the hart is running at <>; memory access from the Debug Module using System Bus Access must be checked by a system memory protection mechanism, such as IOPMP or WorldGuard. + - *Register Access:* Register access using the Program Buffer or an Abstract Command works as if the hart is running at <> instead of M-mode privilege level. The debug CSRs (`dcsr` and `dpc` ) are shadowed in supervisor domains while Smtdeleg/Sstcfg extensions expose the trigger CSRs to supervisor domains. + - *Triggers:* Triggers (with action=1) can only fire or match when external debug is allowed in the current privilege mode. === Terminology [cols="2*"] [cols="20%,80%"] |===================================================================================================================================================== -| Abstract command | A high-level command in Debug Module used to interact with and control harts +| Abstract command | A high-level Debug Module operation used to interact with and control harts | Debug Access Privilege | The privilege with which an Abstract Command or instructions in the Program Buffer access hardware resources | Debug Mode | An additional privilege mode to support off-chip debugging | Hart | A RISC-V hardware thread @@ -28,7 +28,7 @@ A summary of the changes introduced by _The RISC-V External Debug Security Speci | M-mode | The highest privileged mode in the RISC-V privilege model | PMA | Physical Memory Attributes | PMP | Physical Memory Protection unit -| Program buffer | A buffer in Debug Module to execute arbitrary instructions on a hart -| Supervisor domain | A isolated supervisor execution context defined in RISC-V Supervisor Domains Access Protection cite:[smmtt] +| Program buffer | A mechanism that allows the Debug Module to execute arbitrary instructions on a hart +| Supervisor domain | An isolated supervisor execution context defined in RISC-V Supervisor Domains Access Protection cite:[smmtt] | Trace encoder | A piece of hardware that takes in instruction execution information from a RISC-V hart and transforms it into trace packets |===================================================================================================================================================== diff --git a/riscv-smtdeleg-sstcfg.adoc b/riscv-smtdeleg-sstcfg.adoc deleted file mode 100644 index fd631d7..0000000 --- a/riscv-smtdeleg-sstcfg.adoc +++ /dev/null @@ -1,117 +0,0 @@ -[[intro]] -== Introduction - -Sdtrig triggers allow both self-hosted and external debuggers to debug target software by transferring control to the debugger at points of interest. However, Sdtrig CSRs are accessible only with M-mode privilege. As a result, a debugger must have M-mode privilege, or be able to invoke M-mode, in order to access them. - -For a self-hosted debugger with less than M-mode privilege, this requires an SBI (Supervisor Binary Interface). This results in traps on all trigger accesses, which can add latency to critical context switch flows. - -For an external debugger, if Sdsec is implemented and the hart is configured such that Debug Mode has less than M-mode privilege, the debugger is unable to access triggers. There is no SBI that can be called from Debug Mode. - -The Smtdeleg extension provides a means for Sdtrig triggers to be accessed from S-mode and VS-mode, using the indirect CSR interface (Sscsrind). It also defines a means to control S-mode and VS-mode access to triggers using the State Enable extensions (Smstateen/Ssstateen). Sstcfg comprises the supervisor components of Smtdeleg. - -[[body]] -== CSRs - -=== Supervisor Trigger Select (`stselect`) - -`stselect` provides read/write access to `tselect` from S-mode and VS-mode. - -== Supervisor and Virtual Supervisor Trigger Access - -While `siselect` holds XXX, the `sireg*` registers provide supervisor read/write access to register state associated with the trigger selected in `tselect`, the same state accessed by M-mode CSRs `tdata*` and `tinfo`. The register mapping is shown below. - -.Indirect Trigger Register Mappings When `siselect` = XXX -[width="70%",options="header"] -|=== -| Indirect CSR | State Accessed -| `sireg` | Same as `tdata1` -| `sireg2` | Same as `tdata2` -| `sireg3` | Same as `tdata3` -| `sireg4` | Same as `tinfo` -|=== - -[WARN] -==== -_There was much discussion of the best way to access counters in S-mode. This method requires 1 new CSR (`stselect`), along with 1 siselect index._ - -_Also proposed was to simply allocate a range of `siselect` values that serve to select the trigger, bypassing `tselect` when accessing trigger state through `sireg*`. This adds no new CSRs, but artificially limits the number of triggers accessible in S-mode. `tselect` supports up to 2^MXLEN^ triggers, while `siselect` would likely allocate only enough values to cover practical implementations (256?)._ - -_Other approaches considered:_ - -* _Define new `stdata[123]` and `stinfo` registers, which provide S-mode access to `tdata[123]` and `tinfo`. Avoids dependence on Sscsrind altogether, but costs 4 more CSR addresses._ - -* _Access `tselect` via `sireg5` instead of through a new `stselect` CSR (access to `tdata*` and `tinfo` is the same as spec'd above). While saving a CSR, this approach would require `sireg5` to continue to access `tselect` while the other `sireg*` registers shift the state they acccess based on the `tselect` value. This approach seems more awkward for implementation._ -==== - -Similarly, when `vsiselect` holds XXX, the `vsireg*` registers provide access to trigger register state in the same manner as described above for `sireg*`. - -=== Trigger State Access Modifications - -`sireg*` and `vsireg*` provide access to a subset of the fields in the native trigger registers, and in some cases fields are relocated. The field modifications that apply when trigger registers are accessed via `sireg*` or `vsireg*` are documented below. - -.Delegated Trigger CSR Field Modifications -[options="header", cols="30%,30%,40%"] -|=== -| Sdtrig Register | `sireg*` Field Modifications | `vsireg*` Field Modifications -| `mcontrol`, `mcontrol6`, `icount`, `etrigger`, `itrigger` - -(accessed by `tdata1`) | M is read-only 0 - -VS and VU are read-only 0 - -| M is read-only 0 - -S accesses `tdata1`.VS - -U accesses `tdata1`.VU - -VS and VU are read-only 0 -| `textra32`, `textra64` - -(accessed by `tdata3`) | none | MHVALUE and MHSELECT are read-only 0 -|=== - -[NOTE] -==== -_The bit positions for the M, S, U, VS, and VU fields referenced above vary based on the trigger type, specified by `tdata1`.TYPE. See details in the RISC-V Debug Specification, Chapter 5.7._ -==== - -[NOTE] -==== -_A hypervisor enabling trigger match in VS-mode or VU-mode must be done through `vsiselect`/`vsireg*`. This simplifies support for nested virtualization. A nested hypervisor (running in VS-mode) that wishes to configure triggers to match in a true guest will attempt to access `vsiselect`/`vsireg*`, which will naturally trap to HS-mode, thereby allowing the L0 hypervisor (running in HS-mode) to emulate the desired behavior._ -==== - -When `tdata1`.DMODE = 1 for the trigger with index _i_, the trigger is reserved for Debug Mode use. In that case, when `tselect` holds _i_ and the hart is not in Debug Mode, `sireg` and `sireg[234]` are read-only 0 while `siselect` holds XXX, and `vsireg` and `vsireg[234]` are read-only 0 while `vsiselect` holds XXX. - -== Supervisor and Virtual Supervisor Trigger State Access Control - -While the privilege mode is M or S and `siselect` holds XXX, illegal instruction exceptions are raised for attempts to access `sireg5` or `sireg6`. Similarly, while the privilege mode is M or S and `vsiselect` holds XXX, illegal instruction exceptions are raised for attempts to access `vsireg5`, or `vsireg6`. - -While the privilege mode is VS and `vsiselect` holds XXX, virtual instruction exceptions are raised for attempts to access `sireg5` (really `vsireg5`) or `sireg6` (really `vsireg6`). - -=== State Enable Access Control - -When Smstateen is implemented, the `mstateen0`.TR bit controls access to Sdtrig register state from privilege modes less privileged than M-mode. When `mstateen0`.TR=1, accesses to Sdtrig register state behave as described in <> above. When `mstateen0`.TR=0 and the privilege mode is less privileged than M-mode, attempts to access `stselect`, `sireg` or `sireg[234]` while `siselect` holds XXX, or `vsireg` or `vsireg[234]` while `vsiselect` holds XXX, raise an illegal-instruction exception. - -If the H extension is implemented and `mstateen0`.TR=1, the `hstateen0`.TR bit controls access to Sdtrig state when V=1. `hstateen0`.TR is read-only 0 when `mstateen0`.TR=0. - -When `mstateen0`.TR=1 and `hstateen0`.TR=1, VS-mode accesses to supervisor TR state behave as described in <> above. When `mstateen0`.TR=1 and `hstateen0`.TR=0, attempts from VS-mode to access `stselect`, or `sireg` (really `vsireg`) or `sireg[234]` (really `vsireg[234]`) while `vsiselect` holds XXX, raise a virtual-instruction exception. - -The TR bit is bit YYY in `mstateen0` and `hstateen0`. - -[NOTE] -[%unbreakable] -==== -_See the Sscsrind spec for how bit 60 in mstateen0 and hstateen0 can also restrict access to `sireg*`/`siselect` and `vsireg*`/`vsiselect` from privilege modes less privileged than M-mode._ -==== - -[WARN] -==== -_Utilizing Smstateen to control access to trigger state in S-mode and VS-mode results in an "all or none" delegation mechanism. It is believed that this is sufficient, that software is not accustomed to exposing only select triggers to less privileged modes on other architectures._ - -_If, in the future, there is a reason to support selective delegation, new `tdelegX` and `htdelegX` registers could be defined, such that each bit enables delegation of the associated trigger. However, this would artificially limit the number of triggers that could be delegated._ -==== - - - - From 789ac9d3fe3230d098ef296fde868d87f5ccea4e Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 15:29:13 -0700 Subject: [PATCH 02/14] minor text improvements to chapter 1 --- chapter1.adoc | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/chapter1.adoc b/chapter1.adoc index 9e06156..9bc5923 100755 --- a/chapter1.adoc +++ b/chapter1.adoc @@ -1,14 +1,9 @@ [[threatmodel]] == External Debug Security Threat model -Modern SoC development consists of several different actors who may not trust each other, resulting in the need to isolate actors’ assets during the development and debugging phases. The current RISC-V Debug specification cite:[dbgspec] grants external debuggers the highest privilege in the system regardless of the privilege level at which the target system is running. This leads to privilege escalation issues when multiple actors are present. - -For example, the owner of a SoC, who needs to debug their M-mode firmware, may be able to use the external debugger to bypass PMP lock (pmpcfg.L=1) and attack Boot ROM (the SoC creator’s asset). - -Additionally, RISC-V privilege architecture supports multiple software entities or "supervisor domains" that do not trust each other. The supervisor domains are managed by secure monitor running in M-mode, they are isolated from each other by PMP/IOPMP and they may need different debug policies. The entity that owns secure monitor wants to disable external debug when shipping the secure monitor, however, the entity that owns the supervisor domain needs to enable external debug to develop the supervisor domain. Since the external debugger will be the granted highest privilege in the system, a malicious supervisor domain will be able to compromise M-mode secure monitor with the external debugger. - - - +Modern SoC development consists of several different actors who may not trust each other, resulting in the need to isolate actors’ assets during the development and debugging phases. The current RISC-V Debug specification cite:[dbgspec] grants external debuggers the highest privilege in the system, regardless of the privilege level at which the target system is running. This leads to privilege escalation issues when multiple actors are present. +For example, the owner of an SoC, who needs to debug their M-mode firmware, may be able to use the external debugger to bypass PMP lock (pmpcfg.L=1) and attack Boot ROM (the SoC creator’s asset). +Additionally, RISC-V privilege architecture supports multiple software entities, or "supervisor domains," that do not trust each other. The supervisor domains are managed by a secure monitor running in M-mode, are isolated from each other by PMP/IOPMP, and may need different debug policies. The entity that owns the secure monitor wants to disable external debug when shipping the secure monitor; however, the entity that owns the supervisor domain needs to enable external debug to develop the supervisor domain. Since the external debugger will be the granted highest privilege in the system, a malicious supervisor domain will be able to compromise M-mode secure monitor with the external debugger. From d51207d3cfe48ad38a9008393ce24c955bffed0c Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 15:33:19 -0700 Subject: [PATCH 03/14] minor text improvements to chaper2.adoc --- chapter2.adoc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chapter2.adoc b/chapter2.adoc index 896a45c..b9380a3 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -1,7 +1,7 @@ [[Sdsec]] == Sdsec (ISA extension) -This chapter introduces the Sdsec ISA extension, which enhances the Sdext extension defined in _The RISC-V Debug Specification_ cite:[dbgspec]. The Sdsec extension provides privilege based protection for debug operations and triggers in Sdtrig cite:[dbgspec]. Furthermore, it constrains trace functionality cite:[etrace] according to RISC-V privilege levels. +This chapter introduces the Sdsec ISA extension, which enhances the Sdext extension defined in _The RISC-V Debug Specification_ cite:[dbgspec]. The Sdsec extension provides privilege based protection for debug operations, and for triggers in Sdtrig cite:[dbgspec]. Furthermore, it constrains trace functionality cite:[etrace] according to RISC-V privilege levels. [[sdsecextdbg]] === External Debug @@ -11,15 +11,15 @@ Chapter 3 of _The RISC-V Debug Specification_ cite:[dbgspec] outlines all mandat [[dbops]] .Debug operations affected by Sdsec * Halting the hart to enter Debug Mode -* Executing Program buffer +* Executing the Program Buffer * Serving abstract commands (Access Register, Access Memory) -When external debug is disallowed in running privilege level, the hart behaves as the following: +When external debug is disallowed in the current privilege level, the hart behaves as follows: [[dbgdisallowed]] * The hart will not enter Debug Mode. Halt requests will remain pending until debug is allowed. * Triggers with `action`=1 will not match or fire. -* Abstract commands without halting will be dropped and set `cmderr` to 6. +* "Quick Access" Abstract Commands, which do not require the hart to be in the halted state, will be dropped and set `abstractcs.cmderr` to 6. The subsequent subsections describe how external debug is authorized by <> and <>. @@ -31,14 +31,14 @@ A pending request to enter Debug Mode can dynamically change from a disallowed s A state element in each hart, named `mdbgen`, is introduced to control the debuggability of M-mode for each hart as depicted in <>. When `mdbgen` is set to 1, the following rules apply: -- The <> for the hart can be configured to any legal privilege level -- The <> are permitted when the hart executes in all modes -- Abstract commands without halting the hart carries M-mode privilege if supported +- The <> for the hart is M-mode +- The <> are permitted when the hart executes in any privilege mode +- Abstract Commands, including "Quick Access", and Program Buffer execution operate with M-mode privilege When `mdbgen` is set to 0, the <> are disallowed and the <> applies when the hart runs in M-mode. [NOTE] -`Mdbgen` may be controlled through various methods, such as a new input port to the hart, a handshake with the system Root of Trust (RoT), or other methods. The implementation can choose to group several harts together and use one signal to drive their `mdbgen` state or assign each hart its own dedicated state. For example, a homogeneous computing system can use a signal to drive all `mdbgen` state to enforce a unified debug policy across all harts. +`mdbgen` may be controlled through various methods, such as a new input port to the hart, a handshake with the system Root of Trust (RoT), or other methods. The implementation can choose to group several harts together and use one signal to drive their `mdbgen` state or assign each hart its own dedicated state. For example, a homogeneous computing system can use a signal to drive all `mdbgen` state to enforce a unified debug policy across all harts. [[submdbgctl]] ==== Supervisor Domain Debug Control From e27da2842faf7926fb28516edd40f8b61f60bb0e Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 16:11:17 -0700 Subject: [PATCH 04/14] fix definition of Debug Allowed Privilege, doesn't depend on dcsr --- chapter2.adoc | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/chapter2.adoc b/chapter2.adoc index b9380a3..df9dc7f 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -42,39 +42,39 @@ When `mdbgen` is set to 0, the <> are disallowed and th [[submdbgctl]] ==== Supervisor Domain Debug Control -The Smsdedbg extension cite:[smmtt] introduces `sdedbgalw` field (bit 7) in CSR <> to control the debuggability of supervisor domains. The `sdedbgalw` along with `mdbgen` determines the debug allowed privilege levels, as illustrated in <>. The <> can only be configured to debug allowed levels. +The Smsdedbg extension cite:[smmtt] introduces `sdedbgalw` field (bit 7) in CSR <>, to control the debuggability of supervisor domains. When `mdbgen`=0, the `sdedbgalw` field determines both the debug allowed privilege modes and the <>, as illustrated in <>. [[dbgpriv]] [options="header"] -[cols="25%,25%,50%"] -.External debug allowed privilege levels per debug controls +[cols="15%,15%,35%,35%"] +.External Debug Configuration and Privilege |============================================ -| mdbgen | sdedbgalw | Debug allowed privilege levels -| 1 | Don't care | All -| 0 | 1 | All except M -| 0 | 0 | None +| mdbgen | sdedbgalw | Debug allowed privilege modes | Debug access privilege +| 1 | Don't care | All | M-mode +| 0 | 1 | All except M | S-mode +| 0 | 0 | None | N/A |============================================ -When debug is allowed in supervisor domain, <> are allowed when hart executes in supervisor domain. The abstract commands without halting the hart carries supervisor mode privilege if supported. - [[dbgaccpriv]] ==== Debug Access Privilege -The *debug access privilege* is defined as the privilege level granted to the external debugger to access hardware resources with abstract commands or program buffers. Memory and register accesses from Debug Mode also carry *debug access privilege* instead of always with M-mode. The *debug access privilege* is represented by the `prv` and `v` fields in `dcsr` or <>. The legal privilege levels programmable to the fields in Debug Mode are elaborated in <>. Debugger accesses to registers and memory will be checked by permission check mechanisms against *debug access privilege*, and trap if they violate corresponding rules. +The *debug access privilege* is defined as the privilege level granted to the external debugger when performing state accesses via the hart, such as Abstract Commands and Program Buffer execution. Any attempt by the debugger to access state inaccessible to *debug access privilege* will return an error. [[prvvacc]] ===== Configuring External Debugger Access Privileges -The `prv` and `v` fields have been modified to authorize privilege for external debug accesses. Upon transitioning into Debug Mode, the `prv` and `v` fields are updated to the privilege level the hart was previously operating in. The maximum debug privilege level that can be configured in `prv` and `v` is determined in <>. The fields retain legal values when the `prv` and `v` are configured with an illegal privilege level. Illegal privilege levels include unsupported levels and any level higher than the maximum allowed debug privilege. When the hart resumes from Debug Mode, the current privilege mode and virtualization mode are changed to that specified by `prv` and `v`. +The `prv` and `v` fields in `dcsr` are updated with the current privilege mode on Debug Mode entry, and are used to set the new privilege mode on resume from Debug Mode. The debugger may modify the `prv` and `v` fields, to alter the mode of execution upon resume, but the allowed values are constrained by the debugger privilege. + +The maximum debug privilege level that can be configured in `prv` and `v` is shown in <>. On a write that attempts to write an illegal value to `prv` and/or `v`, the fields retain legal values. Illegal privilege levels include values higher than the maximum allowed debug privilege. [[maxdbgpriv]] [options="header"] -.Determining maximum debug access privilege with mdbgen and sdedbgalw +.Maximum Allowed Resume Privilege Mode |========================================= -| mdbgen | sdedbgalw | Maximum debug privilege allowed -| 1 | Don't care | M -| 0 | 1 | S(HS) -| 0 | 0 | None +| mdbgen | sdedbgalw | Maximum privilege allowed on resume +| 1 | Don't care | M +| 0 | 1 | S(HS) +| 0 | 0 | N/A |========================================= [NOTE] From 61faf95e6d893211768e5ed8b6b675e43936602a Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 16:21:39 -0700 Subject: [PATCH 05/14] minor text improvements to chapter 2 priv level changing instructions section --- chapter2.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chapter2.adoc b/chapter2.adoc index df9dc7f..e9c4374 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -82,7 +82,7 @@ As the `prv` and `v` fields are Write Any Read Legal (WARL) fields, the external ==== Privilege Level Changing Instructions -The RISC-V Debug Specification cite:[dbgspec] defines that the instructions that change the privilege mode have UNSPECIFIED behavior when executed within the Program Buffer, with exception of the ebreak instruction. In Sdsec, those instructions including mret, sret, uret, ecall, must either act as NOP or trigger an exception (stopping execution and setting `cmderr` to 3) in Program Buffer. Notably, these instructions retain their normal functionality during single stepping. +The RISC-V Debug Specification cite:[dbgspec] defines that the instructions that change the privilege mode have UNSPECIFIED behavior when executed within the Program Buffer, with exception of the EBREAK instruction. In Sdsec, privilege changing instructions (other than EBREAK) executed in the Program Buffer must either act as a NOP or raise an exception (stopping execution and setting `cmderr` to 3). ==== Interrupt during Single Stepping From 9a4ebcf8f7bd2121944036983fb676650e142414 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 16:24:42 -0700 Subject: [PATCH 06/14] minor text improvements to chapter 2 interrupt during single step section --- chapter2.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chapter2.adoc b/chapter2.adoc index e9c4374..2d76f59 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -86,7 +86,7 @@ The RISC-V Debug Specification cite:[dbgspec] defines that the instructions that ==== Interrupt during Single Stepping -The interrupt can be disabled by `stepie` in `dcsr` during single stepping. When `mdbgen` is 1, `stepie` disables interrupts in all privilege modes for the hart. When `mdbgen` is 0 and `sdedbgalw` is 1, only interrupts delegated to the supervisor domain are disabled, while interrupts that trap to M-mode are not affected. +Interrupts during single-step can be disabled by setting `dcsr.stepie`=1. When `mdbgen` is 1, `stepie` disables interrupts in all privilege modes for the hart. When `mdbgen` is 0 and `sdedbgalw` is 1, only delegated interrupts are disabled, while interrupts that trap to M-mode are not affected. [NOTE] When debugging is only allowed for the supervisor domain, M-mode interrupts must not be disabled. Otherwise, debugging might impact the behavior of other parts of the system. For example, if a context switch for the supervisor domain triggered by a timer interrupt is suppressed, some real-time workloads might not be completed on time, resulting in unexpected errors. From dbf2a3e0f1721b168d1c5b959f44ce6acb6ce4b1 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 16:36:18 -0700 Subject: [PATCH 07/14] minor text improvements to chapter 2 trace sections --- chapter2.adoc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chapter2.adoc b/chapter2.adoc index 2d76f59..cb03156 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -95,15 +95,15 @@ When debugging is only allowed for the supervisor domain, M-mode interrupts must When Sdsec is supported, trace, as a non-intrusive debug method, will be constrained based on RISC-V privilege level. The availability of trace output is indicated through the interface defined in <<<_reference to the trace interface doc_>>> to trace module. ==== M-Mode Trace Control -Each hart must add a new state element, `mtrcen`, which controls the availability of M-mode tracing. Setting `mtrcen` to 1 enables trace for both M-mode and the supervisor domain; setting `mtrcen` to 0 disables trace output when the hart is running in M-mode. +Each hart must add a new state element, `mtrcen`, which controls the availability of M-mode tracing. Setting `mtrcen` to 1 enables trace for both M-mode and the supervisor domain; setting `mtrcen` to 0 inhibits trace when the hart is running in M-mode. [NOTE] Similar to M-mode debug control, `mtrcen` may be controlled through various methods, such as a new input port to the hart, a handshake with the system Root of Trust (RoT), or other methods. The implementation may group several harts together and use one signal to drive their `mtrcen` state or assign each hart its own dedicated state. ==== Supervisor Domain Trace Control -The Smsdetrc extension introduces `sdetrcalw` field (bit 8) in CSR <> within a hart. The trace availability for a hart in supervisor domain is determined by the `sdetrcalw` field and `mtrcen`. If either `sdetrcalw` or `mtrcen` is set to 1, the trace output is allowed when the hart runs in the supervisor domain. +The Smsdetrc extension introduces `sdetrcalw` field (bit 8) in CSR <> within a hart. The trace availability for a hart in supervisor domain is determined by the `sdetrcalw` field and `mtrcen`. If either `sdetrcalw` or `mtrcen` is set to 1, trace can be enabled when the hart runs in the supervisor domain. -When both `sdetrcalw` and `mtrcen` are set to 0, trace output is inhibited at all privilege levels. +When both `sdetrcalw` and `mtrcen` are set to 0, trace is inhibited in all privilege levels. === Trigger (Sdtrig) From d7e3ed8f136123aa2a221f777614fd911c889321 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 16:54:55 -0700 Subject: [PATCH 08/14] minor text improvements to chapter 2 trigger sections --- chapter2.adoc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/chapter2.adoc b/chapter2.adoc index cb03156..7720324 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -105,7 +105,7 @@ The Smsdetrc extension introduces `sdetrcalw` field (bit 8) in CSR <>. @@ -114,16 +114,16 @@ Implementations must ensure that pending triggers intending to enter Debug Mode ==== M-mode Accessibility to `dmode` -When Sdsec extension is implemented, `dmode` is read/write for both M-mode and Debug Mode when `mdbgen` is 0 and remains only accessible to Debug Mode when `mdbgen` is 1. +When Sdsec extension is implemented, `dmode` is read/write for both M-mode and Debug Mode when `mdbgen` is 0, and remains only accessible to Debug Mode when `mdbgen` is 1. [NOTE] -The `dmode` being read/write allows M-mode to switch trigger context. The trigger can form a side-channel to debug disallowed supervisor domains from a debug allowed supervisor domain if the trigger context is not switched. Although the trigger cannot fire or match in disallowed supervisor domain to enter Debug Mode, the malicious debugger can exploit it by setting a trigger to raise breakpoint exception (`action` = 0) when it is in debug allowed supervisor domain. If the trigger hits in debug disallowed supervisor domain, the external debugger can indirectly observe the executed PC, accessed memory address or read/write data in debug disallowed supervisor domain by the checking value in `hit0`/`hit1`. As the `dmode` is accessible when `mdbgen` is 0, such attack can be mitigated by having M-mode firmware switch the trigger context at supervisor domain boundary. +Allowing M-mode to have write access to `dmode` allows M-mode to save/restore trigger context on behalf of a supervisor debugger. Otherwise a trigger could serve as a side-channel to debug disallowed supervisor domains from a debug allowed supervisor domain. Although the trigger could take action (breakpoint exception or Debug Mode entry) in a disallowed supervisor domain, the action could be pended and taken once a debug allowed supervisor domain is entered. This could allow the external debugger to indirectly observe the state from the debug disallowed supervisor domain (PC, data address, etc). By making `dmode` M-mode accessible when `mdbgen` is 0, such an attack can be mitigated by having M-mode firmware switch the trigger context at supervisor domain boundary. ==== External Triggers The external trigger outputs (with `action` = 8/9) will not fire or match when the privilege level of the hart exceeds debug allowed privilege as specified in <>. -The external trigger input can be driven by any input signals, e.g. the external trigger output from another hart or interrupt signals etc. The input signals cause the trigger (with `action` = 1) to fire only when the hart is allowed to debug. The initiators of these signals are responsible for determining whether the signal is allowed to assert. For example, if the external trigger input of hart i is connected to external trigger output of hart j. The assertion of output signal from hart j is determined by its own allowed privilege level for debug. The output signal of hart j must not assert when debug is disallowed. Similarly, signals from other module in the system are managed by the individual module. When the module is not allowed to debug, the signal connected to external trigger input must not be asserted. +The external trigger input can be driven by any input signals, e.g. the external trigger output from another hart, interrupt signals, etc. The input signals cause the trigger (with `action` = 1) to fire only when the hart is allowed to debug. The initiators of these signals are responsible for determining whether the signal is allowed to assert. For example, if the external trigger input of hart _i_ is connected to external trigger output of hart _j_, the assertion of output signal from hart _j_ is determined by its own allowed privilege level for debug. The output signal of hart _j_ must not assert when debug is disallowed. Similarly, signals from other modules in the system are managed by the individual module. When the module is not debug allowed, the signal connected to external trigger input must not be asserted. [NOTE] This represents a balance between usability and hardware complexity. There may be instances where the triggers are linked across different privilege levels (e.g., from S-mode to M-mode), while the external debugger may only have access with S-mode privilege. The external debugger should not modify the chain, because it could be suppressed or incorrectly match or fire in M-mode. From c7ec2d2d6119b011aedcff2ad34e9aaa5fa1baf3 Mon Sep 17 00:00:00 2001 From: beeman Date: Thu, 17 Oct 2024 17:32:03 -0700 Subject: [PATCH 09/14] minor text improvements to chapter 2 other --- chapter2.adoc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chapter2.adoc b/chapter2.adoc index 7720324..9d02418 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -147,7 +147,7 @@ The `sdcsr` and `sdpc` registers provide supervisor read/write access to the `dc The `sdcsr` register exposes a subset of `dcsr`, formatted as shown in <>, while the `sdpc` register provides full access to `dpc`. [NOTE] -Unlike `dcsr` and `dpc`, the scratch registers do not have supervisor access, and external debuggers with S-mode privilege cannot not use them as scratch memory. +Unlike `dcsr` and `dpc`, the `dscratch*` registers do not have a supervisor access mechanism, and external debuggers with S-mode privilege cannot not use them. [caption="Register {counter:rimage}: ", reftext="Register {rimage}"] [title="Supervisor debug control and status register (sdcsr)"] @@ -179,7 +179,7 @@ Unlike `dcsr` and `dpc`, the scratch registers do not have supervisor access, an .... [NOTE] -The `nmip`, `mprven`, `stoptime`, `stopcount`, `ebreakm` and `cetrig` fields in `dcsr` are configurable only by M-mode, masked from `sdcsr` while the `prv` field is constrained to 1 bit. +The `nmip`, `mprven`, `stoptime`, `stopcount`, `ebreakm` and `cetrig` fields in `dcsr` are configurable only by M-mode, masked from `sdcsr`, while the `prv` field is constrained to 1 bit. [caption="Register {counter:rimage}: ", reftext="Register {rimage}"] [title="Supervisor debug program counter (sdpc)"] @@ -207,5 +207,5 @@ When M-mode enables debugging for supervisor domain, it can optionally delegate [[Sdseccsr]] ==== Debug Control CSR -The CSR holding the debug and trace contol knobs for supervisor domain are specified in Smsdedbg and Smsdetrc extension respectively in _RISC-V Supervisor Domains Access Protection_ cite:[smmtt]. The Smsdedbg and/or Smsdetrc extension must be implemented to support security control for debugging and/or tracing in supervisor domain. +The CSR holding the debug and trace control knobs for supervisor domain are specified in the Smsdedbg and Smsdetrc extensions, respectively, defined in _RISC-V Supervisor Domains Access Protection_ cite:[smmtt]. The Smsdedbg and/or Smsdetrc extensions must be implemented to support security control for debugging and/or tracing in supervisor domains. From 1c2a90f15316bc9dfe2173c0f3fa950f6146c09a Mon Sep 17 00:00:00 2001 From: beeman Date: Fri, 18 Oct 2024 17:24:54 -0400 Subject: [PATCH 10/14] minor text improvements to chapter 3 --- chapter3.adoc | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/chapter3.adoc b/chapter3.adoc index aa6703a..4a126b5 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -1,7 +1,7 @@ [[dmsext]] -== Debug Module Security Extension (non-ISA extension) +== Debug Module Security (non-ISA) Extension -This chapter outlines the security enhancements defined for the Debug Module as non-ISA extension. The debug operations listed below are modified by the non-ISA extension. All features in this chapter must be implemented in Debug Module to achieve external debug security. If any hart in the system implements the Sdsec extension, the Debug Module must also implement the non-ISA extension. The debug operations affected by the non-ISA extension include: +This chapter defines the required security enhancements for the Debug Module. The debug operations listed below are modified by the extension. * Halt * Reset @@ -9,29 +9,28 @@ This chapter outlines the security enhancements defined for the Debug Module as * Abstract commands (Access Register, Quick Access, Access Memory) * System bus access +Further, all harts in the system must implement Sdsec. + === External Debug Security Extensions Discovery -The ISA and non-ISA external debug security extensions impose security constraints and introduce non-backward-compatible changes. The presence of the extensions can be determined by polling the `allsecured` or/and `anysecured` bits in dmstatus <>. If the field `allsecured` or `anysecured` is set to 1, it represents that all or any selected harts adopt the Sdsec extension. When any hart adopts the Sdsec extension, it indicates the Debug Module implements Debug Module Security Extension as described in this chapter. +The ISA and non-ISA external debug security extensions impose security constraints and introduce non-backward-compatible changes. The presence of the extensions can be determined by polling the `allsecured` or/and `anysecured` bits in `dmstatus` <>. If the field `allsecured` or `anysecured` is set to 1, it represents that all or any selected harts adopt the Sdsec extension. When any hart adopts the Sdsec extension, it indicates the Debug Module implements Debug Module Security Extension as described in this chapter. === Halt -The halt behavior for a hart is detailed in <>. According to _The RISC-V Debug Specification_ cite:[dbgspec], a halt request must be responded within one second. However, this constraint must be removed as the request might be pending due to the situations where debugging is disallowed. In the case of halt-on-reset request, the request is only acknowledged by the hart when it is permitted to debug after the deassertion of reset. Besides, when a Quick Access abstract command is issued to a hart while the hart is not yet allowed to debug, the Quick Access cannot halt the hart, and the Debug Module will receive a security error fault (`cmderr`=6). - -[NOTE] -The halt action in Quick Access is handled differently because other types of halts can be canceled by external debugger when debugging is disallowed, while the Quick Access command can only complete successfully or respond with an error. Otherwise, the debug interface to the selected hart will appear to be hung. Additionally, reset is not always applicable to the hart to recover from a hang situation. To avoid such situations, the halt action in Quick Access must be handled separately. +The halt behavior for a hart is detailed in <>. According to _The RISC-V Debug Specification_ cite:[dbgspec], a halt request must be responded within one second. However, this constraint must be removed as the request might be pending due to the situations where debugging is disallowed. In the case of halt-on-reset request, the request is only acknowledged by the hart once it has reached a privilege level in which debug is permitted. === Reset -The hartreset operation resets selected harts. When M-mode is not allowed to be debugged, the hart will raise a security fault error to Debug Module. The debugger could monitor the error by polling `allsecfault` or/and `anysecfault` in dmstatus. +The hartreset operation resets selected harts. When M-mode is not allowed to be debugged, the hart will raise a security fault error to the Debug Module. The debugger could monitor the error by polling `allsecfault` or/and `anysecfault` in `dmstatus`. -The ndmreset operation is a system-level reset not tied to hart privilege levels and reset the entire system (excluding the Debug Module). It can only be secured by the system. Thus, it must be de-featured. The debugger can determine support for the ndmreset operation by setting the field to 1 and subsequently verifying the returned value upon reading. +The ndmreset operation is a system-level reset not tied to hart privilege levels and reset the entire system (excluding the Debug Module). Debug Module Security makes ndmreset read-only 0. The debugger can determine support for the ndmreset operation by setting the field to 1 and subsequently verifying the returned value upon reading. === Keepalive The keepalive bit serves as an optional request for the hart to remain available for debugging. This bit only takes effect when M-mode is allowed to be debugged; otherwise, the hart behaves as if the bit is not set. === Abstract Commands -The hart's response to abstract commands is detailed in <>. The following subsection delineates the constraints when the Debug Module issues the abstract commands. +The hart's response to abstract commands is detailed in <>. The following subsection delineates the constraints when the Debug Module issues an abstract command. ==== Relaxed Permission Check `relaxedpriv` @@ -43,7 +42,7 @@ The field `aamvirtual` in the command (at 0x17 in the Debug Module) determines w ==== Quick Access -When M-mode debugging is not allowed (`mdbgen`=0) for a hart, any Quick Access operation will be discarded, causing `cmderr` being set to 6. +When M-mode debugging is not allowed (`mdbgen`=0) for a hart, any Quick Access operation will be discarded, causing `abstractcs.cmderr` to set to 6. [NOTE] Quick Access abstract commands effect a halt, execution of Program Buffer, and resume of the selected hart. However, it is undesirable for these Quick Access halts to remain pending until debug is allowed, since the debugger blocks while waiting for the Quick Access to complete. Returning an error only for Quick Access commands received when debug is not allowed would require the hart to distinguish between Quick Access halt requests and other halt requests. Because Quick Access is merely an optimized flow and not required for any usage models, it was decided to avoid burdening the hart with extra hardware. Therefore, Quick Access is forbiden when `mdbgen` is 0. From 12ae3d2461282dd01fc614f1c9a22aeddffb6458 Mon Sep 17 00:00:00 2001 From: beeman Date: Fri, 1 Nov 2024 09:34:54 -0700 Subject: [PATCH 11/14] get rid of italics preceding list --- chapter2.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chapter2.adoc b/chapter2.adoc index 9d02418..02cf8cc 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -9,7 +9,7 @@ This chapter introduces the Sdsec ISA extension, which enhances the Sdext extens Chapter 3 of _The RISC-V Debug Specification_ cite:[dbgspec] outlines all mandatory and optional debug operations. The operations listed below are affected by the Sdsec extension, other operations remain unaffected. In the context of this chapter, *debug operations* refer to those listed below. [[dbops]] -.Debug operations affected by Sdsec +Debug operations affected by Sdsec: * Halting the hart to enter Debug Mode * Executing the Program Buffer * Serving abstract commands (Access Register, Access Memory) From bc1c0a268861b044c604c43e43f107318b3c3cd8 Mon Sep 17 00:00:00 2001 From: Aote Jin Date: Thu, 7 Nov 2024 15:53:37 +0800 Subject: [PATCH 12/14] Fix some wording Add back description that any hart with Sdsec indicates DM implementing security extension --- chapter2.adoc | 6 +++--- chapter3.adoc | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/chapter2.adoc b/chapter2.adoc index 02cf8cc..d2a9931 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -74,7 +74,7 @@ The maximum debug privilege level that can be configured in `prv` and `v` is sho | mdbgen | sdedbgalw | Maximum privilege allowed on resume | 1 | Don't care | M | 0 | 1 | S(HS) -| 0 | 0 | N/A +| 0 | 0 | None |========================================= [NOTE] @@ -101,7 +101,7 @@ Each hart must add a new state element, `mtrcen`, which controls the availabilit Similar to M-mode debug control, `mtrcen` may be controlled through various methods, such as a new input port to the hart, a handshake with the system Root of Trust (RoT), or other methods. The implementation may group several harts together and use one signal to drive their `mtrcen` state or assign each hart its own dedicated state. ==== Supervisor Domain Trace Control -The Smsdetrc extension introduces `sdetrcalw` field (bit 8) in CSR <> within a hart. The trace availability for a hart in supervisor domain is determined by the `sdetrcalw` field and `mtrcen`. If either `sdetrcalw` or `mtrcen` is set to 1, trace can be enabled when the hart runs in the supervisor domain. +The Smsdetrc extension introduces `sdetrcalw` field (bit 8) in CSR <> within a hart. The trace availability for a hart in supervisor domain is determined by the `sdetrcalw` field and `mtrcen`. If either `sdetrcalw` or `mtrcen` is set to 1, trace can be allowed when the hart runs in the supervisor domain. When both `sdetrcalw` and `mtrcen` are set to 0, trace is inhibited in all privilege levels. @@ -117,7 +117,7 @@ Implementations must ensure that pending triggers intending to enter Debug Mode When Sdsec extension is implemented, `dmode` is read/write for both M-mode and Debug Mode when `mdbgen` is 0, and remains only accessible to Debug Mode when `mdbgen` is 1. [NOTE] -Allowing M-mode to have write access to `dmode` allows M-mode to save/restore trigger context on behalf of a supervisor debugger. Otherwise a trigger could serve as a side-channel to debug disallowed supervisor domains from a debug allowed supervisor domain. Although the trigger could take action (breakpoint exception or Debug Mode entry) in a disallowed supervisor domain, the action could be pended and taken once a debug allowed supervisor domain is entered. This could allow the external debugger to indirectly observe the state from the debug disallowed supervisor domain (PC, data address, etc). By making `dmode` M-mode accessible when `mdbgen` is 0, such an attack can be mitigated by having M-mode firmware switch the trigger context at supervisor domain boundary. +M-mode is given write access to `dmode` to allow it to save/restore trigger context on behalf of a supervisor debugger. Otherwise a trigger could serve as a side-channel to debug disallowed supervisor domains from a debug allowed supervisor domain. Although the trigger could take action (breakpoint exception or Debug Mode entry) in a disallowed supervisor domain, the action could be pended and taken once a debug allowed supervisor domain is entered. This could allow the external debugger to indirectly observe the state from the debug disallowed supervisor domain (PC, data address, etc). By making `dmode` M-mode accessible when `mdbgen` is 0, such an attack can be mitigated by having M-mode firmware switch the trigger context at supervisor domain boundary. ==== External Triggers diff --git a/chapter3.adoc b/chapter3.adoc index 4a126b5..d6aeab5 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -9,7 +9,7 @@ This chapter defines the required security enhancements for the Debug Module. Th * Abstract commands (Access Register, Quick Access, Access Memory) * System bus access -Further, all harts in the system must implement Sdsec. +If any hart in the system implements the Sdsec extension, the Debug Module must also implement the non-ISA extension. === External Debug Security Extensions Discovery @@ -23,7 +23,7 @@ The halt behavior for a hart is detailed in <>. According to _The R The hartreset operation resets selected harts. When M-mode is not allowed to be debugged, the hart will raise a security fault error to the Debug Module. The debugger could monitor the error by polling `allsecfault` or/and `anysecfault` in `dmstatus`. -The ndmreset operation is a system-level reset not tied to hart privilege levels and reset the entire system (excluding the Debug Module). Debug Module Security makes ndmreset read-only 0. The debugger can determine support for the ndmreset operation by setting the field to 1 and subsequently verifying the returned value upon reading. +The ndmreset operation is a system-level reset not tied to hart privilege levels and reset the entire system (excluding the Debug Module). Debug Module Security Extension makes ndmreset read-only 0. The debugger can determine support for the ndmreset operation by setting the field to 1 and subsequently verifying the returned value upon reading. === Keepalive From c924aee2f03dccb51a3a8ba9c0a19ea98429c2bd Mon Sep 17 00:00:00 2001 From: Aote Jin Date: Thu, 7 Nov 2024 18:12:12 +0800 Subject: [PATCH 13/14] Add back description that any hart with Sdsec indicates DM implementing security extension --- chapter3.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chapter3.adoc b/chapter3.adoc index d6aeab5..2f63131 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -9,7 +9,7 @@ This chapter defines the required security enhancements for the Debug Module. Th * Abstract commands (Access Register, Quick Access, Access Memory) * System bus access -If any hart in the system implements the Sdsec extension, the Debug Module must also implement the non-ISA extension. +If any hart in the system implements the Sdsec extension, the Debug Module must also implement the Debug Module Security Extension. === External Debug Security Extensions Discovery From a6dd932fb47d7ce9c70f9188c4b228b39264d786 Mon Sep 17 00:00:00 2001 From: Aote Jin Date: Mon, 11 Nov 2024 11:44:49 +0800 Subject: [PATCH 14/14] Update the note for `dmode` --- Makefile | 2 +- chapter2.adoc | 11 +++++++++-- chapter3.adoc | 6 +++--- external-debug-security.pdf | Bin 230030 -> 228622 bytes 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 213830c..2455bb5 100644 --- a/Makefile +++ b/Makefile @@ -13,7 +13,7 @@ # the Doc Template for RISC-V Extensions. DATE ?= $(shell date +%Y-%m-%d) -VERSION ?= v0.5.2 +VERSION ?= v0.6.0 REVMARK ?= Draft DOCKER_RUN := docker run --rm -v ${PWD}:/build -w /build \ riscvintl/riscv-docs-base-container-image:latest diff --git a/chapter2.adoc b/chapter2.adoc index d2a9931..e9bc843 100644 --- a/chapter2.adoc +++ b/chapter2.adoc @@ -82,7 +82,7 @@ As the `prv` and `v` fields are Write Any Read Legal (WARL) fields, the external ==== Privilege Level Changing Instructions -The RISC-V Debug Specification cite:[dbgspec] defines that the instructions that change the privilege mode have UNSPECIFIED behavior when executed within the Program Buffer, with exception of the EBREAK instruction. In Sdsec, privilege changing instructions (other than EBREAK) executed in the Program Buffer must either act as a NOP or raise an exception (stopping execution and setting `cmderr` to 3). +The RISC-V Debug Specification cite:[dbgspec] defines that the instructions that change the privilege mode have UNSPECIFIED behavior when executed within the Program Buffer, with exception of the EBREAK instruction. In Sdsec, privilege changing instructions (other than EBREAK) executed in the Program Buffer must either act as a NOP or raise an exception (stopping execution and setting `abstractcs.cmderr` to 3). ==== Interrupt during Single Stepping @@ -117,7 +117,14 @@ Implementations must ensure that pending triggers intending to enter Debug Mode When Sdsec extension is implemented, `dmode` is read/write for both M-mode and Debug Mode when `mdbgen` is 0, and remains only accessible to Debug Mode when `mdbgen` is 1. [NOTE] -M-mode is given write access to `dmode` to allow it to save/restore trigger context on behalf of a supervisor debugger. Otherwise a trigger could serve as a side-channel to debug disallowed supervisor domains from a debug allowed supervisor domain. Although the trigger could take action (breakpoint exception or Debug Mode entry) in a disallowed supervisor domain, the action could be pended and taken once a debug allowed supervisor domain is entered. This could allow the external debugger to indirectly observe the state from the debug disallowed supervisor domain (PC, data address, etc). By making `dmode` M-mode accessible when `mdbgen` is 0, such an attack can be mitigated by having M-mode firmware switch the trigger context at supervisor domain boundary. +M-mode is given write access to `dmode` to allow it to save/restore trigger context on behalf of a supervisor debugger. Otherwise a trigger could serve as a side-channel to debug disallowed supervisor domains from a debug allowed supervisor domain. + + +Although the trigger could take action (breakpoint exception or Debug Mode entry) in a disallowed supervisor domain, the action could be pended and taken once a debug allowed supervisor domain is entered. + +The trigger can raise breakpoint exception in a debug disallowed supervisor domain, and the breakpoint hit by reading the Sdtrig CSR. + +This could allow the external debugger to indirectly observe the state from the debug disallowed supervisor domain (PC, data address, etc). By making `dmode` M-mode accessible when `mdbgen` is 0, such an attack can be mitigated by having M-mode firmware switch the trigger context at supervisor domain boundary. ==== External Triggers diff --git a/chapter3.adoc b/chapter3.adoc index 2f63131..d4260e5 100644 --- a/chapter3.adoc +++ b/chapter3.adoc @@ -38,7 +38,7 @@ The `relaxedpriv` field is hardwired to 0. ==== Address Translation `aamvirtual` -The field `aamvirtual` in the command (at 0x17 in the Debug Module) determines whether the Access Memory command uses a physical or virtual address. When an Access Memory command is issued with `aamvirtual`=0, the hart must check whether the physical access is allowed to access memory. The hart responds with an exception to the Debug Module when M-mode is not permitted to debug, `tvm` (in mstatus) is set to 1, and `mode` (in satp) enables any kind of virtual translation. In the event of an exception, the Debug Module set `cmderr` to 3 and clear the data registers to 0. +The field `aamvirtual` in the command (at 0x17 in the Debug Module) determines whether the Access Memory command uses a physical or virtual address. When an Access Memory command is issued with `aamvirtual`=0, the hart must check whether the physical access is allowed to access memory. The hart responds with an exception to the Debug Module when M-mode is not permitted to debug, `tvm` (in mstatus) is set to 1, and `mode` (in satp) enables any kind of virtual translation. In the event of an exception, the Debug Module set `cmderr` of `abstractcs` (at 0x16 in Debug Module) to 3 and clear the data registers to 0. ==== Quick Access @@ -49,14 +49,14 @@ Quick Access abstract commands effect a halt, execution of Program Buffer, and r === System Bus Access -The System Bus Access must be checked by bus initiator protection mechanisms such as IOPMP cite:[iopmp], WorldGuard cite:[worldguard]. The bus protection unit can return error to Debug Module on illegal access, in that case, Debug Module will set `sberror` to 6 (security fault error). +The System Bus Access must be checked by bus initiator protection mechanisms such as IOPMP cite:[iopmp], WorldGuard cite:[worldguard]. The bus protection unit can return error to Debug Module on illegal access, in that case, Debug Module will set `sberror` of `sbcs` (at 0x38 in Debug Module) to 6 (security fault error). [NOTE] Trusted entities like RoT should configure IOPMP or equivalent protection before granting debug access to M-mode. Similarly, M-mode should apply the protection before enabling supervisor domain debug. === Security Fault Error Reporting -A dedicated error code, security fault error (cmderr 6), is included in `cmderr` of `abstractcs` (at 0x16 in Debug Module). Issuance of abstract commands under disallowed circumstance sets `cmderr` to 6. Additionally, the bus security fault error (sberror 6) is introduced in `sberror` of `sbcs` (at 0x38 in Debug Module) to denote errors related to system bus access. +A dedicated error code, security fault error (cmderr 6), is included in `cmderr` of `abstractcs`. Issuance of abstract commands under disallowed circumstance sets `cmderr` to 6. Additionally, the bus security fault error (sberror 6) is introduced in `sberror` of `sbcs` to denote errors related to system bus access. The error raised by resethaltreq, reset can be identified through the fields `allsecfault` and `anysecfault` in dmstatus. Error status bits are internally maintained for each hart, with the `allsecfault` and `anysecfault` fields indicating the error status of the currently selected harts. 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