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spec v0.5 ch 1 - ch 3 feedback #36
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Thanks Beeman for the insightful feedback! 3.1 3.1.2 3.1.3
3.2
3.4
3.4.2 I made updates according to your feedback in PR #38 |
Without cmderr=6 the user may assume the command was successful, if the last command left cmderr=0.
But since halted already has an established behavior, it may be better to go with 0b01. So define sec_check as 0 when halted=1.
I see. Is that necessary though? If medbgen=1 and a halt occurs in U-mode, why would we prevent the debugger from being able to write all the bits? dcsr is already a special case, it is only writable in debug mode today, no other priv mode check apply. So rather than introducing complicated priv mode checks per field, couldn't the fields be put into one of two buckets (requires medbgen=1 and doesn't require medbgen=1)? btw, there is a typo in table 4. "ebeaks" -> "ebreaks" All the other stuff sounds good. |
I think you make sense for 3.1.3 and 3.4. Updated in PR #38 I suppose it is more appropriate to define of the behavior of vector [sec_check, halted] in trace repo, could we move the discussion over there? |
Are you only referring to command.cmdtype=1 (Quick Access) here for cmderr=6? If Yes, I am fine with the change.
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Actually I am referring to In this case, it is not appropriate to set cmderr to 4. |
I don't see the changes for 3.1.3 and 3.4 in PR #38 ? And yes, moving the sec_check discussion to the trace issue sounds good. |
Actually, I take it back, I think changes are needed in this spec for the encoder interface. The interface is changing to an encoded input (name TBD, based on the trace issue you linked above), so this spec should not refer to individual bit names. [sec_check, halted] is misleading, since the implementation actually needs to do something like:
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Hi @bcstrongx, the updates based on your feedback are included in PR #47 . Thanks a lot! |
Great, I'll review the PR this week |
Close as PR merged to main branch. |
By chapter.
3.1
By default, the extension forbids the following debug operation in The debug operations affected by Zedsec extension unless they are explicitly granted to the external debugger.
Linking to the text that immediately follows, including a capitalized word in the middle of the sentence, seems odd. Perhaps it would be more clear to say:3.1.2
For the homogeneous computing system
. Same for 3.2.1.triggers configured to enter Debug Mode will neither fire nor match in machine mode.
is this necessary? If medbgen[i]=0, then debug mode can't access the trigger registers (since that requires M-mode privilege), so an external debugger couldn't setup a trigger to enter debug mode. With this extension I guess M-mode can now set dmode=1 on behalf of the S-mode debugger, but couldn't we rely on M-mode to keep tdata1.m=0 for such triggers, ensuring they never match/fire in M-mode? Or perhaps the HW could even force that, such that tdata1.m = wrval.m & ~(wrval.dmode & ~medbgen).3.1.3
The submachine mode debug of hart i is determined by the sdedbgalw field of CSR msdcfg within hart i and mdbgen[i].
I recommendThe submachine mode debug of hart i is determined by both mdbgen[i] and the sdedbgalw field of CSR msdcfg within hart i.
The register access without halting is dropped.
Is this referring to abstract commands? Would they be dropped, or cmderr=6?3.2
the combined state of [sec_check, halted] as 0b11 remains unutilized
If mtrcen=0 but medbgen=1, then we could enter debug mode from M-mode, and hence sec_check=halted=1. Unless you're intending to clear sec_check on entry to debug mode, but if so that should be explicitly stated.3.3.2
3.4
3.4.2
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