From 51a4f58e672e40c941c79ad4420e511c6e494903 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Fri, 28 Jun 2024 08:56:35 -0500 Subject: [PATCH] signal fence_w_ip only if iofence completes --- iommu_ref_model/libiommu/src/iommu_command_queue.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/iommu_ref_model/libiommu/src/iommu_command_queue.c b/iommu_ref_model/libiommu/src/iommu_command_queue.c index 83c46621..1f69f237 100644 --- a/iommu_ref_model/libiommu/src/iommu_command_queue.c +++ b/iommu_ref_model/libiommu/src/iommu_command_queue.c @@ -482,12 +482,6 @@ do_iofence_c( if ( PR == 1 || PW == 1 ) iommu_to_hb_do_global_observability_sync(PR, PW); - // The wired-signaled-interrupt (WSI) bit when set to 1 causes a wired-interrupt from the command - // queue to be generated on completion of IOFENCE.C. This bit is reserved if the IOMMU supports MSI - if ( g_reg_file.cqcsr.fence_w_ip == 0 && WSI_BIT == 1 ) { - g_reg_file.cqcsr.fence_w_ip = 1; - generate_interrupt(COMMAND_QUEUE); - } // The AV command operand indicates if ADDR[63:2] operand and DATA operands are valid. // If AV=1, the IOMMU writes DATA to memory at a 4-byte aligned address ADDR[63:2] * 4 as // a 4-byte store. @@ -501,6 +495,12 @@ do_iofence_c( return 1; } } + // The wired-signaled-interrupt (WSI) bit when set to 1 causes a wired-interrupt from the command + // queue to be generated on completion of IOFENCE.C. This bit is reserved if the IOMMU supports MSI + if ( g_reg_file.cqcsr.fence_w_ip == 0 && WSI_BIT == 1 ) { + g_reg_file.cqcsr.fence_w_ip = 1; + generate_interrupt(COMMAND_QUEUE); + } return 0; } // Retry a pending IOFENCE if all invalidations received