diff --git a/docs/RISC-V-N-Trace.adoc b/docs/RISC-V-N-Trace.adoc index e9eadfc..b1b187b 100644 --- a/docs/RISC-V-N-Trace.adoc +++ b/docs/RISC-V-N-Trace.adoc @@ -2,7 +2,7 @@ :description: RISC-V N-Trace (Nexus-based Trace) :company: RISC-V.org :revdate: May 23, 2024 -:revnumber: 1.0.0_rc33 +:revnumber: 1.0.0_rc34 :revremark: Stable state (ready for Freeze) :url-riscv: http://riscv.org :doctype: book @@ -52,9 +52,10 @@ Change is extremely unlikely. PDF generated on: {localdatetime} -=== Version 1.0.0_rc31 -* 2024-05-07 +=== Version 1.0.0_rc34 +* 2024-05-23 ** PDF theme from ISA Manual ADOC. +** Adjusted column widths in tables. ** Accepted by ARC. [Preface] @@ -178,7 +179,7 @@ NOTE: Placement of the Trace Encoder and Trace Control Layer are implementation [#Terms Used In This Specification] .Terms Used In This Specification -[cols="25%,75%",options="header",] +[cols="20%,~",options="header"] |====================================================================================================== |Term| Definition |Message|N-Trace messages are sequences of bytes. First byte of every message includes the TCODE field, which defines the type of information carried in the message and its format. When messages are transmitted or stored, a protocol, described in <> chapter, defines the start and the end of each message. @@ -206,7 +207,7 @@ The table below provides a detailed mapping of causes for terminating an instruc [#Generating itype for different instructions] .Generating itype for different instructions -[cols="20%,40%,40%",options="header",] +[cols="18%,~,35%",options="header"] |====================================================================================================== |Instruction|Condition/Notes|itype Value/Name |Exception in instruction|An exception trap that occurred following the final retired instruction in the block|1 = Exception @@ -262,7 +263,7 @@ Table below defines how N-Trace encoder should handle different 3-bit *itype* va [#Handling of 3-bit itype values] .Handling of 3-bit itype values -[cols="5%,20%,75%",options="header",] +[cols="5%,20%,75%",options="header"] |====================================================================================================== |#|itype|Encoder Action |0|No special type|Only update <> field. @@ -298,7 +299,7 @@ When the *itype* input of ingress port is 4-bit wide, the Indirect jump (with or [#Handling of 4-bit itype values] .Handling of 4-bit itype values -[cols="5%,20%,63%,12%",options="header",] +[cols="5%,20%,63%,12%",options="header"] |====================================================================================================== |#|itype|Encoder Action|Stack Action |8|Indirect call|Update <> field. Emit Indirect Branch message with <>=0|Push @@ -347,7 +348,7 @@ N-Trace message transmission protocol is a strict subset of IEEE-5001 Nexus Stan [N-Trace subset] .N-Trace subset -[cols="33%,20%,45%",options="header",] +[cols="25%,20%,~",options="header"] |==== |Protocol Feature|Nexus Standard|N-Trace (strict subset of Nexus) |Number of *MSEO* bits|1 or 2|2 @@ -385,7 +386,7 @@ The table below provides possible sequences of *MSEO[1:0]* bits (to expand above [#MSEO Transitions] .Transitions of MSEO Bits -[cols="30%,30%",options="header",] +[cols="40%,60%",options="header",align=center,width=80%] |==== |MSEO Function|Previous-*Current* MSEO[1:0] Sequence |Start of message|11-*00* @@ -478,7 +479,7 @@ Table below shows one N-Trace message with several fields. It is an output from [#MDO_MSEO Examples] .MDO and MSEO Encoding Example -[cols="7%,10%,8%,25%,50%",options="header",] +[cols="6%,10%,10%,18%,~",options="header"] |==== |Byte|MDO [5:0]|MSEO [1:0]|Decoded (by reference tool)|Explanation |0xFF| 111111|11 | Idle | Most likely idle, but can also be the last byte of the previous message. @@ -489,7 +490,8 @@ Table below shows one N-Trace message with several fields. It is an output from |0x1D| 000111|01 | U-ADDR[6] = 0x7| This is a single byte variable-length U-ADDR field (with three most significant 0-s). |0xF8| 111110|00 || Normal transfer of new field (6 least significant bits). |0xFF| 111111|11 | HIST[12] = 0xFFE| Last byte of message. It implies the end of the 12-bit HIST field. In this field we do not have any extra most significant 0-s. -5+|Here optional TSTAMP field could be sent (previous MSEO should became 01 encoding end of HIST field, but not end of the message). +5+|Here optional TSTAMP field could be sent + +Previous MSEO should became 01 encoding end of HIST field, but not end of the message). |0xFF| 111111|11 | Idle|This is idle as this is the second byte with MSEO=11 (NOTE: Last byte of message is also 0xFF). |==== @@ -501,7 +503,7 @@ NOTE: The table below does not provide names of Trace Encoder control registers [#Details_Control_Parameters] .Trace Encoder Parameters and Controls -[cols="30%,17%,53%",options="header",] +[cols="25%,15%,~",options="header"] |====================================================================================================== |Trace Control Field|Applicability|Description |trTeActive |*Required*|See <> Specification. @@ -600,26 +602,26 @@ Message field attributes are described using the following terminology: * *[Cfg]*: A configurable field, where the existence and size depend on the encoder configuration options. .Fields in Messages -[cols="27%,9%,6%,7%,9%,17%,8%,10%,7%",options="header",] +[cols="22%,8%,5%,6%,8%,14%,7%,8%,8%,~",options="header",] |=========================================================================================== -| Message ID/Field [size]|<> [6]|<> [Cfg]|<> [4]|<> [2]|Other fields|<> [Var]|<
> [Var]|<> [Var] -|[[msg_Ownership]]<> |2 |Cfg| | |<> *[Var]* | | | -|[[msg_DirectBranch]]<> |3 |Cfg| | | |Yes | | -|[[msg_IndirectBranch]]<> |4 |Cfg| |Yes | |Yes |<>| -|[[msg_Error]]<> |8 |Cfg| | |<> *[4]* + <> *[Var]* | | | -|[[msg_ProgTraceSync]]<> |9 |Cfg|Yes | | |Yes |<>| -|[[msg_DirectBranchSync]]<> |11 |Cfg|Yes | | |Yes |<>| -|[[msg_IndirectBranchSync]]<> |12 |Cfg|Yes |Yes | |Yes |<>| -|[[msg_ResourceFull]]<> |27 |Cfg| | |<> *[4]* + <> *[Var]*| | | -|[[msg_IndirectBranchHist]]<> |28 |Cfg| |Yes | |Yes |<>|Yes -|[[msg_IndirectBranchHistSync]]<>|29 |Cfg|Yes |Yes | |Yes |<>|Yes -|[[msg_RepeatBranch]]<> |30 |Cfg| | |<> *[Var]* | | | -|[[msg_ProgTraceCorrelation]]<> |33 |Cfg| | |<> *[4]* + <> *[2]* |Yes | |*Cfg* -|<>|56..62|Cfg 6+| Designated for use by Vendor Defined messages -|<>|other|Cfg 6+| Reserved for future extensions of N-Trace specification +| Message ID/Field [size]|<> [6]|<> [Cfg]|<> [4]|<> [2]|Other fields|<> [Var]|<
> [Var]|<> [Var]|<> [Var,Cfg] +|[[msg_Ownership]]<> |2 |Cfg| | |<> *[Var]* | | ||Cfg +|[[msg_DirectBranch]]<> |3 |Cfg| | | |Yes | ||Cfg +|[[msg_IndirectBranch]]<> |4 |Cfg| |Yes | |Yes |<>||Cfg +|[[msg_Error]]<> |8 |Cfg| | |<> *[4]* + <> *[Var]* | | ||Cfg +|[[msg_ProgTraceSync]]<> |9 |Cfg|Yes | | |Yes |<>||Cfg +|[[msg_DirectBranchSync]]<> |11 |Cfg|Yes | | |Yes |<>||Cfg +|[[msg_IndirectBranchSync]]<> |12 |Cfg|Yes |Yes | |Yes |<>||Cfg +|[[msg_ResourceFull]]<> |27 |Cfg| | |<> *[4]* + <> *[Var]*| | ||Cfg +|[[msg_IndirectBranchHist]]<> |28 |Cfg| |Yes | |Yes |<>|Yes|Cfg +|[[msg_IndirectBranchHistSync]]<>|29 |Cfg|Yes |Yes | |Yes |<>|Yes|Cfg +|[[msg_RepeatBranch]]<> |30 |Cfg| | |<> *[Var]* | | ||Cfg +|[[msg_ProgTraceCorrelation]]<> |33 |Cfg| | |<> *[4]* + <> *[2]* |Yes | |*Cfg*|Cfg +|<>|56..62|Cfg 7+| Designated for use by Vendor Defined messages +|<>|other|Cfg 7+| Reserved for future extensions of N-Trace specification |=========================================================================================== -IMPORTANT: Any message may include the optional <> *[Var,Cfg]* field as the very last field of a message (it is not shown in above table because of lack of space). It must be enabled by <> control bit. Timestamp field always starts at byte-boundary (as it is always preceded by variable-length field). See <> chapter for more details. +IMPORTANT: Any message may include the optional <> *[Var,Cfg]* field as the very last field of a message. It must be enabled by <> control bit. Timestamp field always starts at byte-boundary (as it is always preceded by variable-length field). See <> chapter for more details. [[msg_other]] NOTE: Messages marked as *Reserved* or *Vendor Defined* should be ignored by decoders interested in program flow only. @@ -670,7 +672,7 @@ NOTE: Reference code is using plain C-style identifiers, so the field name as *B Table below provides details for fields which are used in more than one message type. Fields which are present in only one message are described with each message. .Details of Common Fields -[cols="10%,7%,18%,65%",options="header",] +[cols="9%,5%,15%,~",options="header"] |====================================================================================================== | Name | Bits | Description | Values/Notes 4+|*Fields used in many messages* @@ -679,28 +681,25 @@ Table below provides details for fields which are used in more than one message [[field_SRC]] | SRC | *Cfg* | Source of Message Transmission | Width of SRC field is defined by <> control field and it may be enabled/disabled by <> control bit. This optional field is used to identify the source of the message transmission. In configurations that comprise only a single hart, this field need not be transmitted. For devices that comprise multiple harts, this field must be transmitted (if enabled) as part of the message to identify the source of the message transmission. The transmitted SRC field size should be the same for all enabled trace encoders sharing a trace stream. [[field_SYNC]] -| SYNC | 4 |Reason for Synchronization| Encodings and details are provided in <> chapter. - -NOTE: The SYNC field is always sent together with the <> field, so decoding may start from a message containing the SYNC field. +| SYNC | 4 |Reason for Synchronization| Encodings and details are provided in <> chapter. + +*NOTE:* The SYNC field is always sent together with the <> field, so decoding may start from a message containing the SYNC field. [[field_B-TYPE]] | B-TYPE | 2 | Branch Type | Reason for indirect flow change: + *0:* Indirect control flow change (jump, call or return). + *1:* Exception or interrupt (if the encoder is not capable of reporting 2 and 3). + *2:* *Extension:* Exception + *3:* *Extension:* Interrupt + - NOTE: Either 1-only or both 2 and 3 should be implemented and consistently reported. Extended values 2 and 3 allow trace tools to distinguish exceptions and interrupts easily. +*NOTE:* Either 1-only or both 2 and 3 should be implemented and consistently reported. Extended values 2 and 3 allow trace tools to distinguish exceptions and interrupts easily. [[field_I-CNT]] | I-CNT | *Var* | Instruction Count | As RISC-V allows variable-length instructions, this is the number of 16-bit (INST_LEN/2) instruction units executed/retired since the I-CNT counter was transmitted or reset. See <> chapter for more details. [[field_F-ADDR]] | F-ADDR | *Var* | Full Target Address | Full PC without the least significant bit. The least significant bit is not reported as it is always 0. -See <
> chapter for more details. - - NOTE: The F-ADDR field is always sent together with the <> field. +See <
> chapter for more details. + +*NOTE:* The F-ADDR field is always sent together with the <> field. [[field_U-ADDR]] | U-ADDR | *Var* | Unique part of Target Address | Unique part of PC address (XOR with recently reported address). -See <
> chapter for more details. - +See <
> chapter for more details. + The U-ADDR field is always sent together with the <> field. [[field_HIST]] | HIST | *Var* | Direct Branch History map | Most significant bit (always 1) serves as a 'stop-bit', the least significant bit denotes the last direct conditional branch. See <> chapter for more details. @@ -712,7 +711,7 @@ IEEE-5001 Nexus Standard does not define limits for variable-length fields, but [#Max_Field_Sizes] .Maximum Field Sizes -[cols="22%,30%,8%,50%",options="header",] +[cols="10%,25%,5%,~",options="header"] |====================================================================================================== |Field|Symbol|Bits|Description [[NTRACE_MAX_SRC]] @@ -766,7 +765,7 @@ NOTE: If tracing multiple OS-es, main decoder may route messages to an OS-specif [#Fields_Ownership] .Ownership Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=2(0x2). Standard Transfer Code (<>) field. @@ -783,7 +782,7 @@ Field PROCESS is encoded as 4 sub-fields (FORMAT, PRV, V, CONTEXT). Bit layout i PROCESS[x+5:0] = {CONTEXT[x:0], V[0], PRV[1:0], FORMAT[1:0]} .Encoding of PROCESS field (in LSB to MSB order) -[cols="35%,20%,12%,8%,25%",options="header",] +[cols="35%,20%,12%,8%,25%",options="header",align=center,width=80%] |====================================================================================================== |Reason|FORMAT[1:0]|PRV[1:0]|V[0]|CONTEXT[x:0] | V and/or PRV change |00 |Yes|Yes|-- @@ -816,7 +815,7 @@ This message is generated when the taken direct conditional branch has retired. [#Fields_DirectBranch] .Direct Branch Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=3(0x3). Standard Transfer Code (<>) field. @@ -845,7 +844,7 @@ This message is generated under two conditions: [#Fields_IndirectBranch] .Indirect Branch Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=4(0x4). Standard Transfer Code (<>) field. @@ -873,7 +872,7 @@ An error message must be generated in the event of an internal messages FIFO ove [#Fields_Error] .Error Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=8(0x8). Standard Transfer Code (<>) field. @@ -920,7 +919,7 @@ In above case, Error Message will be the last message in trace stream. [#Fields_ProgTraceSync] .Program Trace Synchronization Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=9(0x9). Standard Transfer Code (<>) field. @@ -943,7 +942,7 @@ Additionally, the F-ADDR field provides the complete PC address at the moment th [#Fields_DirectBranchSync] .Direct Branch with Sync Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=11(0xB). Standard Transfer Code (<>) field. @@ -964,7 +963,7 @@ However, it further includes details on the reason for synchronization via the S [#Fields_IndirectBranchSync] .Indirect Branch with Sync Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=12(0xC). Standard Transfer Code (<>) field. @@ -988,7 +987,7 @@ This mechanism ensures that no information is lost, as it enables the decoder to [#Fields_ResourceFull] .Resource Full Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=27(0x1B). Standard Transfer Code (<>) field. @@ -1023,7 +1022,7 @@ messages. [#Fields_IndirectBranchHist] .Indirect Branch History Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=28(0x1C). Standard Transfer Code (<>) field. @@ -1046,7 +1045,7 @@ Next PC is determine by applying the <
> [#Fields_IndirectBranchHistSync] .Indirect Branch History with Sync Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=29(0x1D). Standard Transfer Code (<>) field. @@ -1069,7 +1068,7 @@ However, it further includes details on the reason for synchronization via the S [#Fields_RepeatBranch] .Repeat Branch Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=30(0x1E). Standard Transfer Code (<>) field. @@ -1091,7 +1090,7 @@ This message is emitted when the trace is disabled or stopped. [#Fields_ProgTraceCorrelation] .Program Trace Correlation Message Fields -[cols="10%,13%,77%",options="header",] +[cols="8%,10%,~",options="header"] |====================================================================================================== |Bits|Name|Description |6 |TCODE |Value=33(0x21). Standard Transfer Code (<>) field. @@ -1456,7 +1455,7 @@ Trace requires different types of synchronization on different abstraction level [#SYNC Field Values] .SYNC Field Values -[cols="7%,18%,12%,63%",options="header",] +[cols="6%,15%,10%,~",options="header"] |==== |Value|Name |Required|Description |0| External Trace Trigger | No | This message serves as a marker of external trigger. If trace is enabled by an external trigger SYNC=5 should be used. @@ -1559,7 +1558,7 @@ However, sometimes normal flow is interrupted (by exception or interrupt) or som [#Corner Cases] .Corner Cases -[cols="25%,75%",options="header",] +[cols="20%,~",options="header"] |==== |Sequence of events|Messages Generated |Back to back return|Second message should have <>=1 or 2 (depending on the size of the second return instruction). @@ -2033,7 +2032,7 @@ Table below is proposing some future enhancements for N-Trace messages. These we [#Future Enhancements] .Future Enhancements -[cols="25%,17%,58%",options="header",] +[cols="17%,17%,~",options="header"] |==== |Enhancement|Conformance|Notes |Instrumentation Data Trace|Nexus Compatible|Very likely (Nexus defines appropriate messages). It will require software to be instrumented by code sending data using trace infrastructure (Arm CoreSight ITM enabled many use-cases). diff --git a/docs/RISC-V-Trace-Connectors.adoc b/docs/RISC-V-Trace-Connectors.adoc index d1aa76a..01ac90c 100644 --- a/docs/RISC-V-Trace-Connectors.adoc +++ b/docs/RISC-V-Trace-Connectors.adoc @@ -2,7 +2,7 @@ :description: RISC-V Trace Connectors :company: RISC-V.org :revdate: May 23, 2024 -:revnumber: 1.0.0_rc33 +:revnumber: 1.0.0_rc34 :revremark: Stable state (ready for Freeze) :url-riscv: http://riscv.org :doctype: book @@ -52,9 +52,10 @@ Change is extremely unlikely. PDF generated on: {localdatetime} -=== Version 1.0.0_rc33 +=== Version 1.0.0_rc34 * 2024-05-23 ** PDF theme from ISA Manual ADOC. +** Adjusted column widths in tables. ** Accepted by ARC. [Preface] @@ -111,7 +112,7 @@ This connector adds 1-bit/2-bit/4-bit parallel trace and serial trace options on [#MIPI20 Connector Layout] .MIPI20 Connector Layout -[cols = "~,8%,8%,~", options = header] +[cols = "~,8%,8%,~", options = header, align=center, width=80%] |========================================================= |Signal |Odd Pin#|Even Pin#|Signal |VREF |1 |2 |TMS / TMSC @@ -132,7 +133,7 @@ NOTE: Smaller MIPI10 version of this connector (pins #1 .. #10 only) is capable [#Details of MIPI20 Signals] .Details of MIPI20 Signals -[cols = "8%,30%,~", options = header] +[cols = "6%,25%,~", options = header] |================================================================================= |Pin# | Pin Name |Explanation | 1 | VREF |Reference voltage for all other pins and signals (single voltage for debug and trace). @@ -200,7 +201,7 @@ Mictor-38 connector provides also an option to have different reference voltages [#Mictor-38 Connector Layout] .Mictor-38 Connector Layout -[cols = "~,10%,8%,8%,10%,~", options = header] +[cols = "~,10%,8%,8%,10%,~", options = header, align=center, width=80%] |====================================== |Signal|Ref Voltage|Odd Pin#|Even Pin#|Ref Voltage|Signal |NC | | 1 | 2 | | NC @@ -232,7 +233,7 @@ All debug signals share alternate functions as defined for the MIPI20 connector. [#Micror-38 additional pins] .Micror-38 additional pins (comparing to MIPI20 defined above) -[cols = "8%,20%,~", options = header] +[cols = "6%,20%,~", options = header] |================================================================================= |Pin# | Pin Name |Explanation (comparing to MIPI20) | 7 | TRIGIN |Same as MIPI20 #18 alternative pin function but not shared with trace. diff --git a/docs/RISC-V-Trace-Control-Interface.adoc b/docs/RISC-V-Trace-Control-Interface.adoc index 3c28bfb..717cc41 100644 --- a/docs/RISC-V-Trace-Control-Interface.adoc +++ b/docs/RISC-V-Trace-Control-Interface.adoc @@ -2,7 +2,7 @@ :description: RISC-V Trace Control Interface :company: RISC-V.org :revdate: May 23, 2024 -:revnumber: 1.0.0_rc33 +:revnumber: 1.0.0_rc34 :revremark: Stable state (ready for Freeze) :url-riscv: http://riscv.org :doctype: book @@ -52,9 +52,10 @@ Change is extremely unlikely. PDF generated on: {localdatetime} -=== Version 1.0.0_rc33 +=== Version 1.0.0_rc34 * 2024-05-23 ** PDF theme from ISA Manual ADOC. +** Adjusted column widths in tables. ** Only reset values remaining to be changed. [Preface] @@ -197,7 +198,7 @@ Each hart being traced must have its own separate Trace Encoder control componen This specification defines the following trace components (**__N__** in at the end of symbol name denotes 0-based index of particular component) .*Trace Components* -[cols="30%,40%,30%",options="header",] +[cols="20%,40%,40%",options="header",align=center,width=80%] |=== |*Component Name* |*Component Type* (value=symbol)|*Base Address* (symbol #**__N__**) |Trace Encoder |0x1=TRCOMP_ENCODER|trBaseEncoder**__N__** @@ -227,7 +228,7 @@ Different components must be connected via internal busses and/or FIFO buffers. ** Use triggers to create trace windows/ranges to limit amount of trace data - especially in multi-core configurations. .*Allowed Connections Between Components* -[cols="20%,20%,~",options="header",] +[cols="15%,15%,~",options="header"] |=== |*Input* |*Output* |*Description* |Ingress Port|Trace Encoder|Ingress Port (from hart) providing raw trace trace to be encoded @@ -373,7 +374,7 @@ NOTE: Additional control path(s) may also be implemented, such as extra JTAG reg Each block of 32-bit registers (for each component) has the following layout: .*Register Layout for Component* -[cols="10%,25%,15%,~",options="header",] +[cols="15%,23%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x000 |tr??Control |Required |Main control register for this trace component @@ -400,7 +401,7 @@ All other trace components are shared between different trace encoders (N-Trace ==== Summary of Trace Encoder Registers .*Trace Encoder Registers (trTe??, trTs??)* -[cols="10%,25%,15%,~",options="header",] +[cols="15%,23%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x000 |trTeControl |Required |Trace Encoder control register @@ -436,7 +437,7 @@ All other trace components are shared between different trace encoders (N-Trace ==== Summary of Trace RAM Sink Registers .*Trace RAM Sink Registers (trRam??)* -[cols="10%,25%,15%,~",options="header",] +[cols="15%,23%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x000 |trRamControl |Required |RAM Sink control register @@ -457,7 +458,7 @@ All other trace components are shared between different trace encoders (N-Trace ==== Summary of Trace PIB Sink Registers .*Trace PIB Sink Registers (trPib??)* -[cols="10%,25%,15%,~",options="header",] +[cols="15%,23%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x000 |trPibControl |Required |Trace PIB Sink control register @@ -467,7 +468,7 @@ All other trace components are shared between different trace encoders (N-Trace ==== Summary of Trace Funnel Registers .*Trace Funnel Registers (trFunnel??, trTs??)* -[cols="10%,25%,15%,~",options="header",] +[cols="15%,23%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x000 |trFunnelControl |Required |Trace Funnel control register @@ -486,7 +487,7 @@ NOTE: Funnels may optionally be a source of timestamp and/or forward timestamp t ==== Summary of Trace ATB Bridge Registers .*Trace ATB Bridge Registers (trAtbBridge??)* -[cols="10%,25%,15%,~",options="header",] +[cols="15%,23%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x000 |trAtbBridgeControl |Required |Trace ATB Bridge control register @@ -527,7 +528,7 @@ Displayed messages should report component name, component base address and curr Many features of the Trace Encoder (TE for short) are optional. In most cases, optional features are enabled using a WARL (write any, read legal) register field. A debugger can determine if an optional feature is present by writing to the register field and reading back the result. .*Register: trTeControl: Trace Encoder Control Register (trBaseEncoder+0x000)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trTeActive |Primary activate/reset bit for the TE. When 0, the TE may have clocks gated off or be powered @@ -589,7 +590,7 @@ Trace recording/protocol format: + NOTE: Writing to this register while trace is enabled may unintentionally change a value of `trTeInstTracing` bit because that bit may dynamically change by triggers. .*Register: trTeImpl: Trace Encoder Implementation Register (trBaseEncoder+0x004)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trTeVerMajor |Trace Encoder Component Major Version. Value 1 means the component is compliant with this document. Value 0 means pre-ratified/initial version - see 'Pre-ratified/Initial Interface Version' chapter at the end. |RO| 1 @@ -606,7 +607,7 @@ NOTE: Writing to this register while trace is enabled may unintentionally change NOTE: `trTeProtocol??` fields are separated from `trTeVer??` as we may have the same control interface, but protocol itself may be extended with new packets/ messages/ fields. .*Register: trTeInstFeatures: Trace Instruction Features Register (trBaseEncoder+0x008)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trTeInstNoAddrDiff|When set, trace messages/packets always carry a full address.|WARL|0 @@ -632,7 +633,7 @@ NOTE: `trTeProtocol??` fields are separated from `trTeVer??` as we may have the NOTE: Applicability of different `trTeInst??` fields for each trace encoding protocol is described in a document which defines the protocol (and not all fields are applicable to all protocols). .*Register: trTeInstFilters: Trace Instruction Filters Register (trBaseEncoder+0x00C)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |15:0 |trTeInstFilters | @@ -642,7 +643,7 @@ Determine which filters defined in <> chapter for more details.|RW |0 @@ -736,14 +737,14 @@ Prescale timestamp input clock by 2^(2*trTsPrescale). It will be divided by 1, 4 |=== .*Register: trTsCounterLow: Timestamp Counter Lower Bits (trBaseEncoder/Funnel+0x048)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTsCounterLow |Lower 32 bits of timestamp counter. |RO|0 |=== .*Register: trTsCounterHigh: Timestamp Counter Upper Bits (trBaseEncoder/Funnel+0x04C)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTsCounterHigh |Upper bits of timestamp counter, zero-extended. |RO|0 @@ -756,9 +757,9 @@ Prescale timestamp input clock by 2^(2*trTsPrescale). It will be divided by 1, 4 Debug module triggers are signals from the hart that a trigger was hit, but the action associated with that trigger is a trace-related action. Action identifiers 2-5 are reserved for trace actions in the RISC-V Debug Specification, where triggers are defined. Actions 2-4 are defined by the Efficient Trace for RISC-V (E-Trace) Specification. The desired action is written to the `action` field of the Match Control `mcontrol` CSR (0x7a1). As not all harts may support all trace actions, the debugger should read back the `mcontrol` CSR after setting the desired trace action to verify that the option exists. .*Debug Trigger Actions* -[cols="30%,70%",options="header",align=center] +[cols="30%,~",options="header"] |=== -|*Action (from debug spec)* |*Effect* +|*Trigger Action (from debug spec)* |*Effect* |0 |Breakpoint exception (as defined in RISC-V Debug Specification) |1 |Debug exception (as defined in RISC-V Debug Specification) |2 |*Trace-on action* + @@ -769,13 +770,13 @@ When `trTeInstTrigEnable` = 1 it will stop instruction tracing (`trTeInstTracing When `trTeDataTrigEnable` = 1 it will stop data tracing (`trTeDataTracing` -> 0). |4 |*Trace-notify action* + If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packet with the current PC and, if enabled, a timestamp. -|5 |*Vendor-specific action* (optional) +|5 |*Vendor-specific trace action* (optional) |=== If there are vendor-specific features that require control, the `trTeTrigDbgControl` register is used. .*Register: trTeTrigDbgControl: Debug Trigger Control Register (trBaseEncoder+0x050)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeTrigDbgControl |Vendor-specific trigger setup |WARL|0 @@ -788,7 +789,7 @@ The TE may be configured with up to 8 external trigger inputs for controlling tr External Trigger Outputs may also be present. A trigger out may be generated by trace starting, trace stopping, a watchpoint, or by other system-specific events. .*Register: trTeTrigExtInControl: External Trigger Input Control Register (trBaseEncoder+0x054)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trTeTrigExtInAction0 a| @@ -809,7 +810,7 @@ If tracing is active (`trTeInstTracing` = 1), then the encoder generates a packe |=== .*Register: trTeTrigExtOutControl: External Trigger Output Control Register (trBaseEncoder+0x058)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trTeTrigExtOutEvent0 a| @@ -841,7 +842,7 @@ The registers below divide the filter logic into filters and comparators to prov NOTE: Filter and comparator registers refer to values of some signals (as *priv*, *itype*, *ecause*, *dtype*, *dsize*, ...) available on Trace Ingress Port. See E-Trace specification for details of encoding of these values. .*Register: trTeFilter??: Trace Encoder Filter Registers (trBaseEncoder+0x400..0x5FF)* -[cols="10%,35%,14%,~",options="header",] +[cols="17%,30%,12%,~",options="header"] |=== |*Address Offset* |*Register Name* |*Compliance* |*Description* |0x400 + 0x20*__i__ |trTeFilter__i__Control |Optional |Filter _i_ control @@ -855,8 +856,9 @@ NOTE: Filter and comparator registers refer to values of some signals (as *priv* |=== .*Register: trTeComp??: Trace Encoder Comparator Registers (trBaseEncoder+0x600..0x6FF)* -[cols="10%,35%,14%,~",options="header",] +[cols="17%,30%,12%,~",options="header"] |=== +|*Address Offset* |*Register Name* |*Compliance* |*Description* |0x600 + 0x20*__j__ |trTeComp__j__Control |Optional |Comparator _j_ control |0x604 + 0x20*__j__ |--|Optional |Reserved |0x608 + 0x20*__j__ |--|Optional |Reserved @@ -868,7 +870,7 @@ NOTE: Filter and comparator registers refer to values of some signals (as *priv* |=== .*Register: trTeFilter__i__Control : Filter _i_ Control Register (trBaseEncoder+0x400 + 0x20__i__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trTeFilterEnable | Overall filter enable for filter #__i__|WARL|0 @@ -916,7 +918,7 @@ When set, match *dsize* values as specified by `trTeFilterMatchChoiceDsize` fiel |=== .*Register: trTeFilter__i__MatchInst : Filter _i_ Instruction Match Control Register (trBaseEncoder+0x404 + 0x20__i__)* -[cols="7%,38%,~,8%,8%",options="header",] +[cols="6%,30%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |7:0 |trTeFilterMatchChoicePrivilege | @@ -931,7 +933,7 @@ respectively. |=== .*Register: trTeFilter__i__MatchEcauseLow : Filter _i_ Ecause Match Control (low) Register (trBaseEncoder+0x408 + 0x20__i__)* -[cols="7%,38%,~,8%,8%",options="header",] +[cols="6%,30%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeFilterMatchChoiceEcauseLow | @@ -940,7 +942,7 @@ When `trTeFilterMatchEcause` field for filter #__i__ is set, match all excepion |=== .*Register: trTeFilter__i__MatchEcauseHigh : Filter _i_ Ecause Match Control (high) Register (trBaseEncoder+0x40C + 0x20__i__)* -[cols="7%,38%,~,8%,8%",options="header",] +[cols="6%,30%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeFilterMatchChoiceEcauseHigh | This register stores bits 63:32 to allow matching of higher *ecause* codes. If bit N is 1, then match if the *ecause* is N+32. @@ -948,7 +950,7 @@ When `trTeFilterMatchEcause` field for filter #__i__ is set, match all excepion |=== .*Register: trTeFilter__i__MatchValueImpdef : Filter _i_ Impdef Match Value Register (trBaseEncoder+0x410 + 0x20__i__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeFilterMatchValueImpdef | @@ -959,7 +961,7 @@ When `trTeFilterMatchimpdef` field for filter #__i__ is set, match if |=== .*Register: trTeFilter__i__MatchMaskImpdef : Filter _i_ Impdef Match Mask Register (trBaseEncoder+0x414 + 0x20__i__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeFilterMatchMaskImpdef | @@ -970,7 +972,7 @@ When `trTeFilterMatchimpdef` field for filter #__i__ is set, match if |=== .*Register: trTeFilter__i__MatchData : Filter _i_ Data Match Control Register (trBaseEncoder+0x418 + 0x20__i__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |15:0 |trTeFilterMatchChoiceDtype | @@ -985,7 +987,7 @@ for which the corresponding bit is set. For example, if bit N is 1, then match i |=== .*Register: trTeComp__j__Control : Comparator _j_ Control Register (trBaseEncoder+0x600 + 0x20__j__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |1:0 |trTeCompPInput | @@ -1045,7 +1047,7 @@ Requires `trTeCompSInput` to be 0, and has no effect otherwise. IMPORTANT: Comparisions are performed as unsigned numbers. Only bits from an input signal (as defined by `trTeCompPInput` and/or `trTeCompSInput` fields), should be compared. Additional most significant bits from the `trTeComp__j__PMatchLow/High` registers must be ignored. .*Register: trTeComp__j__PMatchLow : Comparator _j_ Primary match (low) Register (trBaseEncoder+0x610 + 0x20__j__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeCompPMatchLow | @@ -1054,7 +1056,7 @@ The match value for the primary comparator (bits 31:0). |=== .*Register: trTeComp__j__PMatchHigh : Comparator _j_ Primary match (high) Register (trBaseEncoder+0x614 + 0x20__j__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeCompPMatchHigh | @@ -1063,7 +1065,7 @@ The match value for the primary comparator (bits 63:32). |=== .*Register: trTeComp__j__SMatchLow : Comparator _j_ Secondary match (low) Register (trBaseEncoder+0x618 + 0x20__j__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeCompSMatchLow | @@ -1072,7 +1074,7 @@ The match value for the secondary comparator (bits 31:0). |=== .*Register: trTeComp__j__SMatchHigh : Comparator _j_ Secondary match (high) Register (trBaseEncoder+0x61C + 0x20__j__)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trTeCompSMatchHigh | @@ -1089,7 +1091,7 @@ Trace data is placed in memory in LSB order (first byte of trace packet/data is Be aware that in case trace memory wraps around some protocols may require additional synchronization data - it is usually done by periodically generating a sequence of alignment synchronization bytes which cannot be part of any valid packet. Specification of each trace protocol must define it. .*Register: trRamControl: Trace RAM Sink Control Register (trBaseRam+0x000)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trRamActive |Primary activate/reset bit for Trace RAM Sink. When 0, the Trace RAM Sink may have clocks gated off or be powered @@ -1118,7 +1120,7 @@ Details should be defined in definition of each trace protocol. |=== .*Register: trRamImpl: Trace RAM Sink Implementation Register (trBaseRamSink+0x004)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trRamVerMajor |Trace RAM Sink Component Major Version. Value 1 means the component is compliant with this document. |RO|1 @@ -1133,7 +1135,7 @@ Details should be defined in definition of each trace protocol. NOTE: Single RAM Sink may support both SRAM and SMEM modes, but not both of them may be enabled at the same time. It is also possible to have more than one RAM Sink in a system. .*Register: trRamStartLow: Trace RAM Sink Start Register (trBaseRamSink+0x010)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |1:0 |--|Always 0 (two LSB of 32-bit address)|RO|0 @@ -1143,14 +1145,14 @@ NOTE: Single RAM Sink may support both SRAM and SMEM modes, but not both of them For a bus with an address larger than 32-bit, corresponding `High` registers define the MSB part of such a larger address. .*Register: trRamStartHigh: Trace RAM Sink Start High Bits Register (trBaseRamSink+0x014)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trRamStartHigh |High order bits (63:32) of `trRamStart` register. |WARL|Undef |=== .*Register: trRamLimitLow: Trace RAM Sink Limit Register (trBaseRamSink+0x018)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |1:0 |--|Always 0 (two LSB of 32-bit address)|RO|0 @@ -1158,14 +1160,14 @@ For a bus with an address larger than 32-bit, corresponding `High` registers def |=== .*Register: trRamLimitHigh: Trace RAM Sink Limit High Bits Register (trBaseRamSink+0x01C)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trRamLimitHigh |High order bits (63:32) of `trRamLimit` register. |WARL|Undef |=== .*Register: trRamWPLow: Trace RAM Sink Write Pointer Register (trBaseRamSink+0x020)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trRamWrap |Set to 1 by hardware when `trRamWP` wraps. It is only set to 0 if `trRamWPLow` is written|WARL|0 @@ -1174,14 +1176,14 @@ For a bus with an address larger than 32-bit, corresponding `High` registers def |=== .*Register: trRamWPHigh: Trace RAM Sink Write Pointer High Bits Register (trBaseRamSink+0x024)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trRamWPHigh |High order bits (63:32) of `trRamWP` register.|WARL|Undef |=== .*Register: trRamRPLow: Trace RAM Sink Read Pointer Register (trBaseRamSink+0x028)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |1:0 |--|Always 0 (two LSB of 32-bit address)|RO|0 @@ -1189,14 +1191,14 @@ For a bus with an address larger than 32-bit, corresponding `High` registers def |=== .*Register: trRamRPHigh: Trace RAM Sink Read Pointer High Bits Register (trBaseRamSink+0x02C)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trRamRPHigh |High order bits (63:32) of `trRamRP` register.|WARL|Undef |=== .*Register: trRamData: Trace RAM Sink Data Register (trBaseRamSink+0x040)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |31:0 |trRamData |Read (and optional write) value for trace sink memory access. SRAM is always accessed by 32-bit words through this path regardless of the actual width of the sink memory. Required for SRAM mode and optional for SMEM mode. |R or RW |Undef @@ -1207,7 +1209,7 @@ NOTE: When trace capture was wrapped around (`trRamWrap` = 1) beginning of trace Table below shows typical Trace RAM Sink configurations. Implementing other configurations is not suggested as trace tools may not support it without adjustments. .*Typical Trace RAM Sink Configurations* -[cols="10%,15%,30%,15%,15%,15%",options="header",] +[cols="8%,18%,~,12%,15%,15%",options="header"] |=== |*Mode* |*trRamStart* |*trRamLimit* |*trRamWP* |*trRamRP* |*trRamData* |SRAM |0 |Hard coded to max size (2^M - A) at reset, but can be possibly trimmed|Required |Required |Required @@ -1254,7 +1256,7 @@ NOTE: Trace RAM Sink may implement writing trace by writing to `trRamData`, but The Trace Funnel combines messages/packets from multiple sources into a single trace stream. It is implementation-dependent how many incoming messages/packets are accepted before it is switching to another input source and in what order. But a continuous stream of messages/packets at one input cannot cause other inputs to not be handled. Suggested implementation would be to process just a single message/packet from each input in a round-robin fashion. .*Register: trFunnelControl: Trace Funnel Control Register (trBaseFunnel+0x000)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trFunnelActive |Primary activate/reset bit for trace funnel. When 0, the Trace Funnel may have clocks gated off or be powered @@ -1266,7 +1268,7 @@ down, and other register locations may be inaccessible. Hardware may take an arb |=== .*Register: trFunnelImpl: Trace Funnel Implementation Register (trBaseFunnel+0x004)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trFunnelVerMajor |Trace Funnel Component Major Version. Value 1 means the component is compliant with this document. |RO|1 @@ -1277,7 +1279,7 @@ down, and other register locations may be inaccessible. Hardware may take an arb |=== .*Register: trFunnelDisInput: Disable Individual Funnel Inputs (trBaseFunnel+0x008)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |15:0 |trFunnelDisInput |*1:* Funnel input *#n* (bit position in register) is disabled. Incoming messages are read from diabled input but discarded.|WARL|0 @@ -1299,7 +1301,7 @@ The modes and behavior described here are intended to be compatible with trace p *PIB Register Interface* .*Register: trPibControl: PIB Sink Control Register (trBasePib+0x000)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trPibActive |Primary activate/reset bit for PIB Sink component. When 0, the PIB Sink may have clocks gated off or be powered @@ -1327,7 +1329,7 @@ After the PIB reset value of this field should be set to safe (not too fast cloc |=== .*Register: trPibImpl: Trace PIB Implementation Register (trBasePib+0x004)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trPibVerMajor |Trace PIB Sink Component Major Version. Value 1 means the component is compliant with this document. |RO|1 @@ -1340,7 +1342,7 @@ After the PIB reset value of this field should be set to safe (not too fast cloc Software can determine what modes are available by attempting to write each mode setting to the WARL field `trPibMode` and reading back to see if the value was accepted. .*Allowed PIB Configurations* -[cols="40%,20%,23%,17%",options="header",align=center,width=80%] +[cols="40%,20%,23%,17%",options="header",align=center,width=60%] |=== |*Mode* |*trPibMode* |*trPibClkCenter* |*Bit rate* |Off |0 |X |-- @@ -1398,7 +1400,7 @@ image:./RISC-V-Trace-Control-Interface-images/pib-ref1.png[image] In optional calibration mode, the PIB transmits a repeating pattern. Probes can use this to automatically tune input delays due to skew on different PIB signal lines and to adjust to the transmitter's data rate (`trPibDivider` and `trPibClkCenter`). Calibration patterns for each mode are listed below. .*PIB Calibration Patterns* -[cols="25%,30%,~",options="header",align=center,width=95%] +[cols="25%,30%,~",options="header",align=center,width=80%] |=== |*Mode* |*Calibration Bytes* |*Wire Sequence* |UART, Manchester |AA 55 00 FF |alternating 1/0, then all 0, then all 1 @@ -1416,7 +1418,7 @@ NOTE: Calibration mode may be used even by probes which do not support calibrati In this mode, the PIB outputs complete trace messages encapsulated between a start bit and a stop bit. Each bit period is divided into 2 phases and the sequential values of the TRC_DATA[0] pin during those 2 phases denote the bit value. Bits of the message are transmitted LSB first. The idle state of TRC_DATA[0] is low in this mode. .*Manchester Encoding Patterns* -[cols="~,~,~",options="header",align=center,width=40%] +[cols="~,~,~",options="header",align=center,width=30%] |=== |*Bit* |*Phase 1* |*Phase 2* |start |1 |0 @@ -1438,7 +1440,7 @@ image:./RISC-V-Trace-Control-Interface-images/swt-uart.jpg[image] Some SoCs may have an Advanced Trace Bus (ATB) infrastructure to manage trace produced by other components. In such systems, it may be desired to route entire RISC-V trace stream to the ATB through an ATB Bridge. This module manages the interface to ATB, generating ATB trace records that encapsulate RISC-V trace produced by the Trace Encoder[s] and/or Trace Funnel[s]. There is a control register that includes trace on/off control and a field allowing software to set the ID to be used on the ATB bus. This ID allows software to extract entire RISC-V trace from the combined trace. This interface is compatible with AMBA 4 ATB v1.1. .*Register: trAtbBridgeControl: ATB Bridge Control Register (trAtbBridgeBase+0x000)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |0 |trAtbBridgeActive |Primary activate/reset for the ATB Bridge. When 0, the ATB Bridge may have clocks gated off or be powered @@ -1452,7 +1454,7 @@ down, and other register locations may be inaccessible. Hardware may take an arb |=== .*Register: trAtbBridgeImpl: ATB Bridge Implementation Register (trAtbBridgeBase+0x004)* -[cols="7%,30%,~,8%,8%",options="header",] +[cols="6%,24%,~,7%,7%",options="header"] |=== |*Bit* |*Field* |*Description* |*RW* |*Reset* |3:0 |trAtbBridgeVerMajor |ATB Bridge Component Major Version. Value 1 means the component is compliant with this document. |RO|1