SAIL implementation of CLIC

[dansmathers]

SAIL implementation needed for Definition of Done. Creating an issue for tracking purposes.

[dansmathers]

Replace pseudo-code in spec with SAIL code once SAIL code is implemented?

[dansmathers]

FYI, smrnmi may be a good reference for how to implement clic in SAIL
riscv/sail-riscv#396

[dansmathers]

another reference is an attempt at plic: https://github.com/saravanakumarsastra/sail-riscv

[dansmathers]

if CLIC changes from mem-mapped clicint registers to using indirect csrs: https://github.com/adlr/sail-riscv/tree/smcsrindpr

[dansmathers]

Initial sail-riscv clic implementation. Moving issue to post 1.0 - ecosystem phase as we work to get the pull approved.

riscv/sail-riscv#420
Tested against Tests: riscv-non-isa/riscv-arch-test#436

Note: pulls are not yet available for spike that support CLIC

Related pulls to run arch-tests against the sail-riscv model:
riscv-software-src/riscv-config#169
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include m-mode CLIC interrupt tests in riscof testlist flow, add Smclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
ISA: RV32IMCZicsr_Zifencei_Smclic