diff --git a/constants.py b/constants.py
index 3451ade8..dc76ba38 100644
--- a/constants.py
+++ b/constants.py
@@ -157,11 +157,8 @@
     'rstsa16',
     'rstsa32',
     'srli32_u',
-    'slli_rv128',
     'slli_rv32',
-    'srai_rv128',
     'srai_rv32',
-    'srli_rv128',
     'srli_rv32',
     'umax32',
     'c_mop_1',
diff --git a/parse.py b/parse.py
index 1c41d9c0..98e06a6e 100755
--- a/parse.py
+++ b/parse.py
@@ -756,9 +756,7 @@ def make_chisel(instr_dict, spinal_hdl=False):
         extensions = instr_dict_2_extensions(instr_dict)
         for e in extensions:
             e_instrs = filter(lambda i: instr_dict[i]['extension'][0] == e, instr_dict)
-            if "rv128_" in e:
-                e_format = e.replace("rv128_", "").upper() + "128"
-            elif "rv64_" in e:
+            if "rv64_" in e:
                 e_format = e.replace("rv64_", "").upper() + "64"
             elif "rv32_" in e:
                 e_format = e.replace("rv32_", "").upper() + "32"
diff --git a/unratified/rv128_c b/unratified/rv128_c
deleted file mode 100644
index 79cd5325..00000000
--- a/unratified/rv128_c
+++ /dev/null
@@ -1,14 +0,0 @@
-# quadrant 0
-c.lq rd_p rs1_p c_uimm9lo c_uimm9hi     1..0=0 15..13=1 
-$import rv64_c::c.ld
-c.sq rs1_p rs2_p c_uimm9hi c_uimm9lo    1..0=0 15..13=5
-$import rv64_c::c.sd
-
-#quadrant 1
-$import rv64_c::c.addiw
-
-#quadrant 2
-c.lqsp rd_n0 c_uimm10sphi c_uimm10splo  1..0=2 15..13=1
-$import rv64_c::c.ldsp
-c.sqsp c_rs2 c_uimm10sp_s               1..0=2 15..13=5
-$import rv64_c::c.sdsp
diff --git a/unratified/rv128_i b/unratified/rv128_i
deleted file mode 100644
index bb2c10b4..00000000
--- a/unratified/rv128_i
+++ /dev/null
@@ -1,24 +0,0 @@
-# RV128I additions to RV64I
-
-addid   rd rs1 imm12            14..12=0 6..2=0x16 1..0=3
-sllid   rd rs1 31..26=0  shamtd 14..12=1 6..2=0x16 1..0=3
-srlid   rd rs1 31..26=0  shamtd 14..12=5 6..2=0x16 1..0=3
-sraid   rd rs1 31..26=16 shamtd 14..12=5 6..2=0x16 1..0=3
-
-addd    rd rs1 rs2 31..25=0  14..12=0 6..2=0x1E 1..0=3
-subd    rd rs1 rs2 31..25=32 14..12=0 6..2=0x1E 1..0=3
-slld    rd rs1 rs2 31..25=0  14..12=1 6..2=0x1E 1..0=3
-srld    rd rs1 rs2 31..25=0  14..12=5 6..2=0x1E 1..0=3
-srad    rd rs1 rs2 31..25=32 14..12=5 6..2=0x1E 1..0=3
-
-lq      rd rs1       imm12 14..12=3 6..2=0x03 1..0=3
-ldu     rd rs1       imm12 14..12=7 6..2=0x00 1..0=3
-
-sq     imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3
-
-$pseudo_op rv64_i::slli slli    rd rs1 31..27=0  shamtq 14..12=1 6..2=0x04 1..0=3
-$pseudo_op rv64_i::srli srli    rd rs1 31..27=0  shamtq 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_i::srai srai    rd rs1 31..27=8  shamtq 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_i::slli slli_rv128 rd rs1 31..27=0  shamtq 14..12=1 6..2=0x04 1..0=3
-$pseudo_op rv64_i::srli srli_rv128 rd rs1 31..27=0  shamtq 14..12=5 6..2=0x04 1..0=3
-$pseudo_op rv64_i::srai srai_rv128 rd rs1 31..27=8  shamtq 14..12=5 6..2=0x04 1..0=3