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The following will simplify shifter logic (and also allow to merge SIMD and regular shifters easier):
In imm shifts (as kslli8) let chunk[25:20+len(imm)] bits be 0;
In reg shifts (as ksll8) if val(rs2) is not in shift range, result is implementation defined.
KSLRA's input should be properly sign extended; no exceptions like sa = (sa == 8)? 7 : sa;.
This will be somehow similar to C/C++ standards where int64_t >> 64 is an UB.
The text was updated successfully, but these errors were encountered:
The following will simplify shifter logic (and also allow to merge SIMD and regular shifters easier):
kslli8
) letchunk[25:20+len(imm)]
bits be 0;ksll8
) if val(rs2) is not in shift range, result is implementation defined.KSLRA's input should be properly sign extended; no exceptions like
sa = (sa == 8)? 7 : sa;
.This will be somehow similar to C/C++ standards where
int64_t >> 64
is an UB.The text was updated successfully, but these errors were encountered: