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where Rs1 is an even register, Rs3 is an even+1 register, and Rs2[5] == 0.
In here, ensuring that Rs2[5] == 0 is the problem. We might assume that following expansion works:
# wext rd, rs1, rs2
andi rd, rs2, 0x1f # bit 5 (and upper bits) is set to zero
fsr rd, rs1, (rs1+1), rd
Wrong. If rd is either rs1 or (rs1+1), the result will be most likely incorrect. And former WEXT instruction did not prohibit such register overlap.
We must allocate an independent temporary register for this reason but this is a great pain for toolchains ... at least for GNU Binutils.
So, I propose to make some changes so that the alias WEXT is not what toolchain (specifically, assembler) developers should implement. Removing this alias (or aliases including WEXTI) is an option (though WEXTI alias is not harmful itself).
To note, as a porting guide from former WEXT to recent FSR, this text is not only correct but acceptable. But as an assembler alias, it's not.
The text was updated successfully, but these errors were encountered:
Quoting 6.3. FSR, FSRI (version 0.9.11),
In here, ensuring that
Rs2[5] == 0
is the problem. We might assume that following expansion works:Wrong. If
rd
is eitherrs1
or(rs1+1)
, the result will be most likely incorrect. And formerWEXT
instruction did not prohibit such register overlap.We must allocate an independent temporary register for this reason but this is a great pain for toolchains ... at least for GNU Binutils.
So, I propose to make some changes so that the alias
WEXT
is not what toolchain (specifically, assembler) developers should implement. Removing this alias (or aliases includingWEXTI
) is an option (thoughWEXTI
alias is not harmful itself).To note, as a porting guide from former
WEXT
to recentFSR
, this text is not only correct but acceptable. But as an assembler alias, it's not.The text was updated successfully, but these errors were encountered: