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Add mstatus.VS setting code for vector extension
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@XinlaiWan
XinlaiWan committed Sep 19, 2023
1 parent d3ef092 commit 057890d
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Showing 17 changed files with 225 additions and 204 deletions.
4 changes: 2 additions & 2 deletions c_emulator/riscv_platform.c
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Expand Up @@ -37,9 +37,9 @@ bool sys_enable_zfinx(unit u)
return rv_enable_zfinx;
}

bool sys_enable_rvv(unit u)
bool sys_enable_vext(unit u)
{
return rv_enable_rvv;
return rv_enable_vext;
}

bool sys_enable_writable_misa(unit u)
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2 changes: 1 addition & 1 deletion c_emulator/riscv_platform.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ bool sys_enable_next(unit);
bool sys_enable_fdext(unit);
bool sys_enable_zfinx(unit);
bool sys_enable_writable_misa(unit);
bool sys_enable_rvv(unit);
bool sys_enable_vext(unit);

bool plat_enable_dirty_update(unit);
bool plat_enable_misaligned_access(unit);
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2 changes: 1 addition & 1 deletion c_emulator/riscv_platform_impl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ bool rv_enable_rvc = true;
bool rv_enable_next = false;
bool rv_enable_writable_misa = true;
bool rv_enable_fdext = true;
bool rv_enable_rvv = true;
bool rv_enable_vext = true;

bool rv_enable_dirty_update = false;
bool rv_enable_misaligned = false;
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2 changes: 1 addition & 1 deletion c_emulator/riscv_platform_impl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ extern bool rv_enable_zfinx;
extern bool rv_enable_rvc;
extern bool rv_enable_next;
extern bool rv_enable_fdext;
extern bool rv_enable_rvv;
extern bool rv_enable_vext;
extern bool rv_enable_writable_misa;
extern bool rv_enable_dirty_update;
extern bool rv_enable_misaligned;
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2 changes: 1 addition & 1 deletion c_emulator/riscv_sim.c
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Original file line number Diff line number Diff line change
Expand Up @@ -288,7 +288,7 @@ char *process_args(int argc, char **argv)
break;
case 'W':
fprintf(stderr, "disabling RVV vector instructions.\n");
rv_enable_rvv = false;
rv_enable_vext = false;
break;
case 'i':
fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n");
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136 changes: 68 additions & 68 deletions model/riscv_insts_vext_arith.sail
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72 changes: 36 additions & 36 deletions model/riscv_insts_vext_fp.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -57,8 +57,8 @@ mapping encdec_fvvfunct6 : fvvfunct6 <-> bits(6) = {
FVV_VMUL <-> 0b100100
}

mapping clause encdec = FVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV()
<-> encdec_fvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()
<-> encdec_fvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(FVVTYPE(funct6, vm, vs2, vs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -132,8 +132,8 @@ mapping encdec_fvvmafunct6 : fvvmafunct6 <-> bits(6) = {
FVV_VNMSAC <-> 0b101111
}

mapping clause encdec = FVVMATYPE(funct6, vm, vs2, vs1, vd) if haveRVV()
<-> encdec_fvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FVVMATYPE(funct6, vm, vs2, vs1, vd) if haveVExt()
<-> encdec_fvvmafunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(FVVMATYPE(funct6, vm, vs2, vs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -199,8 +199,8 @@ mapping encdec_fwvvfunct6 : fwvvfunct6 <-> bits(6) = {
FWVV_VMUL <-> 0b111000
}

mapping clause encdec = FWVVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV()
<-> encdec_fwvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FWVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()
<-> encdec_fwvvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(FWVVTYPE(funct6, vm, vs2, vs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -264,8 +264,8 @@ mapping encdec_fwvvmafunct6 : fwvvmafunct6 <-> bits(6) = {
FWVV_VNMSAC <-> 0b111111
}

mapping clause encdec = FWVVMATYPE(funct6, vm, vs1, vs2, vd) if haveRVV()
<-> encdec_fwvvmafunct6(funct6) @ vm @ vs1 @ vs2 @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FWVVMATYPE(funct6, vm, vs1, vs2, vd) if haveVExt()
<-> encdec_fwvvmafunct6(funct6) @ vm @ vs1 @ vs2 @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(FWVVMATYPE(funct6, vm, vs1, vs2, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -328,8 +328,8 @@ mapping encdec_fwvfunct6 : fwvfunct6 <-> bits(6) = {
FWV_VSUB <-> 0b110110
}

mapping clause encdec = FWVTYPE(funct6, vm, vs2, vs1, vd) if haveRVV()
<-> encdec_fwvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FWVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt()
<-> encdec_fwvfunct6(funct6) @ vm @ vs2 @ vs1 @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(FWVTYPE(funct6, vm, vs2, vs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -391,8 +391,8 @@ mapping encdec_vfunary0_vs1 : vfunary0 <-> bits(5) = {
FV_CVT_RTZ_X_F <-> 0b00111
}

mapping clause encdec = VFUNARY0(vm, vs2, vfunary0, vd) if haveRVV()
<-> 0b010010 @ vm @ vs2 @ encdec_vfunary0_vs1(vfunary0) @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFUNARY0(vm, vs2, vfunary0, vd) if haveVExt()
<-> 0b010010 @ vm @ vs2 @ encdec_vfunary0_vs1(vfunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -504,8 +504,8 @@ mapping encdec_vfwunary0_vs1 : vfwunary0 <-> bits(5) = {
FWV_CVT_RTZ_X_F <-> 0b01111
}

mapping clause encdec = VFWUNARY0(vm, vs2, vfwunary0, vd) if haveRVV()
<-> 0b010010 @ vm @ vs2 @ encdec_vfwunary0_vs1(vfwunary0) @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFWUNARY0(vm, vs2, vfwunary0, vd) if haveVExt()
<-> 0b010010 @ vm @ vs2 @ encdec_vfwunary0_vs1(vfwunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFWUNARY0(vm, vs2, vfwunary0, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -634,8 +634,8 @@ mapping encdec_vfnunary0_vs1 : vfnunary0 <-> bits(5) = {
FNV_CVT_RTZ_X_F <-> 0b10111
}

mapping clause encdec = VFNUNARY0(vm, vs2, vfnunary0, vd) if haveRVV()
<-> 0b010010 @ vm @ vs2 @ encdec_vfnunary0_vs1(vfnunary0) @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFNUNARY0(vm, vs2, vfnunary0, vd) if haveVExt()
<-> 0b010010 @ vm @ vs2 @ encdec_vfnunary0_vs1(vfnunary0) @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -769,8 +769,8 @@ mapping encdec_vfunary1_vs1 : vfunary1 <-> bits(5) = {
FVV_VCLASS <-> 0b10000
}

mapping clause encdec = VFUNARY1(vm, vs2, vfunary1, vd) if haveRVV()
<-> 0b010011 @ vm @ vs2 @ encdec_vfunary1_vs1(vfunary1) @ 0b001 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFUNARY1(vm, vs2, vfunary1, vd) if haveVExt()
<-> 0b010011 @ vm @ vs2 @ encdec_vfunary1_vs1(vfunary1) @ 0b001 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFUNARY1(vm, vs2, vfunary1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -845,8 +845,8 @@ mapping clause assembly = VFUNARY1(vm, vs2, vfunary1, vd)
/* ****************************** OPFVV (VWFUNARY0) ****************************** */
union clause ast = VFMVFS : (regidx, regidx)

mapping clause encdec = VFMVFS(vs2, rd) if haveRVV()
<-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b001 @ rd @ 0b1010111 if haveRVV()
mapping clause encdec = VFMVFS(vs2, rd) if haveVExt()
<-> 0b010000 @ 0b1 @ vs2 @ 0b00000 @ 0b001 @ rd @ 0b1010111 if haveVExt()

function clause execute(VFMVFS(vs2, rd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -893,8 +893,8 @@ mapping encdec_fvffunct6 : fvffunct6 <-> bits(6) = {
VF_VRSUB <-> 0b100111
}

mapping clause encdec = FVFTYPE(funct6, vm, vs2, rs1, vd) if haveRVV()
<-> encdec_fvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FVFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()
<-> encdec_fvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(FVFTYPE(funct6, vm, vs2, rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -983,8 +983,8 @@ mapping encdec_fvfmafunct6 : fvfmafunct6 <-> bits(6) = {
VF_VNMSAC <-> 0b101111
}

mapping clause encdec = FVFMATYPE(funct6, vm, vs2, rs1, vd) if haveRVV()
<-> encdec_fvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FVFMATYPE(funct6, vm, vs2, rs1, vd) if haveVExt()
<-> encdec_fvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(FVFMATYPE(funct6, vm, vs2, rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -1050,8 +1050,8 @@ mapping encdec_fwvffunct6 : fwvffunct6 <-> bits(6) = {
FWVF_VMUL <-> 0b111000
}

mapping clause encdec = FWVFTYPE(funct6, vm, vs2, rs1, vd) if haveRVV()
<-> encdec_fwvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FWVFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()
<-> encdec_fwvffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(FWVFTYPE(funct6, vm, vs2, rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -1114,8 +1114,8 @@ mapping encdec_fwvfmafunct6 : fwvfmafunct6 <-> bits(6) = {
FWVF_VNMSAC <-> 0b111111
}

mapping clause encdec = FWVFMATYPE(funct6, vm, rs1, vs2, vd) if haveRVV()
<-> encdec_fwvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FWVFMATYPE(funct6, vm, rs1, vs2, vd) if haveVExt()
<-> encdec_fwvfmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(FWVFMATYPE(funct6, vm, rs1, vs2, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -1177,8 +1177,8 @@ mapping encdec_fwffunct6 : fwffunct6 <-> bits(6) = {
FWF_VSUB <-> 0b110110
}

mapping clause encdec = FWFTYPE(funct6, vm, vs2, rs1, vd) if haveRVV()
<-> encdec_fwffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = FWFTYPE(funct6, vm, vs2, rs1, vd) if haveVExt()
<-> encdec_fwffunct6(funct6) @ vm @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(FWFTYPE(funct6, vm, vs2, rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -1231,8 +1231,8 @@ mapping clause assembly = FWFTYPE(funct6, vm, vs2, rs1, vd)
/* This instruction operates on all body elements regardless of mask value */
union clause ast = VFMERGE : (regidx, regidx, regidx)

mapping clause encdec = VFMERGE(vs2, rs1, vd) if haveRVV()
<-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFMERGE(vs2, rs1, vd) if haveVExt()
<-> 0b010111 @ 0b0 @ vs2 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFMERGE(vs2, rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -1282,8 +1282,8 @@ mapping clause assembly = VFMERGE(vs2, rs1, vd)
/* This instruction shares the encoding with vfmerge.vfm, but with vm=1 and vs2=v0 */
union clause ast = VFMV : (regidx, regidx)

mapping clause encdec = VFMV(rs1, vd) if haveRVV()
<-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFMV(rs1, vd) if haveVExt()
<-> 0b010111 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFMV(rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down Expand Up @@ -1320,8 +1320,8 @@ mapping clause assembly = VFMV(rs1, vd)
/* ****************************** OPFVF (VRFUNARY0) ****************************** */
union clause ast = VFMVSF : (regidx, regidx)

mapping clause encdec = VFMVSF(rs1, vd) if haveRVV()
<-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VFMVSF(rs1, vd) if haveVExt()
<-> 0b010000 @ 0b1 @ 0b00000 @ rs1 @ 0b101 @ vd @ 0b1010111 if haveVExt()

function clause execute(VFMVSF(rs1, vd)) = {
let rm_3b = fcsr.FRM();
Expand Down
32 changes: 16 additions & 16 deletions model/riscv_insts_vext_mask.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -55,8 +55,8 @@ mapping encdec_mmfunct6 : mmfunct6 <-> bits(6) = {
MM_VMXNOR <-> 0b011111
}

mapping clause encdec = MMTYPE(funct6, vs2, vs1, vd) if haveRVV()
<-> encdec_mmfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = MMTYPE(funct6, vs2, vs1, vd) if haveVExt()
<-> encdec_mmfunct6(funct6) @ 0b1 @ vs2 @ vs1 @ 0b010 @ vd @ 0b1010111 if haveVExt()

function clause execute(MMTYPE(funct6, vs2, vs1, vd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -113,8 +113,8 @@ mapping clause assembly = MMTYPE(funct6, vs2, vs1, vd)
/* ************************* OPMVV (vpopc in VWXUNARY0) ************************** */
union clause ast = VCPOP_M : (bits(1), regidx, regidx)

mapping clause encdec = VCPOP_M(vm, vs2, rd) if haveRVV()
<-> 0b010000 @ vm @ vs2 @ 0b10000 @ 0b010 @ rd @ 0b1010111 if haveRVV()
mapping clause encdec = VCPOP_M(vm, vs2, rd) if haveVExt()
<-> 0b010000 @ vm @ vs2 @ 0b10000 @ 0b010 @ rd @ 0b1010111 if haveVExt()

function clause execute(VCPOP_M(vm, vs2, rd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -149,8 +149,8 @@ mapping clause assembly = VCPOP_M(vm, vs2, rd)
/* ************************* OPMVV (vfirst in VWXUNARY0) ************************* */
union clause ast = VFIRST_M : (bits(1), regidx, regidx)

mapping clause encdec = VFIRST_M(vm, vs2, rd) if haveRVV()
<-> 0b010000 @ vm @ vs2 @ 0b10001 @ 0b010 @ rd @ 0b1010111 if haveRVV()
mapping clause encdec = VFIRST_M(vm, vs2, rd) if haveVExt()
<-> 0b010000 @ vm @ vs2 @ 0b10001 @ 0b010 @ rd @ 0b1010111 if haveVExt()

function clause execute(VFIRST_M(vm, vs2, rd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -187,8 +187,8 @@ mapping clause assembly = VFIRST_M(vm, vs2, rd)
/* ************************** OPMVV (vmsbf in VMUNARY0) ************************** */
union clause ast = VMSBF_M : (bits(1), regidx, regidx)

mapping clause encdec = VMSBF_M(vm, vs2, vd) if haveRVV()
<-> 0b010100 @ vm @ vs2 @ 0b00001 @ 0b010 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VMSBF_M(vm, vs2, vd) if haveVExt()
<-> 0b010100 @ vm @ vs2 @ 0b00001 @ 0b010 @ vd @ 0b1010111 if haveVExt()

function clause execute(VMSBF_M(vm, vs2, vd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -228,8 +228,8 @@ mapping clause assembly = VMSBF_M(vm, vs2, vd)
/* ************************** OPMVV (vmsif in VMUNARY0) ************************** */
union clause ast = VMSIF_M : (bits(1), regidx, regidx)

mapping clause encdec = VMSIF_M(vm, vs2, vd) if haveRVV()
<-> 0b010100 @ vm @ vs2 @ 0b00011 @ 0b010 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VMSIF_M(vm, vs2, vd) if haveVExt()
<-> 0b010100 @ vm @ vs2 @ 0b00011 @ 0b010 @ vd @ 0b1010111 if haveVExt()

function clause execute(VMSIF_M(vm, vs2, vd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -269,8 +269,8 @@ mapping clause assembly = VMSIF_M(vm, vs2, vd)
/* ************************** OPMVV (vmsof in VMUNARY0) ************************** */
union clause ast = VMSOF_M : (bits(1), regidx, regidx)

mapping clause encdec = VMSOF_M(vm, vs2, vd) if haveRVV()
<-> 0b010100 @ vm @ vs2 @ 0b00010 @ 0b010 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VMSOF_M(vm, vs2, vd) if haveVExt()
<-> 0b010100 @ vm @ vs2 @ 0b00010 @ 0b010 @ vd @ 0b1010111 if haveVExt()

function clause execute(VMSOF_M(vm, vs2, vd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -314,8 +314,8 @@ mapping clause assembly = VMSOF_M(vm, vs2, vd)
/* ************************** OPMVV (viota in VMUNARY0) ************************** */
union clause ast = VIOTA_M : (bits(1), regidx, regidx)

mapping clause encdec = VIOTA_M(vm, vs2, vd) if haveRVV()
<-> 0b010100 @ vm @ vs2 @ 0b10000 @ 0b010 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VIOTA_M(vm, vs2, vd) if haveVExt()
<-> 0b010100 @ vm @ vs2 @ 0b10000 @ 0b010 @ vd @ 0b1010111 if haveVExt()

function clause execute(VIOTA_M(vm, vs2, vd)) = {
let SEW = get_sew();
Expand Down Expand Up @@ -355,8 +355,8 @@ mapping clause assembly = VIOTA_M(vm, vs2, vd)
/* *************************** OPMVV (vid in VMUNARY0) *************************** */
union clause ast = VID_V : (bits(1), regidx)

mapping clause encdec = VID_V(vm, vd) if haveRVV()
<-> 0b010100 @ vm @ 0b00000 @ 0b10001 @ 0b010 @ vd @ 0b1010111 if haveRVV()
mapping clause encdec = VID_V(vm, vd) if haveVExt()
<-> 0b010100 @ vm @ 0b00000 @ 0b10001 @ 0b010 @ vd @ 0b1010111 if haveVExt()

function clause execute(VID_V(vm, vd)) = {
let SEW = get_sew();
Expand Down
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1 comment on commit 057890d

@martinberger
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The changes look fine to me.

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