Use Zc* extensions

riscv · Jul 28, 2024 · 1f2b8b8 · 1f2b8b8
1 parent 7de3d70
commit 1f2b8b8
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Showing 9 changed files with 102 additions and 107 deletions.
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail
@@ -19,7 +19,7 @@ function fetch() -> FetchResult =
  match ext_fetch_check_pc(PC, PC) {
  Ext_FetchAddr_Error(e) => F_Ext_Error(e),
  Ext_FetchAddr_OK(use_pc) => {
- if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_C))))
+ if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
  then F_Error(E_Fetch_Addr_Align(), PC)
  else match translateAddr(use_pc, Execute()) {
  TR_Failure(e, _) => F_Error(e, PC),

diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail
@@ -17,7 +17,7 @@ function fetch() -> FetchResult = {
  Ext_FetchAddr_Error(e) => F_Ext_Error(e),
  Ext_FetchAddr_OK(use_pc) => {
  /* then check PC alignment */
- if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_C))))
+ if (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
  then F_Error(E_Fetch_Addr_Align(), PC)
  else match translateAddr(use_pc, Execute()) {
  TR_Failure(e, _) => F_Error(e, PC),

diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
@@ -12,6 +12,9 @@
 enum clause extension = Ext_C
 function clause extensionEnabled(Ext_C) = misa[C] == 0b1
 
+enum clause extension = Ext_Zca
+function clause extensionEnabled(Ext_Zca) = extensionEnabled(Ext_C)
+
 /* ****************************************************************** */
 union clause ast = UTYPE : (bits(20), regidx, uop)
 
@@ -69,7 +72,7 @@ function clause execute (RISCV_JAL(imm, rd)) = {
  },
  Ext_ControlAddr_OK(target) => {
  /* Perform standard alignment check */
- if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C))
+ if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca))
  then {
  handle_mem_exception(target, E_Fetch_Addr_Align());
  RETIRE_FAIL
@@ -133,7 +136,7 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = {
  RETIRE_FAIL
  },
  Ext_ControlAddr_OK(target) => {
- if bit_to_bool(target[1]) & not(extensionEnabled(Ext_C)) then {
+ if bit_to_bool(target[1]) & not(extensionEnabled(Ext_Zca)) then {
  handle_mem_exception(target, E_Fetch_Addr_Align());
  RETIRE_FAIL;
  } else {

diff --git a/model/riscv_insts_cdext.sail b/model/riscv_insts_cdext.sail
@@ -14,12 +14,14 @@
  */
 
 /* ****************************************************************** */
+
+enum clause extension = Ext_Zcd
+function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (sizeof(xlen) == 32 | sizeof(xlen) == 64)
+
 union clause ast = C_FLDSP : (bits(6), regidx)
 
-mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FLDSP(ui86 @ ui5 @ ui43, rd) if extensionEnabled(Ext_Zcd)
+ <-> 0b001 @ ui5 : bits(1) @ rd : regidx @ ui43 : bits(2) @ ui86 : bits(3) @ 0b10 if extensionEnabled(Ext_Zcd)
 
 function clause execute (C_FLDSP(uimm, rd)) = {
  let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -34,10 +36,8 @@ mapping clause assembly = C_FLDSP(uimm, rd)
 /* ****************************************************************** */
 union clause ast = C_FSDSP : (bits(6), regidx)
 
-mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FSDSP(ui86 @ ui53, rs2) if extensionEnabled(Ext_Zcd)
+ <-> 0b101 @ ui53 : bits(3) @ ui86 : bits(3) @ rs2 : regidx @ 0b10 if extensionEnabled(Ext_Zcd)
 
 function clause execute (C_FSDSP(uimm, rs2)) = {
  let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -52,10 +52,8 @@ mapping clause assembly = C_FSDSP(uimm, rs2)
 /* ****************************************************************** */
 union clause ast = C_FLD : (bits(5), cregidx, cregidx)
 
-mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FLD(ui76 @ ui53, rs1, rd) if extensionEnabled(Ext_Zcd)
+ <-> 0b001 @ ui53 : bits(3) @ rs1 : cregidx @ ui76 : bits(2) @ rd : cregidx @ 0b00 if extensionEnabled(Ext_Zcd)
 
 function clause execute (C_FLD(uimm, rsc, rdc)) = {
  let imm : bits(12) = zero_extend(uimm @ 0b000);
@@ -72,10 +70,8 @@ mapping clause assembly = C_FLD(uimm, rsc, rdc)
 /* ****************************************************************** */
 union clause ast = C_FSD : (bits(5), cregidx, cregidx)
 
-mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2)
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
- <-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00
- if (sizeof(xlen) == 32 | sizeof(xlen) == 64) & extensionEnabled(Ext_C) & extensionEnabled(Ext_D)
+mapping clause encdec_compressed = C_FSD(ui76 @ ui53, rs1, rs2) if extensionEnabled(Ext_Zcd)
+ <-> 0b101 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00 if extensionEnabled(Ext_Zcd)
 
 function clause execute (C_FSD(uimm, rsc1, rsc2)) = {
  let imm : bits(12) = zero_extend(uimm @ 0b000);