From 28bd3bee8b473f249cbc53717f817aed9aa2abc5 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sat, 28 Sep 2024 19:12:13 +0800
Subject: [PATCH] replace vxrm with vcsr[vxrm]

---
 model/riscv_insts_vext_utils.sail |  2 +-
 model/riscv_insts_zicsr.sail      |  2 +-
 model/riscv_sys_control.sail      |  3 +-
 model/riscv_sys_regs.sail         |  1 -
 vtest.py                          | 47 +++++++++++++++++++++++++++++++
 5 files changed, 50 insertions(+), 5 deletions(-)
 create mode 100644 vtest.py

diff --git a/model/riscv_insts_vext_utils.sail b/model/riscv_insts_vext_utils.sail
index 5aa5bdff1..879b17170 100755
--- a/model/riscv_insts_vext_utils.sail
+++ b/model/riscv_insts_vext_utils.sail
@@ -399,7 +399,7 @@ val get_fixed_rounding_incr : forall ('m 'n : Int), ('m > 0 & 'n >= 0). (bits('m
 function get_fixed_rounding_incr(vec_elem, shift_amount) = {
   if shift_amount == 0 then 0b0
   else {
-    let rounding_mode = vxrm[1 .. 0];
+    let rounding_mode = vcsr[vxrm];
     match rounding_mode {
       0b00 => slice(vec_elem, shift_amount - 1, 1),
       0b01 => bool_to_bits(
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index c96d31a5b..544b41289 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -72,7 +72,7 @@ function clause read_CSR(0b1011100 /* 0xB80 */ @ index : bits(5) if sizeof(xlen)
 /* vector */
 function clause read_CSR(0x008) = zero_extend(vstart)
 function clause read_CSR(0x009) = zero_extend(vxsat)
-function clause read_CSR(0x00A) = zero_extend(vxrm)
+function clause read_CSR(0x00A) = zero_extend(vcsr[vxrm])
 function clause read_CSR(0x00F) = zero_extend(vcsr.bits)
 function clause read_CSR(0xC20) = vl
 function clause read_CSR(0xC21) = vtype.bits
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 8a8c9daa7..28f5c0301 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -558,8 +558,7 @@ function init_sys() -> unit = {
    */
   vstart             = zero_extend(0b0);
   vxsat              = 0b0;
-  vxrm               = 0b00;
-  vcsr[vxrm]       = vxrm;
+  vcsr[]       = vxrm;
   vcsr[vxsat]      = vxsat;
   vl                 = zero_extend(0b0);
   vtype[vill]      = 0b1;
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 65336f2e1..600ce26e3 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -857,7 +857,6 @@ function is_fiom_active() -> bool = {
 /* vector csrs */
 register vstart : bits(16) /* use the largest possible length of vstart */
 register vxsat  : bits(1)
-register vxrm   : bits(2)
 register vl     : xlenbits
 register vlenb  : xlenbits
 
diff --git a/vtest.py b/vtest.py
new file mode 100644
index 000000000..38ca44c6f
--- /dev/null
+++ b/vtest.py
@@ -0,0 +1,47 @@
+import os
+import subprocess
+import pandas as pd
+
+# 测试目录和模拟器路径
+TEST_DIR = "/home/rez/workbench/riscv-vector-tests/out/v512x64machine/bin/stage2/"
+EMULATOR = "/home/rez/workbench/prtest/sail-riscv/c_emulator/riscv_sim_RV64"
+
+# 结果列表
+results = []
+
+# 遍历 TEST_DIR 下的所有文件
+for root, dirs, files in os.walk(TEST_DIR):
+    for file in files:
+        test_path = os.path.join(root, file)
+        print(f"Running {test_path}...")
+
+        # 运行测试并捕获输出
+        try:
+            result = subprocess.run([EMULATOR, test_path], capture_output=True, text=True, timeout=60)
+            last_line = result.stdout.splitlines()[-1] if result.stdout else ""
+        except subprocess.TimeoutExpired:
+            last_line = "TIMEOUT"
+
+        # 判断测试结果
+        if "FAILURE" in last_line:
+            status = "FAILED"
+        elif "TIMEOUT" in last_line:
+            status = "TIMEOUT"
+        else:
+            status = "SUCCEEDED"
+
+        # 将测试结果保存到列表
+        results.append({
+            "Test File": test_path,
+            "Last Line": last_line,
+            "Status": status
+        })
+
+# 生成结果表格
+df = pd.DataFrame(results)
+
+# 将结果保存为 CSV 文件
+df.to_csv("test_results.csv", index=False)
+
+# 打印表格
+print(df)