Add Svnapot and Svpbmt extensions

riscv · Mar 28, 2024 · 3cadf65 · 3cadf65
1 parent d564b93
commit 3cadf65
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Showing 21 changed files with 200 additions and 88 deletions.
diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
@@ -77,6 +77,16 @@ bool plat_mtval_has_illegal_inst_bits(unit u)
  return rv_mtval_has_illegal_inst_bits;
 }
 
+bool sys_enable_svnapot(unit u)
+{
+ return rv_enable_svnapot;
+}
+
+bool sys_enable_svpbmt(unit u)
+{
+ return rv_enable_svpbmt;
+}
+
 mach_bits plat_ram_base(unit u)
 {
  return rv_ram_base;

diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h
@@ -8,6 +8,8 @@ bool sys_enable_zfinx(unit);
 bool sys_enable_writable_misa(unit);
 bool sys_enable_writable_fiom(unit);
 bool sys_enable_vext(unit);
+bool sys_enable_svnapot(unit);
+bool sys_enable_svpbmt(unit);
 
 uint64_t sys_pmp_count(unit);
 uint64_t sys_pmp_grain(unit);

diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
@@ -17,6 +17,8 @@ bool rv_enable_dirty_update = false;
 bool rv_enable_misaligned = false;
 bool rv_mtval_has_illegal_inst_bits = false;
 bool rv_enable_writable_fiom = true;
+bool rv_enable_svnapot = false;
+bool rv_enable_svpbmt = false;
 
 uint64_t rv_ram_base = UINT64_C(0x80000000);
 uint64_t rv_ram_size = UINT64_C(0x4000000);

diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
@@ -21,6 +21,8 @@ extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;
 extern bool rv_mtval_has_illegal_inst_bits;
 extern bool rv_enable_writable_fiom;
+extern bool rv_enable_svnapot;
+extern bool rv_enable_svpbmt;
 
 extern uint64_t rv_ram_base;
 extern uint64_t rv_ram_size;

diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
@@ -53,6 +53,8 @@ const char *RV32ISA = "RV32IMAC";
 #define OPT_ENABLE_WRITABLE_FIOM 1001
 #define OPT_PMP_COUNT 1002
 #define OPT_PMP_GRAIN 1003
+#define OPT_ENABLE_SVNAPOT 1004
+#define OPT_ENABLE_SVPBMT 1005
 
 static bool do_dump_dts = false;
 static bool do_show_times = false;
@@ -148,6 +150,8 @@ static struct option options[] = {
 #ifdef SAILCOV
  {"sailcov-file", required_argument, 0, 'c' },
 #endif
+ {"enable-svnapot", no_argument, 0, OPT_ENABLE_SVNAPOT },
+ {"enable-svpbmt", no_argument, 0, OPT_ENABLE_SVPBMT },
  {0, 0, 0, 0 }
 };
 
@@ -400,6 +404,14 @@ static int process_args(int argc, char **argv)
  trace_log_path = optarg;
  fprintf(stderr, "using %s for trace output.\n", trace_log_path);
  break;
+ case OPT_ENABLE_SVNAPOT:
+ fprintf(stderr, "enabling Svnapot extension.\n");
+ rv_enable_svnapot = true;
+ break;
+ case OPT_ENABLE_SVPBMT:
+ fprintf(stderr, "enabling Svpbmt extension.\n");
+ rv_enable_svpbmt = true;
+ break;
  case '?':
  print_usage(argv[0], 1);
  break;

diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail
@@ -24,7 +24,7 @@ function fetch() -> FetchResult =
  then F_Error(E_Fetch_Addr_Align(), PC)
  else match translateAddr(use_pc, Execute()) {
  TR_Failure(e, _) => F_Error(e, PC),
- TR_Address(ppclo, _) => {
+ TR_Address(ppclo, _, _) => {
  /* split instruction fetch into 16-bit granules to handle RVC, as
  * well as to generate precise fault addresses in any fetch
  * exceptions.
@@ -42,7 +42,7 @@ function fetch() -> FetchResult =
  Ext_FetchAddr_OK(use_pc_hi) => {
  match translateAddr(use_pc_hi, Execute()) {
  TR_Failure(e, _) => F_Error(e, PC_hi),
- TR_Address(ppchi, _) => {
+ TR_Address(ppchi, _, _) => {
  match mem_read(Execute(), ppchi, 2, false, false, false) {
  MemException(e) => F_Error(e, PC_hi),
  MemValue(ihi) => F_Base(append(ihi, ilo))

diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail
@@ -21,7 +21,7 @@ function fetch() -> FetchResult = {
  then F_Error(E_Fetch_Addr_Align(), PC)
  else match translateAddr(use_pc, Execute()) {
  TR_Failure(e, _) => F_Error(e, PC),
- TR_Address(_, _) => {
+ TR_Address(_, _, _) => {
  let i = rvfi_instruction[rvfi_insn];
  rvfi_inst_data->rvfi_insn() = zero_extend(i);
  if (i[1 .. 0] != 0b11)
@@ -34,7 +34,7 @@ function fetch() -> FetchResult = {
  Ext_FetchAddr_OK(use_pc_hi) =>
  match translateAddr(use_pc_hi, Execute()) {
  TR_Failure(e, _) => F_Error(e, PC),
- TR_Address(_, _) => F_Base(i)
+ TR_Address(_, _, _) => F_Base(i)
  }
  }
  }

diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail
@@ -85,7 +85,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr, _) =>
+ TR_Address(addr, _, _) =>
  match (width, sizeof(xlen)) {
  (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false),
  (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false),
@@ -149,7 +149,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
  match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here:
  * both result in a SAMO exception */
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr, _) => {
+ TR_Address(addr, _, _) => {
  let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
  (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),
  (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),
@@ -221,7 +221,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
  Ext_DataAddr_OK(vaddr) => {
  match translateAddr(vaddr, ReadWrite(Data, Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr, _) => {
+ TR_Address(addr, _, _) => {
  let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
  (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),
  (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),

diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail
@@ -333,7 +333,7 @@ function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = {
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(paddr, _) =>
+ TR_Address(paddr, _, _) =>
  match (width) {
  BYTE =>
  process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned),
@@ -389,7 +389,7 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = {
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = match width {
  BYTE => mem_write_ea(paddr, 1, aq, rl, false),
  HALF => mem_write_ea(paddr, 2, aq, rl, false),

diff --git a/model/riscv_insts_fext.sail b/model/riscv_insts_fext.sail
@@ -322,7 +322,7 @@ function clause execute(LOAD_FP(imm, rs1, rd, width)) = {
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr, _) => {
+ TR_Address(addr, _, _) => {
  let (aq, rl, res) = (false, false, false);
  match (width) {
  BYTE => { handle_illegal(); RETIRE_FAIL },
@@ -388,7 +388,7 @@ function clause execute (STORE_FP(imm, rs2, rs1, width)) = {
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
- TR_Address(addr, _) => {
+ TR_Address(addr, _, _) => {
  let eares : MemoryOpResult(unit) = match width {
  BYTE => MemValue () /* bogus placeholder for illegal size */,
  HALF => mem_write_ea(addr, 2, aq, rl, false),

diff --git a/model/riscv_insts_vext_mem.sail b/model/riscv_insts_vext_mem.sail
@@ -95,7 +95,7 @@ function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) =
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
  MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -182,7 +182,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem)
  trimmed = true
  }
  },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
  MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),
  MemException(e) => {
@@ -265,7 +265,7 @@ function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem)
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);
  match (eares) {
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
@@ -336,7 +336,7 @@ function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_e
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
  MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem),
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -402,7 +402,7 @@ function process_vssseg (nf, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);
  match (eares) {
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
@@ -474,7 +474,7 @@ function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, EEW_data_bytes, false, false, false) {
  MemValue(elem) => write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), elem),
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -565,7 +565,7 @@ function process_vsxseg (nf, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_inde
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = mem_write_ea(paddr, EEW_data_bytes, false, false, false);
  match (eares) {
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
@@ -658,7 +658,7 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = {
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
  MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, cur_field), elem),
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -682,7 +682,7 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = {
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) {
  MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j), elem),
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -740,7 +740,7 @@ function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = {
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);
  match (eares) {
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
@@ -774,7 +774,7 @@ function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = {
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false);
  match (eares) {
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
@@ -842,7 +842,7 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = {
  then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Read(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  match mem_read(Read(Data), paddr, 1, false, false, false) {
  MemValue(elem) => write_single_element(8, i, vd_or_vs3, elem),
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }
@@ -858,7 +858,7 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = {
  then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL }
  else match translateAddr(vaddr, Write(Data)) {
  TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },
- TR_Address(paddr, _) => {
+ TR_Address(paddr, _, _) => {
  let eares : MemoryOpResult(unit) = mem_write_ea(paddr, 1, false, false, false);
  match (eares) {
  MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL },