From 58c914e66dc66189112f92ff225cd63d1d316c01 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 30 May 2024 13:26:44 -0500 Subject: [PATCH] riscv_ctr_regs.sail --- c_emulator/riscv_platform.c | 4 ---- c_emulator/riscv_platform.h | 1 - c_emulator/riscv_platform_impl.c | 1 - c_emulator/riscv_platform_impl.h | 1 - c_emulator/riscv_sim.c | 12 +++++------- model/riscv_ctr_regs.sail | 7 ++----- model/riscv_insts_ctr.sail | 18 ++++++------------ model/riscv_sys_control.sail | 9 ++++----- model/riscv_sys_regs.sail | 14 ++++++++------ ocaml_emulator/platform.ml | 2 -- ocaml_emulator/riscv_ocaml_sim.ml | 3 --- 11 files changed, 25 insertions(+), 47 deletions(-) diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c index aa321326e..4ab464606 100644 --- a/c_emulator/riscv_platform.c +++ b/c_emulator/riscv_platform.c @@ -75,10 +75,6 @@ uint64_t sys_valid_ctr_depth(unit u) { return rv_valid_ctr_depth; } -bool sys_enable_ssctr(unit u) -{ - return rv_enable_ssctr; -} bool sys_enable_smctr(unit u) { return rv_enable_smctr; diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h index df2591d11..3e52c4df9 100644 --- a/c_emulator/riscv_platform.h +++ b/c_emulator/riscv_platform.h @@ -12,7 +12,6 @@ bool sys_enable_writable_fiom(unit); bool sys_enable_vext(unit); uint64_t sys_valid_ctr_depth(unit u); -bool sys_enable_ssctr(unit u); bool sys_enable_smctr(unit u); uint64_t sys_pmp_count(unit); diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c index 51b40c8fe..e91748d1e 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c @@ -8,7 +8,6 @@ uint64_t rv_pmp_grain = 0; uint64_t rv_valid_ctr_depth = 0x1F; bool rv_enable_smctr = true; -bool rv_enable_ssctr = true; bool rv_enable_svinval = false; bool rv_enable_zcb = false; diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h index 7d3450037..498fefedf 100644 --- a/c_emulator/riscv_platform_impl.h +++ b/c_emulator/riscv_platform_impl.h @@ -13,7 +13,6 @@ extern uint64_t rv_pmp_grain; extern uint64_t rv_valid_ctr_depth; extern bool rv_enable_smctr; -extern bool rv_enable_ssctr; extern bool rv_enable_svinval; extern bool rv_enable_zcb; diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index dd278951c..7461aefc4 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -55,8 +55,7 @@ const char *RV32ISA = "RV32IMAC"; #define OPT_PMP_GRAIN 1003 #define OPT_ENABLE_SVINVAL 1004 #define OPT_ENABLE_SMCTR 1005 -#define OPT_ENABLE_SSCTR 1006 -#define OPT_VALID_CTR_DEPTH 1007 +#define OPT_VALID_CTR_DEPTH 1006 #define OPT_ENABLE_ZCB 10014 static bool do_dump_dts = false; @@ -154,7 +153,6 @@ static struct option options[] = { {"enable-zcb", no_argument, 0, OPT_ENABLE_ZCB }, {"valid-ctr-depth", required_argument, 0, OPT_VALID_CTR_DEPTH }, {"enable-smctr", no_argument, 0, OPT_ENABLE_SMCTR }, - {"enable-ssctr", no_argument, 0, OPT_ENABLE_SSCTR }, #ifdef SAILCOV {"sailcov-file", required_argument, 0, 'c' }, #endif @@ -406,15 +404,15 @@ static int process_args(int argc, char **argv) fprintf(stderr, "enabling Smctr extension.\n"); rv_enable_smctr = true; break; - case OPT_ENABLE_SSCTR: - fprintf(stderr, "enabling Ssctr extension.\n"); - rv_enable_ssctr = true; - break; case OPT_VALID_CTR_DEPTH: rv_valid_ctr_depth = atol(optarg); fprintf(stderr, "Valid CTR depth: %" PRIu64 "\n", rv_valid_ctr_depth); if (rv_valid_ctr_depth > 0x1F) { fprintf(stderr, "invalid CTR depth"); + fprintf(stderr, + "CTR depth should be specified as a bitmap where \n" + "bit position i being 1 indicates CTR depth of \n" + "2^(i+4) is valid and implemented\n"); exit(1); } break; diff --git a/model/riscv_ctr_regs.sail b/model/riscv_ctr_regs.sail index 1c88e55f3..f1e06034f 100644 --- a/model/riscv_ctr_regs.sail +++ b/model/riscv_ctr_regs.sail @@ -96,6 +96,7 @@ register ctr_cycle_counter_valid : bool function legalize_mctrctl(o : Mctrctl, v : xlenbits) -> Mctrctl = { let m : Mctrctl = Mk_Mctrctl(zero_extend(v)); + let m = [m with LCOFIFRZ = if haveSmcofpmf() then m[LCOFIFRZ] else 0b0]; m } @@ -153,13 +154,9 @@ function number_of_ctr() -> int = { let num = if bit_to_bool(valid_ctr_depth[4]) then 256 else num; num } -function isValidCtrMiselect() -> bool = { - let ctr_select = miselect.bits[7 .. 0]; - haveSmctr() & (unsigned(ctr_select) < number_of_ctr()) -} function isValidCtrSiselect() -> bool = { let ctr_select = siselect.bits[7 .. 0]; - haveSsctr() & (unsigned(ctr_select) < number_of_ctr()) + haveSmctr() & (unsigned(ctr_select) < number_of_ctr()) } /* Logical entry N, selected by *iselect value of (0x200 | N), is * physically at ((WRPTR - N - 1) % depth) where depth = 2^(DEPTH+4) diff --git a/model/riscv_insts_ctr.sail b/model/riscv_insts_ctr.sail index 39942d40a..6fdd19973 100644 --- a/model/riscv_insts_ctr.sail +++ b/model/riscv_insts_ctr.sail @@ -17,7 +17,7 @@ mapping clause encdec = SCTRCLR() function clause execute SCTRCLR() = { let sctrclr_illegal : bool = match cur_privilege { User => true, - Supervisor => not(haveSsctr()) | mstateen0[CTR] == 0b0, + Supervisor => not(haveSmctr()) | mstateen0[CTR] == 0b0, Machine => not(haveSmctr()) }; if sctrclr_illegal @@ -74,18 +74,11 @@ mapping encdec_ctr_xfer_type : ctr_xfer_type <-> bits(4) = { OTHER_DIRECT_JUMP_WITH_LINKAGE <-> 0b1111 } -function isSsctrEnabled() -> bool = - match(haveSmstateen(), mstateen0[CTR]) { - (false, _) => false, - (true, 0b0) => false, - (true, 0b1) => haveSsctr() - } - function is_ctr_active(priv : Privilege) -> bool = match priv { - User => isSsctrEnabled() & mctrctl[U] == 0b1 & sctrstatus[FROZEN] == 0b0, - Supervisor => isSsctrEnabled() & mctrctl[S] == 0b1 & sctrstatus[FROZEN] == 0b0, - Machine => haveSmctr() & mctrctl[M] == 0b1 & sctrstatus[FROZEN] == 0b0 + User => mctrctl[U] == 0b1 & sctrstatus[FROZEN] == 0b0, + Supervisor => mctrctl[S] == 0b1 & sctrstatus[FROZEN] == 0b0, + Machine => mctrctl[M] == 0b1 & sctrstatus[FROZEN] == 0b0 } @@ -114,7 +107,8 @@ function update_ctr(transfer_type : ctr_xfer_type, src_recorded : bool, dst_reco OTHER_DIRECT_JUMP_WITH_LINKAGE => mctrctl[DIRLJMPINH] == 0b0 & not(ras_emu), }; - /* In RAS emulation, function returns pop but coroutine swaps pop and then push */ + /* In RAS emulation, function returns only pop */ + /* In RAS emulation, coroutine swaps pop and then push */ if ras_emu & (transfer_type == FUNCTION_RETURN | transfer_type == COROUTINE_SWAP) then { sctrstatus[WRPTR] = (sctrstatus[WRPTR] - 1) & get_wrptr_mask(sctrdepth); ctrsource[unsigned(sctrstatus[WRPTR])] = [ctrsource[unsigned(sctrstatus[WRPTR])] with V = 0b0]; diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index c466ccd7d..38f643fa7 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -9,8 +9,6 @@ /* Machine-mode and supervisor-mode functionality. */ -val isSsctrEnabled : (unit) -> bool - /* CSR access control */ function csrAccess(csr : csreg) -> csrRW = csr[11..10] @@ -89,9 +87,9 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool = 0x144 => haveSupMode() & (p == Machine | p == Supervisor), // sip /* supervisor mode: Machine Control Transfer Records Control Register */ - 0x14E => haveSsctr() & (p == Machine | (p == Supervisor & isSsctrEnabled())), // sctrctl + 0x14E => haveSmctr() & (p == Machine | (p == Supervisor & mstateen0[CTR] == 0b1)), // sctrctl /* supervisor mode: Machine Control Transfer Records Status Register */ - 0x14F => haveSsctr() & (p == Machine | (p == Supervisor & isSsctrEnabled())), // sctrstatus + 0x14F => haveSmctr() & (p == Machine | (p == Supervisor & mstateen0[CTR] == 0b1)), // sctrstatus /* supervisor mode: indirect register select and alias CSRs */ 0x150 => haveSupMode() & haveSscsrind() & @@ -110,7 +108,7 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool = (p == Machine | (p == Supervisor & isSscsrindEnabled())), // sireg6 /* supervisor mode: Machine Control Transfer Records Depth Register */ - 0x15F => haveSsctr() & (p == Machine | (p == Supervisor & isSsctrEnabled())), // sctrdepth + 0x15F => haveSmctr() & (p == Machine | (p == Supervisor & mstateen0[CTR] == 0b1)), // sctrdepth /* supervisor mode: address translation */ 0x180 => haveSupMode() & (p == Machine | p == Supervisor), // satp @@ -576,6 +574,7 @@ function init_sys() -> unit = { menvcfg.bits = zero_extend(0b0); senvcfg.bits = zero_extend(0b0); mstateen0.bits = zero_extend(0b0); + mctrctl.bits = zero_extend(0b0); /* Smctr/Ssctr cycle counter */ ctr_cycle_counter_valid = false; diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 7e3ef443f..42775d287 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -177,11 +177,14 @@ function haveSscsrind() -> bool = true /* Smcsrind extension support */ function haveSmcsrind() -> bool = true -/* Smctr extension support - Smctr depends on S-mode, and Smcsrind */ -function haveSmctr() -> bool = haveSupMode() & sys_enable_smctr() & haveSmcsrind() +/* Smctr extension support - Smctr depends on S-mode, and Sscsrind */ +function haveSmctr() -> bool = haveSupMode() & sys_enable_smctr() & haveSscsrind() /* Ssctr extension support - Ssctr depends on S-mode, Smctr, and Sscsrind */ -function haveSsctr() -> bool = haveSupMode() & sys_enable_ssctr() & haveSmctr() & haveSscsrind() +function haveSsctr() -> bool = haveSupMode() & haveSmctr() & haveSscsrind() + +/* Smcofpmf extension support */ +function haveSmcofpmf() -> bool = false bitfield Mstatush : bits(32) = { MBE : 5, @@ -997,10 +1000,9 @@ function isValidMiselect() -> bool = { * is UNSPECIFIED. It is expected that implementations * will typically raise an illegal instruction exception */ - if unsigned(miselect[REG]) >= 512 & unsigned(miselect[REG]) <= 767 - then isValidCtrMiselect() /* 0x200 - 0x2FF is designated for Smctr */ - else false; + false } + function isValidSiselect() -> bool = { /* The behavior upon accessing sireg* from M/S-mode, * while siselect holds a value that is not implemented, diff --git a/ocaml_emulator/platform.ml b/ocaml_emulator/platform.ml index afd491eee..0c7767313 100644 --- a/ocaml_emulator/platform.ml +++ b/ocaml_emulator/platform.ml @@ -13,7 +13,6 @@ let config_mtval_has_illegal_inst_bits = ref false let config_enable_svinval = ref false let config_enable_zcb = ref false let config_enable_smctr = ref false -let config_enable_ssctr = ref false let config_valid_ctr_depth = ref Int.zero let config_enable_writable_fiom = ref true let config_enable_vext = ref true @@ -98,7 +97,6 @@ let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits let enable_svinval () = !config_enable_svinval let enable_zcb () = !config_enable_zcb let enable_smctr () = !config_enable_smctr -let enable_ssctr () = !config_enable_ssctr let valid_ctr_depth () = arch_bits_of_int !config_valid_ctr_depth let enable_zfinx () = false let enable_writable_fiom () = !config_enable_writable_fiom diff --git a/ocaml_emulator/riscv_ocaml_sim.ml b/ocaml_emulator/riscv_ocaml_sim.ml index d3ff62fc4..e80777e8d 100644 --- a/ocaml_emulator/riscv_ocaml_sim.ml +++ b/ocaml_emulator/riscv_ocaml_sim.ml @@ -92,9 +92,6 @@ let options = Arg.align ([("-dump-dts", ("-enable-smctr", Arg.Set P.config_enable_smctr, " enable Smctr extension"); - ("-enable-ssctr", - Arg.Set P.config_enable_ssctr, - " enable Ssctr extension"); ("-valid-ctr-depth", Arg.Int P.set_valid_ctr_depth, " valid CTR depths");