diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
index ee90b92be..3a9bfc08d 100644
--- a/c_emulator/riscv_sim.c
+++ b/c_emulator/riscv_sim.c
@@ -53,7 +53,7 @@ const char *RV32ISA = "RV32IMAC";
 #define OPT_ENABLE_WRITABLE_FIOM 1001
 #define OPT_PMP_COUNT 1002
 #define OPT_PMP_GRAIN 1003
-#define OPT_ENABLE_SVINVAL 10017
+#define OPT_ENABLE_SVINVAL 1004
 #define OPT_ENABLE_ZCB 10014
 
 static bool do_dump_dts = false;
diff --git a/model/riscv_insts_svinval.sail b/model/riscv_insts_svinval.sail
index ea7483867..168fb17ff 100644
--- a/model/riscv_insts_svinval.sail
+++ b/model/riscv_insts_svinval.sail
@@ -30,7 +30,7 @@ mapping clause encdec =
 function clause execute SFENCE_W_INVAL() = {
   if cur_privilege == User
   then { handle_illegal(); RETIRE_FAIL }
-  else { RETIRE_SUCCESS }
+  else { RETIRE_SUCCESS } // Implemented as no-op as all memory operations are visible immediately the current Sail model
 }
 
 mapping clause assembly = SFENCE_W_INVAL() <-> "sfence.w.inval"
@@ -46,7 +46,7 @@ mapping clause encdec =
 function clause execute SFENCE_INVAL_IR() = {
   if cur_privilege == User
   then { handle_illegal(); RETIRE_FAIL }
-  else { RETIRE_SUCCESS }
+  else { RETIRE_SUCCESS } // Implemented as no-op as all memory operations are visible immediately in current Sail model
 }
 
 mapping clause assembly = SFENCE_INVAL_IR() <-> "sfence.inval.ir"