From 5c55b5bb6f6d69dc3ff58a2ce9b25c4e582f6e88 Mon Sep 17 00:00:00 2001 From: Martin Berger Date: Tue, 30 Apr 2024 09:33:57 +0100 Subject: [PATCH] Add Svinval extension. These changes add the "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0 to the sail-riscv model. This extension defines five new instructions: SINVAL.VMA, SFENCE.W.INVAL, SFENCE.INVAL.IR, HINVAL.VVMA, HINVAL.GVMA. HINVAL.VVMA & HINVAL.GVMA are omitted since they build on the Hypervisor Extension which is yet to be included in the model. SFENCE.W.INVAL & SFENCE.INVAL.IR are treated as nops pending integration of the coherency model (rmem) with sail. The specification says that SINVAL.VMA behaves just as SFENCE.VMA, except there are additional ordering constraints with respect to the new SFENCE.W.INVAL & SFENCE.INVAL.IR instructions. Since these are nops, we can treat SINVAL.VMA as if it were SFENCE.VMA. Co-authored-by: Kristin Barber --- c_emulator/riscv_sim.c | 2 +- model/riscv_insts_svinval.sail | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index ee90b92be..3a9bfc08d 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -53,7 +53,7 @@ const char *RV32ISA = "RV32IMAC"; #define OPT_ENABLE_WRITABLE_FIOM 1001 #define OPT_PMP_COUNT 1002 #define OPT_PMP_GRAIN 1003 -#define OPT_ENABLE_SVINVAL 10017 +#define OPT_ENABLE_SVINVAL 1004 #define OPT_ENABLE_ZCB 10014 static bool do_dump_dts = false; diff --git a/model/riscv_insts_svinval.sail b/model/riscv_insts_svinval.sail index ea7483867..168fb17ff 100644 --- a/model/riscv_insts_svinval.sail +++ b/model/riscv_insts_svinval.sail @@ -30,7 +30,7 @@ mapping clause encdec = function clause execute SFENCE_W_INVAL() = { if cur_privilege == User then { handle_illegal(); RETIRE_FAIL } - else { RETIRE_SUCCESS } + else { RETIRE_SUCCESS } // Implemented as no-op as all memory operations are visible immediately the current Sail model } mapping clause assembly = SFENCE_W_INVAL() <-> "sfence.w.inval" @@ -46,7 +46,7 @@ mapping clause encdec = function clause execute SFENCE_INVAL_IR() = { if cur_privilege == User then { handle_illegal(); RETIRE_FAIL } - else { RETIRE_SUCCESS } + else { RETIRE_SUCCESS } // Implemented as no-op as all memory operations are visible immediately in current Sail model } mapping clause assembly = SFENCE_INVAL_IR() <-> "sfence.inval.ir"