diff --git a/model/riscv_insts_zicfiss.sail b/model/riscv_insts_zicfiss.sail
index 95875b6c2..36bbb88d2 100644
--- a/model/riscv_insts_zicfiss.sail
+++ b/model/riscv_insts_zicfiss.sail
@@ -90,7 +90,7 @@ function zicfiss_xSSE(priv : Privilege) -> bool = {
   else if priv == Supervisor
   then menvcfg[SSE] == 0b1
   else if haveSupMode()
-  then senvcfg.SSE() == 0b1
+  then senvcfg[SSE] == 0b1
   else false
 }
 
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 3addb2d20..ad467386c 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -860,7 +860,7 @@ function legalize_senvcfg(o : SEnvcfg, v : xlenbits) -> SEnvcfg = {
   let v = Mk_SEnvcfg(v);
   let o = [o with FIOM = if sys_enable_writable_fiom() then v[FIOM] else 0b0];
   // Zicfiss - SSE: shadow stack enable - is ROZ in senvcfg if menvcfg.SSE is 0
-  let o = update_SSE(o, if haveZicfiss() & menvcfg.SSE() == 0b1 then v.SSE() else 0b0);
+  let o = [o with SSE = if haveZicfiss() & menvcfg[SSE] == 0b1 then v[SSE] else 0b0];
   // Other extensions are not implemented yet so all other fields are read only zero.
   o
 }
diff --git a/model/riscv_zicfiss_control.sail b/model/riscv_zicfiss_control.sail
index 6baae058d..f153391ea 100644
--- a/model/riscv_zicfiss_control.sail
+++ b/model/riscv_zicfiss_control.sail
@@ -90,7 +90,7 @@ function clause ext_is_CSR_defined(0x011, priv) = { // ssp
   else if priv == Supervisor
   then menvcfg[SSE] == 0b1
   else if haveSupMode()
-  then senvcfg.SSE() == 0b1
+  then senvcfg[SSE] == 0b1
   else false
 }
 function clause ext_read_CSR(0x011)          = Some(ssp)
@@ -101,7 +101,7 @@ function clause ext_write_CSR(0x011, value)  = {
    * Sail model does not support dynamic switching of UXL/SXL so that is
    * not considered in the following algorithm yet.
    */
-  if ( architecture(misa.MXL()) == Some(RV64) ) then
+  if ( architecture(misa[MXL]) == Some(RV64) ) then
     ssp[2 .. 2] = 0b0;
   Some(ssp);
 }