From 2c74f819edbb98b30460d445be5d87102cb38320 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Mon, 29 Apr 2024 20:26:58 -0500 Subject: [PATCH 01/51] adding support for using https://github.com/riscv-software-src/riscv-tests --- .gitmodules | 4 + SAIL_RISCV_ROOTDIR | 10 + TEST_DIR_ROOT/riscv_tests.git | 1 + bin/run_tests.py | 736 ++++++++++++++++++++++++++++++++++ 4 files changed, 751 insertions(+) create mode 100644 .gitmodules create mode 100644 SAIL_RISCV_ROOTDIR create mode 160000 TEST_DIR_ROOT/riscv_tests.git create mode 100755 bin/run_tests.py diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 000000000..27727d20b --- /dev/null +++ b/.gitmodules @@ -0,0 +1,4 @@ +[submodule "TEST_DIR_ROOT/riscv_tests.git"] + path = TEST_DIR_ROOT/riscv_tests.git + url = git@github.com:riscv-software-src/riscv-tests.git + branch = riscv-tests-sail diff --git a/SAIL_RISCV_ROOTDIR b/SAIL_RISCV_ROOTDIR new file mode 100644 index 000000000..6ab1ca3a7 --- /dev/null +++ b/SAIL_RISCV_ROOTDIR @@ -0,0 +1,10 @@ + +This file is created in the root directory for the RISC-V Sail model. +It is used as a reference point for various tools within the repo. + +Do not rename it. Do not move it. Do not duplicate it anywhere in +the repo, else tooling may get confused. + + + + diff --git a/TEST_DIR_ROOT/riscv_tests.git b/TEST_DIR_ROOT/riscv_tests.git new file mode 160000 index 000000000..6b1d7372d --- /dev/null +++ b/TEST_DIR_ROOT/riscv_tests.git @@ -0,0 +1 @@ +Subproject commit 6b1d7372d951ed75811e0a09c0fe9e065c141c2d diff --git a/bin/run_tests.py b/bin/run_tests.py new file mode 100755 index 000000000..2f422dbdf --- /dev/null +++ b/bin/run_tests.py @@ -0,0 +1,736 @@ +#! /usr/bin/env python3 +# vim: set tabstop=4 shiftwidth=4 expandtab set textwidth=79 +# ===========================================================================79 +# Filename: run_tests.py +# +# Description: Converting run_tests.sh to python +# +# Based on run_test.sh +# +# Same as run_test.sh: +# 1. output into .xml file is the same +# 2. colorization of output +# +# Differences with run_test.sh +# 1. Does not depend upon .elf file extension for filetype. +# Uses the unix 'file' command to get filetype +# 2. Added usage function +# 3. Added run switches (which didn't exist in run_test.sh) +# See the print_usage() function for a descriptionm of +# the supported switches. +# 4. Default search directories, rather than just one. +# 5. Removed use of $RISCV env var. +# 6. requires python3 +# 7. Added support to ignore tests via the --test_ignore_pyfile +# switch +# 8. Added support to supply switches to the riscv_sim command +# via the --test_switch_pyfile. +# +# TODO: Need to add timeouts to tests. +# +# Author(s): Bill McSpadden (bill@riscv.org) +# +# History: See revision control log +# ===========================================================================79 + +# ===========================================================================79 +# Necessary imports for this script: +import os # needed for os command interactions +import glob # needed for file list gathering useing wildcards +import re # regular expression +import sys # needed for command line arguments +import getopt # needed for command line arguments +import collections # needed for dequeues +import subprocess # needed for subprocesses where stdout is needed +from pathlib import Path +from inspect import currentframe, getframeinfo +from abc import ABC, abstractmethod +from copy import deepcopy +# Necessary imports for this script +# ===========================================================================79 + + +# ===========================================================================79 +# General data for use in this script. +# ===========================================================================79 +# Data structure for sim command line arguments +# TODO: make the key a regex +sim_test_command_line_switch_dict = { } +my_ignore_test_tuple = [] + +# Allowed command line options +opts, args = getopt.getopt ( + sys.argv[1:], + "dhuo:", + [ + "help", + "usage", + "outfile=", + "test_dir=", + "32bit=", + "64bit=", + "c_sim=", + "ocaml_sim=", + "sailcov=", + "clean_build=", + "test_dir=", + "test_switch_pyfile=", + "test_ignore_pyfile=", + "debug" + ] + ) + +# Variables to be overridden with command line switches +xml_outfile = "./tests.xml" +run_32bit_tests = True +run_64bit_tests = True +run_csim = True +run_ocamlsim = False +sailcov = False +clean_build = True +test_dir_list = [ "isa", "riscv-tests" ] +sail_riscv_rootdir = 'SAIL_RISCV_ROOTDIR' +test_switch_pyfile = '' +test_ignore_pyfile = '' +debug = False + +# Variables for tracking test status and test output +RED = '\033[0;91m' +GREEN = '\033[0;92m' +YELLOW = '\033[0;93m' +NC = '\033[0m' +test_pass = 0 +test_fail = 0 +all_pass = 0 +all_fail = 0 +SUITE_XML = "" +SUITES_XML = "" +# ===========================================================================79 + +# ===========================================================================79 +# Function prototypes: +# ==================================== +# Print Levels: +# print() Normal python print function. Goes to stdout +# debug_print() Print debug information. Goes to stdout. +# error_print() Print error message. Goes to stdout. Generally most errors should be fatal errors +# fatal_print() Print fatal error message. Exit with status 1. Generally most errors should be fatal errors. Goes to stdout. +# TRACE() For bringup debug only. TRACE() instances should be removed. + +def debug_print (text = "") : + cf = currentframe() + of = cf.f_back + fi = getframeinfo(of) + filename = os.path.basename(fi.filename) + print("debug: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) + return + +def error_print (text = "") : + cf = currentframe() + of = cf.f_back + fi = getframeinfo(of) + filename = os.path.basename(fi.filename) + print("error: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) + return + +def fatal_print (text = "") : + cf = currentframe() + of = cf.f_back + fi = getframeinfo(of) + filename = os.path.basename(fi.filename) + print("fatal error: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) + return + +def TRACE(text = "") : + cf = currentframe() + of = cf.f_back + fi = getframeinfo(of) + filename = os.path.basename(fi.filename) + print("TRACE: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) + return +# Print Levels: +# ==================================== + +# ==================================== +# Support for command line options +def print_usage(invocation) : + print(invocation + " usage: " + invocation + " []") + print(" Typically, invoke this script in the directory above where the elf-file tests live.") + print(" The script looks into test_dir, finds all of the elf files and then runs the simulator") + print(" with each elf file.") + print("") + print(" Output logs are put into [dir]/.cout (for C sim) or [dir/].out (for ocaml sim).") + print("") + print(" Some tests require specific command line switches to properly run. To add these") + print(" command line switches, you must use the '--test_switch_pyfile=' switch.") + print("") + print(" options:") + print(" -h --help -u -usage print out help/usage message") + print(" -o/--outfile= name of xml tests results file to be generated. default: ./tests.xml ") + print(" --32bit=[yes|y|no|n] run 32-bit tests. default: yes") + print(" --64bit=[yes|y|no|n] run 64-bit tests. default: yes") + print(" --c_sim=[yes|y|no|n] run the C simulator. default: yes") + print(" --ocaml_sim=[yes|y|no|n] run the Ocaml simulator. default: no") + print(" --sailcov=[yes|y|no|n] compile and run to get Sail model coverage. default: no. ") + print(" NOTE: sets 'clean_build' to yes. Coverage is gathered seperately for ") + print(" 32 and 64 bit models") + print(" --clean_build=[yes|y|no|n] do a 'make clean' before running 32/64/c_sim/ocaml_sim set of tests. default: yes") + print(" --test_dir= directory where test elf files live. default: ./isa ./riscv-tests") + print(" --test_switch_pyfile= a python fragment file that allows the user to pass in command line switches to the") + print(" riscv_sim command on a per-test basis. The format of the file should be:") + print(" sim_test_command_line_switch_dict = {") + print(" \"\" : \" [ ...] \",") + print(" \"\" : \" [ ...] \",") + print(" }") + print(" --test_ignore_pyfile= contains a tuple (immutable list) of tests to be ignored. The format of the file should be:") + print(" ignore_test_tuple = [") + print(" \"\",") + print(" \"\",") + print(" ]") + print(" -d,--debug turn on debug output") + +def process_command_line_args(opts) : + global xml_outfile + global run_32bit_tests + global run_32bit_tests + global run_64bit_tests + global run_csim + global run_ocamlsim + global sailcov + global clean_build + global test_dir_list + global test_switch_pyfile + global test_ignore_pyfile + global debug + + for opt, arg in opts : + if opt in ('-h', '--help', '-u', '--usage') : + print_usage(sys.argv[0]) + sys.exit(0) + elif opt in ('-o', "--outfile") : + xml_outfile = arg + elif opt in ('--32bit') : + if arg in ('yes', 'y') : + run_32bit_tests = True + elif arg in ('no', 'n') : + run_32bit_tests = False + else : + fatal_print("invalid argument to '--32bit' switch: " + arg) + elif opt in ('--64bit') : + if arg in ('yes', 'y') : + run_64bit_tests = True + elif arg in ('no', 'n') : + run_64bit_tests = False + else : + fatal_print("invalid argument to '--64bit' switch: " + arg) + elif opt in ('--c_sim') : + if arg in ('yes', 'y') : + run_csim = True + elif arg in ('no', 'n') : + run_csim = False + else : + fatal_print("invalid argument to '--run_csim' switch: " + arg) + elif opt in ('--ocaml_sim') : + if arg in ('yes', 'y') : + run_ocamlsim = True + elif arg in ('no', 'n') : + run_ocamlsim = False + else : + fatal_print("invalid argument to '--run_ocamlsim' switch: " + arg) + elif opt in ('--sailcov') : + if arg in ('yes', 'y') : + sailcov = True + elif arg in ('no', 'n') : + sailcov = False + else : + fatal_print("invalid argument to '--sailcov' switch: " + arg) + sys.exit(1) + elif opt in ('--clean_build') : + if arg in ('yes', 'y') : + clean_build = True + elif arg in ('no', 'n') : + clean_build = False + else : + fatal_print("invalid argument to '--run_ocamlsim' switch: " + arg) + sys.exit(1) + elif opt in ('--test_dir') : + if not os.path.exists(arg) : + fatal_print("test_dir path, '" + arg + "', does not exist") + test_dir_list = [] + test_dir_list.append(arg) + elif opt in ('--test_switch_pyfile') : + if not os.path.isfile(arg) : + fatal_print("--test_switch_pyfile argument error. file, '" + arg + "', does not exist") + test_switch_pyfile = arg + elif opt in ('--test_ignore_pyfile') : + if not os.path.isfile(arg) : + fatal_print("--test_ignore_pyfile argument error. file, '" + arg + "', does not exist") + sys.exit(1) + test_ignore_pyfile = arg + elif opt in ('-d', '--debug') : + debug = True + else : + fatal_print("unexpected command line option: " + opt) + +# print_optional_settings AFTER the inmplicit overrides have happened +def print_optional_settings() : + global xml_outfile + global run_32bit_tests + global run_32bit_tests + global run_64bit_tests + global run_csim + global run_ocamlsim + global sailcov + global clean_build + global test_dir_list + global test_switch_pyfile + global test_ignore_pyfile + global debug + + print('================================================================') + print('Run time variable settings: ') + print(' {:32}'.format('debug: ') + str(debug)) + print(' {:32}'.format('outfile: ') + xml_outfile) + print(' {:32}'.format('run_32bit_tests: ') + str(run_32bit_tests)) + print(' {:32}'.format('run_64bit_tests: ') + str(run_64bit_tests)) + print(' {:32}'.format('run_csim: ') + str(run_csim)) + print(' {:32}'.format('run_ocamlsim: ') + str(run_ocamlsim)) + print(' {:32}'.format('sailcov: ') + str(sailcov)) + print(' {:32}'.format('clean_build: ') + str(clean_build)) + print(' {:32}'.format('test_dir_list: ') + str(test_dir_list)) + print(' {:32}'.format('test_ignore_pyfile: ') + test_ignore_pyfile) + print(' {:32}'.format('ignore_test: ') + str(my_ignore_test_tuple)) + print(' {:32}'.format('test_switch_pyfile: ') + test_switch_pyfile) + print(' {:32}'.format('sim_test_comand_line_switch: ') + str(sim_test_command_line_switch)) + print('================================================================') + +# Support for command line options +# ==================================== + +# ==================================== +# Functions from run_tests.sh +def green(test_str, ok_fail_str) : + global test_pass + global SUITE_XML + global GREEN + global NC + test_pass += 1 + print(test_str + ':' + GREEN + ok_fail_str + NC) + SUITE_XML += ' \n' + +def yellow(test_str, ok_fail_str) : + global test_fail + global SUITE_XML + global YELLOW + global NC + test_fail += 1 + print(test_str + ':' + YELLOW + ok_fail_str + NC) + SUITE_XML += ' \n ' + ok_fail_str + '\n \n' + +def red(test_str, ok_fail_str) : + global test_fail + global SUITE_XML + global RED + global NC + test_fail += 1 + print(test_str + ':' + RED + ok_fail_str + NC) + SUITE_XML += ' \n ' + ok_fail_str + '\n \n' + +def finish_suite(suite_name) : + global test_pass + global test_fail + global all_pass + global all_fail + global SUITE_XML + global SUITES_XML + + print(suite_name + ': Passed ' + str(test_pass) + ' out of ' + str(test_pass + test_fail) + '\n\n') + date_tmp = subprocess.check_output("date", shell=True, text=True) + date = date_tmp.rstrip() + SUITES_XML += ' \n' + SUITE_XML + ' \n' + SUITE_XML="" + all_pass += test_pass + all_fail += test_fail + test_pass = 0 + test_fail = 0 +# Functions from run_tests.sh +# ==================================== + + +# ==================================== +# Functions for determining file types +# +# TODO: there MUST be an equivalent to the 'file' command in python. +# Replace the 'file' command with a python equivalent. + +def is_elf(filename) : + cmd = "file -b " + filename + " | awk 'BEGIN { FS = \",\" } ; { print $1 } ' | grep -q \"ELF\" " + ret = os.system(cmd) + if ret == 0 : + return 1 + else : + return 0 + +def is_32bit(filename) : + cmd = "file -b " + filename + " | awk 'BEGIN { FS = \",\" } ; { print $1 } ' | grep -q \"32-bit\" " + ret = os.system(cmd) + if ret == 0 : + return 1 + else : + return 0 + +def is_64bit(filename) : + cmd = "file -b " + filename + " | awk 'BEGIN { FS = \",\" } ; { print $1 } ' | grep -q \"64-bit\" " + ret = os.system(cmd) + if ret == 0 : + return 1 + else : + return 0 + +def is_riscv(filename) : + cmd = "file -b " + filename + " | awk 'BEGIN { FS = \",\" } ; { print $2 } ' | grep -q \"RISC-V\" " + ret = os.system(cmd) + if ret == 0 : + return 1 + else : + return 0 + +def is_riscv_elf(filename) : + return is_elf(filename) and is_riscv(filename) + +def is_riscv_elf_32(filename) : + return is_riscv_elf(filename) and is_32bit(filename) + +def is_riscv_elf_64(filename) : + return is_riscv_elf(filename) and is_64bit(filename) + +def ignore_test(testname) : + for t in my_ignore_test_tuple : + print("ignore_test function: testname: " + os.path.basename(testname) + " t: " + t) + if t == os.path.basename(testname) : + return True + else : + continue + return False +# Functions for determining file types +# ==================================== + +# Function prototypes +# ===========================================================================79 + +# ===========================================================================79 +# Start of execution.... + +debug_print("starting...") +debug_print("abspath to this script: " + os.path.abspath(sys.argv[0])) +debug_print("opts: " + str(opts)) + +process_command_line_args(opts) + +# ==================================== +# Implicit overrides of program varaibles +if sailcov : + clean_build = True + +if test_switch_pyfile : + exec(open(test_switch_pyfile).read()) + # check to see if variable set + if 'sim_test_command_line_switch_dict' in locals() : + sim_test_command_line_switch = sim_test_command_line_switch_dict; + else : + fatal_print("the python variable, sim_test_command_line_switch_dict, is not properly set in " + test_switch_pyfile) + sys.exit(1) + +if test_ignore_pyfile : + exec(open(test_ignore_pyfile).read()) + if 'ignore_test_tuple' in locals() : + my_ignore_test_tuple = ignore_test_tuple + else : + fatal_print("the python variable, ignore_test_tuple, is not properly set in " + test_ignore_pyfile) + +# Debug print out of important program variables +if debug : + print_optional_settings() + +# TODO: check that only 1 dir in test_dir_list exists +for d in test_dir_list : + if os.path.exists(d) : + TESTDIR = d + else : + pass + +debug_print('TESTDIR : ' + TESTDIR) + +# DIR points to the invocation directory. +DIR = os.getcwd() +SEARCH_DIR = DIR +while SEARCH_DIR != '/' : + if os.path.isfile(SEARCH_DIR + '/' + sail_riscv_rootdir) : + RISCVDIR = SEARCH_DIR + break + if SEARCH_DIR == '/' : + fatal_print("can't find root directory of repository") + SEARCH_DIR = os.path.dirname(SEARCH_DIR) +debug_print("RISCVDIR: " + RISCVDIR) + +if sailcov : + MAKE_SAILCOV = "SAILCOV=true" +else : + MAKE_SAILCOV = "" + +if os.path.isfile(DIR + xml_outfile) != False : + os.remove(DIR + xml_outfile) + +# TODO: Do you really want to run the tests from the RISCVDIR? +# TODO: check for success/failure of chdir +os.chdir(RISCVDIR) + +debug_print("DIR + '/' + TESTDIR + '/' + * :" + DIR + '/' + TESTDIR + '/' + "*") + +# Do 'make clean' to avoid cross-arch pollution. + +if clean_build : + cmd = "make clean" + ret_val = os.system(cmd) + if ret_val != 0 : + fatal_print("non-zero exit value from command: '" + cmd + "'") + else : + pass +else : + pass + +if run_ocamlsim : + if run_32bit_tests : + print("Building 32-bit RISCV specification...") + cmd = "make ARCH=RV32 ocaml_emulator/riscv_ocaml_sim_RV32" + ret_val = os.system(cmd) + if ret_val == 0 : + green("Building 32-bit RISCV OCaml emulator", "ok") + else : + debug_print("non-zero exit value from command: '" + cmd + "'") + red("Building 32-bit RISCV OCaml emulator","fail") + +TRACE("run_32bit_tests and run_ocamlsim : " + str(run_32bit_tests and run_ocamlsim)) +if run_32bit_tests and run_ocamlsim : + TRACE() + for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : + debug_print("test: " + test) + if not is_riscv_elf_32(test) : + continue + if ignore_test(test) : + debug_print("ignoring test: " + test) + continue + # skip F/D tests on OCaml for now + pat = re.compile('(rv32ud)') + mo = pat.search(test) + if mo != None : + continue + pat = re.compile('(rv32uf)') + mo = pat.search(test) + if mo != None : + continue + outfile = test + ".out" + sim_switch = "" + for key in sim_test_command_line_switch : + pat = re.compile(key) + mo = pat.search(test) + if mo != None: + sim_switch = sim_test_command_line_switch[key] + break + cmd = "timeout 5 " + RISCVDIR + "/ocaml_emulator/riscv_ocaml_sim_RV32" + " " + sim_switch + " " + test + " > " + outfile + " 2>&1 && grep -q SUCCESS " + outfile + ret_val = os.system(cmd) + if ret_val == 0 : + green("OCaml-32 " + os.path.basename(test), "ok") + else : + red("OCaml-32 " + os.path.basename(test), "fail") +else : + pass + +finish_suite("32-bit RISCV OCaml-simulator tests") + +if clean_build : + cmd = "make clean" + ret_val = os.system(cmd) + if ret_val != 0 : + print("error: non-zero exit value from command: '" + cmd + "'") + sys.exit(1) + else : + pass +else : + pass + + +print("Building 32-bit RISCV specification...") +if run_csim : + if run_32bit_tests : + cmd = "make ARCH=RV32 " + MAKE_SAILCOV + " c_emulator/riscv_sim_RV32" + ret_val = os.system(cmd) + if ret_val == 0 : + green("Building 32-bit RISCV C emulator", "ok") + else : + error_print("non-zero exit value from command: '" + cmd + "'") + red("Building 32-bit RISCV C emulator","fail") + +TRACE("run_32bit_tests and run_csim : " + str(run_32bit_tests and run_csim)) +if run_32bit_tests and run_csim : + TRACE() + for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : + if not is_riscv_elf_32(test) : + continue + if ignore_test(test) : + debug_print("ignoring test: " + test) + continue + outfile = test + ".cout" + sim_switch = "" + for key in sim_test_command_line_switch : + pat = re.compile(key) + mo = pat.search(test) + if mo != None: + sim_switch = sim_test_command_line_switch[key] + break + + if sailcov : + run_sailcov = " --sailcov-file sailcov_RV32" + else : + run_sailcov = "" + + cmd = "timeout 5 " + RISCVDIR + "/c_emulator/riscv_sim_RV32" + run_sailcov + " " + sim_switch + " " + test + " > " + outfile + " 2>&1 && grep -q SUCCESS " + outfile + debug_print("cmd: '" + cmd + "'") + ret_val = os.system(cmd) + if ret_val == 0 : + green("C-32 " + os.path.basename(test), "ok") + else : + red("C-32 " + os.path.basename(test), "fail") +else : + pass + +finish_suite("32-bit RISCV C-simulator tests") + +if clean_build : + cmd = "make clean" + ret_val = os.system(cmd) + if ret_val != 0 : + fatal_print("non-zero exit value from command: '" + cmd + "'") + else : + pass +else : + pass + +print("Building 64-bit RISCV specification...") +if run_ocamlsim : + if run_64-bit_tests : + cmd = "make ARCH=RV64 ocaml_emulator/riscv_ocaml_sim_RV64" + ret_val = os.system(cmd) + if ret_val == 0 : + green("Building 64-bit RISCV OCaml emulator", "ok") + else : + error_print("non-zero exit value from command: '" + cmd + "'") + red("Building 64-bit RISCV OCaml emulator","fail") + +TRACE("run_64bit_tests and run_ocamlsim : " + str(run_64bit_tests and run_ocamlsim)) +if run_64bit_tests and run_ocamlsim : + TRACE() + for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : + debug_print("test: " + test) + if not is_riscv_elf_64(test) : + continue + if ignore_test(test) : + debug_print("ignoring test: " + test) + continue + # skip F/D tests on OCaml for now + pat = re.compile('(rv64ud)') + mo = pat.search(test) + if mo != None : + continue + pat = re.compile('(rv64uf)') + mo = pat.search(test) + if mo != None : + continue + outfile = test + ".out" + sim_switch = "" + for key in sim_test_command_line_switch : + pat = re.compile(key) + mo = pat.search(test) + if mo != None: + sim_switch = sim_test_command_line_switch[key] + break + cmd = "timeout 5 " + RISCVDIR + "/ocaml_emulator/riscv_ocaml_sim_RV64" + " " + sim_switch + " " + test + " > " + outfile + " 2>&1 && grep -q SUCCESS " + outfile + ret_val = os.system(cmd) + if ret_val == 0 : + green("OCaml-64 " + os.path.basename(test), "ok") + else : + red("OCaml-64 " + os.path.basename(test), "fail") +else : + pass + +finish_suite("64-bit RISCV OCaml-simulator tests") + + +if clean_build : + cmd = "make clean" + ret_val = os.system(cmd) + if ret_val != 0 : + fatal_print("non-zero exit value from command: '" + cmd + "'") + else : + pass +else : + pass + +print("Building 64-bit RISCV specification...") +if run_csim : + if run_64bit_tests : + cmd = "make ARCH=RV64 " + MAKE_SAILCOV + " c_emulator/riscv_sim_RV64" + ret_val = os.system(cmd) + if ret_val == 0 : + green("Building 64-bit RISCV C emulator", "ok") + else : + print("error: non-zero exit value from command: '" + cmd + "'") + red("Building 64-bit RISCV C emulator","fail") + +TRACE("run_64bit_tests and run_csim : " + str(run_64bit_tests and run_csim)) +if run_64bit_tests and run_csim : + TRACE() + for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : + debug_print("test: " + test) + if not is_riscv_elf_64(test) : + continue + if ignore_test(test) : + debug_print("ignoring test: " + test) + continue + outfile = test + ".cout" + sim_switch = "" + for key in sim_test_command_line_switch : + pat = re.compile(key) + mo = pat.search(test) + if mo != None: + sim_switch = sim_test_command_line_switch[key] + break + + if sailcov : + run_sailcov = " --sailcov-file sailcov_RV64" + else : + run_sailcov = "" + + cmd = "timeout 5 " + RISCVDIR + "/c_emulator/riscv_sim_RV64" + run_sailcov + " " + sim_switch + " " + test + " > " + outfile + " 2>&1 && grep -q SUCCESS " + outfile + ret_val = os.system(cmd) + if ret_val == 0 : + green("C-64 " + os.path.basename(test), "ok") + else : + red("C-64 " + os.path.basename(test), "fail") +else : + pass + +finish_suite("64-bit RISCV C-simulator tests") + +print('Passed ' + str(all_pass) + ' out of ' + str(all_pass + all_fail) + '\n\n') +XML = '\n' + SUITES_XML + '\n' + +xml_outfile_fh = open(DIR + '/' + xml_outfile, 'w') +print(XML, file = xml_outfile_fh) +xml_outfile_fh.close() + +if all_fail > 0 : + sys.exit(1) +else : + sys.exit(0) + From 72f59843f928bcd74537e5fb45c8b1c6690dc879 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 30 Apr 2024 15:33:17 -0500 Subject: [PATCH 02/51] debug_prirnt() statements were not correctly turned on/off. fatal_print() did not exit as expected. --- bin/run_tests.py | 38 ++++++++++++++++---------------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/bin/run_tests.py b/bin/run_tests.py index 2f422dbdf..61229d4c8 100755 --- a/bin/run_tests.py +++ b/bin/run_tests.py @@ -118,11 +118,12 @@ # TRACE() For bringup debug only. TRACE() instances should be removed. def debug_print (text = "") : - cf = currentframe() - of = cf.f_back - fi = getframeinfo(of) - filename = os.path.basename(fi.filename) - print("debug: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) + if debug : + cf = currentframe() + of = cf.f_back + fi = getframeinfo(of) + filename = os.path.basename(fi.filename) + print("debug: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) return def error_print (text = "") : @@ -139,7 +140,8 @@ def fatal_print (text = "") : fi = getframeinfo(of) filename = os.path.basename(fi.filename) print("fatal error: file: " + filename + " line: " + str(of.f_lineno) + " : " + text) - return + sys.exit(1) + return # never taken def TRACE(text = "") : cf = currentframe() @@ -406,7 +408,7 @@ def is_riscv_elf_64(filename) : def ignore_test(testname) : for t in my_ignore_test_tuple : - print("ignore_test function: testname: " + os.path.basename(testname) + " t: " + t) + debug_print("ignore testname: " + os.path.basename(testname) + " t: " + t) if t == os.path.basename(testname) : return True else : @@ -490,7 +492,7 @@ def ignore_test(testname) : # Do 'make clean' to avoid cross-arch pollution. if clean_build : - cmd = "make clean" + cmd = "make ARCH=RV32 clean" ret_val = os.system(cmd) if ret_val != 0 : fatal_print("non-zero exit value from command: '" + cmd + "'") @@ -510,9 +512,7 @@ def ignore_test(testname) : debug_print("non-zero exit value from command: '" + cmd + "'") red("Building 32-bit RISCV OCaml emulator","fail") -TRACE("run_32bit_tests and run_ocamlsim : " + str(run_32bit_tests and run_ocamlsim)) if run_32bit_tests and run_ocamlsim : - TRACE() for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : debug_print("test: " + test) if not is_riscv_elf_32(test) : @@ -549,10 +549,10 @@ def ignore_test(testname) : finish_suite("32-bit RISCV OCaml-simulator tests") if clean_build : - cmd = "make clean" + cmd = "make ARCH=RV32 clean" ret_val = os.system(cmd) if ret_val != 0 : - print("error: non-zero exit value from command: '" + cmd + "'") + fatal_print("non-zero exit value from command: '" + cmd + "'") sys.exit(1) else : pass @@ -568,12 +568,10 @@ def ignore_test(testname) : if ret_val == 0 : green("Building 32-bit RISCV C emulator", "ok") else : - error_print("non-zero exit value from command: '" + cmd + "'") red("Building 32-bit RISCV C emulator","fail") + error_print("non-zero exit value from command: '" + cmd + "'") -TRACE("run_32bit_tests and run_csim : " + str(run_32bit_tests and run_csim)) if run_32bit_tests and run_csim : - TRACE() for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : if not is_riscv_elf_32(test) : continue @@ -607,7 +605,7 @@ def ignore_test(testname) : finish_suite("32-bit RISCV C-simulator tests") if clean_build : - cmd = "make clean" + cmd = "make ARCH=RV64 clean" ret_val = os.system(cmd) if ret_val != 0 : fatal_print("non-zero exit value from command: '" + cmd + "'") @@ -627,9 +625,7 @@ def ignore_test(testname) : error_print("non-zero exit value from command: '" + cmd + "'") red("Building 64-bit RISCV OCaml emulator","fail") -TRACE("run_64bit_tests and run_ocamlsim : " + str(run_64bit_tests and run_ocamlsim)) if run_64bit_tests and run_ocamlsim : - TRACE() for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : debug_print("test: " + test) if not is_riscv_elf_64(test) : @@ -667,7 +663,7 @@ def ignore_test(testname) : if clean_build : - cmd = "make clean" + cmd = "make ARCH=RV64 clean" ret_val = os.system(cmd) if ret_val != 0 : fatal_print("non-zero exit value from command: '" + cmd + "'") @@ -684,12 +680,10 @@ def ignore_test(testname) : if ret_val == 0 : green("Building 64-bit RISCV C emulator", "ok") else : - print("error: non-zero exit value from command: '" + cmd + "'") red("Building 64-bit RISCV C emulator","fail") + error_print("non-zero exit value from command: '" + cmd + "'") -TRACE("run_64bit_tests and run_csim : " + str(run_64bit_tests and run_csim)) if run_64bit_tests and run_csim : - TRACE() for test in glob.glob(DIR + '/' + TESTDIR + '/' + "*") : debug_print("test: " + test) if not is_riscv_elf_64(test) : From 978d107c74c5b86bb4dd77496635f5f482604344 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 30 Apr 2024 16:03:28 -0500 Subject: [PATCH 03/51] removed trailing whitespace --- bin/run_tests.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/bin/run_tests.py b/bin/run_tests.py index 61229d4c8..094c23208 100755 --- a/bin/run_tests.py +++ b/bin/run_tests.py @@ -60,13 +60,13 @@ # Allowed command line options opts, args = getopt.getopt ( - sys.argv[1:], - "dhuo:", + sys.argv[1:], + "dhuo:", [ "help", "usage", - "outfile=", - "test_dir=", + "outfile=", + "test_dir=", "32bit=", "64bit=", "c_sim=", @@ -288,7 +288,7 @@ def print_optional_settings() : global test_switch_pyfile global test_ignore_pyfile global debug - + print('================================================================') print('Run time variable settings: ') print(' {:32}'.format('debug: ') + str(debug)) @@ -323,7 +323,7 @@ def green(test_str, ok_fail_str) : def yellow(test_str, ok_fail_str) : global test_fail global SUITE_XML - global YELLOW + global YELLOW global NC test_fail += 1 print(test_str + ':' + YELLOW + ok_fail_str + NC) @@ -332,7 +332,7 @@ def yellow(test_str, ok_fail_str) : def red(test_str, ok_fail_str) : global test_fail global SUITE_XML - global RED + global RED global NC test_fail += 1 print(test_str + ':' + RED + ok_fail_str + NC) @@ -345,9 +345,9 @@ def finish_suite(suite_name) : global all_fail global SUITE_XML global SUITES_XML - + print(suite_name + ': Passed ' + str(test_pass) + ' out of ' + str(test_pass + test_fail) + '\n\n') - date_tmp = subprocess.check_output("date", shell=True, text=True) + date_tmp = subprocess.check_output("date", shell=True, text=True) date = date_tmp.rstrip() SUITES_XML += ' \n' + SUITE_XML + ' \n' SUITE_XML="" @@ -463,7 +463,7 @@ def ignore_test(testname) : debug_print('TESTDIR : ' + TESTDIR) -# DIR points to the invocation directory. +# DIR points to the invocation directory. DIR = os.getcwd() SEARCH_DIR = DIR while SEARCH_DIR != '/' : @@ -502,7 +502,7 @@ def ignore_test(testname) : pass if run_ocamlsim : - if run_32bit_tests : + if run_32bit_tests : print("Building 32-bit RISCV specification...") cmd = "make ARCH=RV32 ocaml_emulator/riscv_ocaml_sim_RV32" ret_val = os.system(cmd) From 29825dad4e2d9f8dfcf277ca2d603033224f7a05 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 30 Apr 2024 16:11:42 -0500 Subject: [PATCH 04/51] fixed end-of-file whitespace --- SAIL_RISCV_ROOTDIR | 5 ----- bin/run_tests.py | 1 - 2 files changed, 6 deletions(-) diff --git a/SAIL_RISCV_ROOTDIR b/SAIL_RISCV_ROOTDIR index 6ab1ca3a7..94dadf31f 100644 --- a/SAIL_RISCV_ROOTDIR +++ b/SAIL_RISCV_ROOTDIR @@ -1,10 +1,5 @@ - This file is created in the root directory for the RISC-V Sail model. It is used as a reference point for various tools within the repo. Do not rename it. Do not move it. Do not duplicate it anywhere in the repo, else tooling may get confused. - - - - diff --git a/bin/run_tests.py b/bin/run_tests.py index 094c23208..bc7ccb7e4 100755 --- a/bin/run_tests.py +++ b/bin/run_tests.py @@ -727,4 +727,3 @@ def ignore_test(testname) : sys.exit(1) else : sys.exit(0) - From 8c8959563b45b922662e0f116fa087079056c8e6 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 11:02:29 -0500 Subject: [PATCH 05/51] added download and install of RISC-V toolchain --- .github/workflows/compile.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 865c748a5..f6a6f80d1 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -18,6 +18,10 @@ jobs: run: opam init --disable-sandboxing -y - name: Install sail run: opam install -y sail + - name: Download RISC-V toolchain (32-bit) + run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz + - name: Install RISC-V toolchain (32-bit) + run: sudo tar xvfz riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Build and test simulators run: eval $(opam env) && test/run_tests.sh - name: Upload test results From c7b97435d34125ad61916b4f99797634e0c8bbee Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 11:35:47 -0500 Subject: [PATCH 06/51] added a 'build testsuite' action --- .github/workflows/compile.yml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index f6a6f80d1..67beb6029 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -22,6 +22,19 @@ jobs: run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz - name: Install RISC-V toolchain (32-bit) run: sudo tar xvfz riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt + - name: Download RISC-V toolchain (64-bit) + run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz + - name: Install RISC-V toolchain (32-bit) + run: sudo tar xvfz riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt + - name: Build RISC-V testsuite + run: | + cd TEST_DIR_ROOT/ ; \ + git submodule update --init --recursive ; \ + cd riscv_tests.git ; \ + git checkout riscv-tests-tail ; \ + autoconf ; \ + ./configure --prefix=${PWD}/target ; \ + make isa ; - name: Build and test simulators run: eval $(opam env) && test/run_tests.sh - name: Upload test results From 64097ca86a3f9e75acd3bffdea0a748bbaa258dd Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 11:42:08 -0500 Subject: [PATCH 07/51] fixed a type in the branch name --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 67beb6029..6c55e958c 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -31,7 +31,7 @@ jobs: cd TEST_DIR_ROOT/ ; \ git submodule update --init --recursive ; \ cd riscv_tests.git ; \ - git checkout riscv-tests-tail ; \ + git checkout riscv-tests-sail ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ make isa ; From 25484f1ea54d593bf85c52c00599595eb4c61db2 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 11:56:29 -0500 Subject: [PATCH 08/51] trying to get the submodules to get checked out recursively --- .github/workflows/compile.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 6c55e958c..fbb2caf12 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -11,7 +11,7 @@ jobs: - name: Check out repository code uses: actions/checkout@HEAD with: - submodules: true + submodules: recursive - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always - name: Init opam @@ -28,8 +28,8 @@ jobs: run: sudo tar xvfz riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Build RISC-V testsuite run: | + git branch ; \ cd TEST_DIR_ROOT/ ; \ - git submodule update --init --recursive ; \ cd riscv_tests.git ; \ git checkout riscv-tests-sail ; \ autoconf ; \ From cb0118b14ceea59f08f5e2099599b86b020e3cec Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 12:18:39 -0500 Subject: [PATCH 09/51] still trying to get things to work --- .github/workflows/compile.yml | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index fbb2caf12..1361e3fc2 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,9 +29,7 @@ jobs: - name: Build RISC-V testsuite run: | git branch ; \ - cd TEST_DIR_ROOT/ ; \ - cd riscv_tests.git ; \ - git checkout riscv-tests-sail ; \ + cd TEST_DIR_ROOT/riscv_tests.git ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ make isa ; From 4c2943cff89ae015d4bbb313d4645dfc234df6be Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 13:22:05 -0500 Subject: [PATCH 10/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 1361e3fc2..48be9edeb 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -28,8 +28,8 @@ jobs: run: sudo tar xvfz riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Build RISC-V testsuite run: | - git branch ; \ cd TEST_DIR_ROOT/riscv_tests.git ; \ + echo ${PWD} ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ make isa ; From ee5f1ff7ede258363cf89c4324145c9ddad03beb Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 13:34:39 -0500 Subject: [PATCH 11/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 48be9edeb..4b8f5d788 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,7 +29,7 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ - echo ${PWD} ls ; \ + echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ make isa ; From 7d1b7176baf52898fc9ed772c8cb3267a14f2c4c Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 13:45:47 -0500 Subject: [PATCH 12/51] intermediate checkin --- .github/workflows/compile.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 4b8f5d788..3bad45b2d 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -32,6 +32,8 @@ jobs: echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ + make -v ; \ + which gmake ; \ make isa ; - name: Build and test simulators run: eval $(opam env) && test/run_tests.sh From 0295cebaf0c31ddbe9c4831e69aae1ad9c91be6c Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 15:44:21 -0500 Subject: [PATCH 13/51] intermediate checkin --- .github/workflows/compile.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 3bad45b2d..c2042b080 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -24,7 +24,7 @@ jobs: run: sudo tar xvfz riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Download RISC-V toolchain (64-bit) run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz - - name: Install RISC-V toolchain (32-bit) + - name: Install RISC-V toolchain (64-bit) run: sudo tar xvfz riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Build RISC-V testsuite run: | @@ -34,6 +34,7 @@ jobs: ./configure --prefix=${PWD}/target ; \ make -v ; \ which gmake ; \ + export PATH=/opt/riscv/bin:${PATH} ; \ make isa ; - name: Build and test simulators run: eval $(opam env) && test/run_tests.sh From 4dc5f3099369455a74be5eb6b9e84a34b4822168 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 19:30:47 -0500 Subject: [PATCH 14/51] intermediate checkin --- .github/workflows/compile.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index c2042b080..b1652f9cb 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -35,6 +35,8 @@ jobs: make -v ; \ which gmake ; \ export PATH=/opt/riscv/bin:${PATH} ; \ + riscv32-unknown-elf-gcc -march=rv32g_zbb -c -x c /dev/null ; \ + echo "return code: $?" ; \ make isa ; - name: Build and test simulators run: eval $(opam env) && test/run_tests.sh From 073bdf07a6cd123d23a49ce7a72261848516abf2 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 19:39:05 -0500 Subject: [PATCH 15/51] intermediate checkin --- .github/workflows/compile.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index b1652f9cb..bb97deb60 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -35,6 +35,7 @@ jobs: make -v ; \ which gmake ; \ export PATH=/opt/riscv/bin:${PATH} ; \ + echo "PATH: ${PATH}" ; \ riscv32-unknown-elf-gcc -march=rv32g_zbb -c -x c /dev/null ; \ echo "return code: $?" ; \ make isa ; From 918db78b4f5956925e5973ec4eece1a9d6d5aea0 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 19:45:08 -0500 Subject: [PATCH 16/51] intermediate checkin --- .github/workflows/compile.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index bb97deb60..7e7025388 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -36,6 +36,7 @@ jobs: which gmake ; \ export PATH=/opt/riscv/bin:${PATH} ; \ echo "PATH: ${PATH}" ; \ + ls -l /opt/riscv/bin ; \ riscv32-unknown-elf-gcc -march=rv32g_zbb -c -x c /dev/null ; \ echo "return code: $?" ; \ make isa ; From 4ea23e46d89d22db8a1fa56a08ffa5c2e25d49b1 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 19:55:45 -0500 Subject: [PATCH 17/51] intermediate checkin --- .github/workflows/compile.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 7e7025388..11eb1aee7 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -19,13 +19,13 @@ jobs: - name: Install sail run: opam install -y sail - name: Download RISC-V toolchain (32-bit) - run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz + run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv32-elf-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz - name: Install RISC-V toolchain (32-bit) - run: sudo tar xvfz riscv32-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt + run: sudo tar xvfz riscv32-elf-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Download RISC-V toolchain (64-bit) - run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz + run: wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz - name: Install RISC-V toolchain (64-bit) - run: sudo tar xvfz riscv64-glibc-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt + run: sudo tar xvfz riscv64-elf-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz --directory /opt - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ From ed3497b122ffd416722b05e2179840c54b7ddc63 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 20:41:36 -0500 Subject: [PATCH 18/51] intermediate checkin --- .github/workflows/compile.yml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 11eb1aee7..084072a2b 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,25 +29,31 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ + git checkout riscv-tests-sail ; \ echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ - make -v ; \ - which gmake ; \ export PATH=/opt/riscv/bin:${PATH} ; \ - echo "PATH: ${PATH}" ; \ - ls -l /opt/riscv/bin ; \ - riscv32-unknown-elf-gcc -march=rv32g_zbb -c -x c /dev/null ; \ - echo "return code: $?" ; \ make isa ; - name: Build and test simulators run: eval $(opam env) && test/run_tests.sh + - name: Build and test simulators (new method) + run: | + eval $(opam env) ; \ + cd TEST_DIR_ROOT/riscv_tests.git ; \ + ../../bin/run_tests.py --outfile=tests_new.xml --32bit=yes --64bit=yes --c_sim=yes --ocaml_sim=no --sailcov=no --clean_build=yes --test_switch_pyfile=test_command_line_switch.py --test_ignore_pyfile=test_ignore_list.py - name: Upload test results if: always() uses: actions/upload-artifact@v4 with: name: tests.xml path: test/tests.xml + - name: Upload test results (new) + if: always() + uses: actions/upload-artifact@v4 + with: + name: tests_new.xml + path: TEST_DIR_ROOT/riscv_test.git/tests_new.xml - name: Upload event payload if: always() uses: actions/upload-artifact@v4 From b4459747a1a4217418bc71ca68c52e77df0dcc5d Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 20:54:44 -0500 Subject: [PATCH 19/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 084072a2b..dc51d3d0a 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,7 +29,7 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ - git checkout riscv-tests-sail ; \ + git checkout --track origin/riscv-tests-sail ; \ echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ From 82d992c2fad62a4d7c77d97a1817fe46c103140c Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 21:03:13 -0500 Subject: [PATCH 20/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index dc51d3d0a..72d4e9063 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,7 +29,7 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ - git checkout --track origin/riscv-tests-sail ; \ + git checkout -b sail-tests-sail --track remotes/origin/riscv-tests-sail ; \ echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ From e6a1559d795858d7f637cfe9df445bf0c9415f51 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 21:14:47 -0500 Subject: [PATCH 21/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 72d4e9063..6938033c2 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,7 +29,7 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ - git checkout -b sail-tests-sail --track remotes/origin/riscv-tests-sail ; \ + git checkout -b riscv-tests-sail --track remotes/origin/riscv-tests-sail ; \ echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ From 28756ca077cf92b010ad57a87a728d4881609a0f Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Wed, 1 May 2024 21:38:59 -0500 Subject: [PATCH 22/51] intermediate checkin --- .github/workflows/compile.yml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 6938033c2..2b76b7900 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -12,6 +12,11 @@ jobs: uses: actions/checkout@HEAD with: submodules: recursive + - name: Update submodule branch + run : | + git config --file=.gitmodules submodule.TEST_DIR_ROOT/riscv_tests.git.branch riscv-tests-sail ; \ + git submodule sync ; \ + git submodule update --init --recursive --remote - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always - name: Init opam @@ -29,7 +34,7 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ - git checkout -b riscv-tests-sail --track remotes/origin/riscv-tests-sail ; \ + git checkout -b riscv-tests-sail remotes/origin/riscv-tests-sail ; \ echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ From 275d29df9919328120b24eeccda36cf9cae1be29 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:14:37 -0500 Subject: [PATCH 23/51] intermediate checkin --- .github/workflows/compile.yml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 2b76b7900..ae1c88ab1 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -13,10 +13,14 @@ jobs: with: submodules: recursive - name: Update submodule branch +# run : | +# git config --file=.gitmodules submodule.TEST_DIR_ROOT/riscv_tests.git.branch riscv-tests-sail ; \ +# git submodule sync ; \ +# git submodule update --init --recursive --remote run : | - git config --file=.gitmodules submodule.TEST_DIR_ROOT/riscv_tests.git.branch riscv-tests-sail ; \ - git submodule sync ; \ - git submodule update --init --recursive --remote + cd TES_DIR_ROOT/riscv_tests.git ; \ + git fetch ; \ + git checkout riscv-tests-sail ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always - name: Init opam From 0c5ab9a9839f959ce67db6df8c8a84440094f99e Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:15:45 -0500 Subject: [PATCH 24/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index ae1c88ab1..fb01073f5 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -18,7 +18,7 @@ jobs: # git submodule sync ; \ # git submodule update --init --recursive --remote run : | - cd TES_DIR_ROOT/riscv_tests.git ; \ + cd TEST_DIR_ROOT/riscv_tests.git ; \ git fetch ; \ git checkout riscv-tests-sail ; - name: Ensure pre-commit checks pass From 819084dd5ff12311f28c4dee6959514e39eafb7c Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:21:00 -0500 Subject: [PATCH 25/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index fb01073f5..e3df1802c 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -20,7 +20,7 @@ jobs: run : | cd TEST_DIR_ROOT/riscv_tests.git ; \ git fetch ; \ - git checkout riscv-tests-sail ; + git checkout -b riscv-tests-sail ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always - name: Init opam From 8f5a8096a2ed445fa350079ef9dde811883c9d30 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:23:03 -0500 Subject: [PATCH 26/51] intermediate checkin --- .github/workflows/compile.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index e3df1802c..f1938b127 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -20,7 +20,8 @@ jobs: run : | cd TEST_DIR_ROOT/riscv_tests.git ; \ git fetch ; \ - git checkout -b riscv-tests-sail ; + git checkout -b riscv-tests-sail ; \ + ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always - name: Init opam From 6d956a130c74420b5dc8d049a62b3a995c456edf Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:25:18 -0500 Subject: [PATCH 27/51] intermediate checkin --- .github/workflows/compile.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index f1938b127..bc9c763fc 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -20,7 +20,7 @@ jobs: run : | cd TEST_DIR_ROOT/riscv_tests.git ; \ git fetch ; \ - git checkout -b riscv-tests-sail ; \ + git checkout -t riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always @@ -39,7 +39,6 @@ jobs: - name: Build RISC-V testsuite run: | cd TEST_DIR_ROOT/riscv_tests.git ; \ - git checkout -b riscv-tests-sail remotes/origin/riscv-tests-sail ; \ echo ${PWD} ; ls ; \ autoconf ; \ ./configure --prefix=${PWD}/target ; \ From afc6c02f59aac40901a2fc5235fe7bd5393879d1 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:43:41 -0500 Subject: [PATCH 28/51] intermediate checkin --- .github/workflows/compile.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index bc9c763fc..7fe54a3e8 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -19,8 +19,7 @@ jobs: # git submodule update --init --recursive --remote run : | cd TEST_DIR_ROOT/riscv_tests.git ; \ - git fetch ; \ - git checkout -t riscv-tests-sail ; \ + git checkout -b riscv-tests-sail remotes/origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From 947e68f1064e5f4d67a9b2a00be1078827a0d2a8 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:52:12 -0500 Subject: [PATCH 29/51] intermediate checkin --- .github/workflows/compile.yml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 7fe54a3e8..da254c596 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -18,8 +18,11 @@ jobs: # git submodule sync ; \ # git submodule update --init --recursive --remote run : | - cd TEST_DIR_ROOT/riscv_tests.git ; \ - git checkout -b riscv-tests-sail remotes/origin/riscv-tests-sail ; \ + cd TEST_DIR_ROOT/ ; \ + git clone + git clone git@github.com:riscv-software-src/riscv-tests.git riscv-tests ; \ + cd riscv-tests ; \ + git checkout -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From 63f46c0018aa83e3e0b56e14f5416df185dc1c8c Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:53:10 -0500 Subject: [PATCH 30/51] intermediate checkin --- .github/workflows/compile.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index da254c596..2cb8185b9 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -19,7 +19,6 @@ jobs: # git submodule update --init --recursive --remote run : | cd TEST_DIR_ROOT/ ; \ - git clone git clone git@github.com:riscv-software-src/riscv-tests.git riscv-tests ; \ cd riscv-tests ; \ git checkout -t origin/riscv-tests-sail ; \ From 54914041649bb088ce4cd19cae30da5254473866 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:55:48 -0500 Subject: [PATCH 31/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 2cb8185b9..3d6aa56ae 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -19,7 +19,7 @@ jobs: # git submodule update --init --recursive --remote run : | cd TEST_DIR_ROOT/ ; \ - git clone git@github.com:riscv-software-src/riscv-tests.git riscv-tests ; \ + git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ cd riscv-tests ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; From 7b6d5d14fa6953c2d186c9bdf2a5fbed5c2565ed Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:58:20 -0500 Subject: [PATCH 32/51] intermediate checkin --- .github/workflows/compile.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 3d6aa56ae..197cfdd55 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -18,9 +18,9 @@ jobs: # git submodule sync ; \ # git submodule update --init --recursive --remote run : | - cd TEST_DIR_ROOT/ ; \ - git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ - cd riscv-tests ; \ + cd TEST_DIR_ROOT/riscv_tests.git ; \ +# git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ +# cd riscv-tests ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass From 75b0efd049c356f7a242610413402f798ee64b1e Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 12:59:30 -0500 Subject: [PATCH 33/51] intermediate checkin --- .github/workflows/compile.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 197cfdd55..6e64781c4 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -17,10 +17,10 @@ jobs: # git config --file=.gitmodules submodule.TEST_DIR_ROOT/riscv_tests.git.branch riscv-tests-sail ; \ # git submodule sync ; \ # git submodule update --init --recursive --remote - run : | - cd TEST_DIR_ROOT/riscv_tests.git ; \ # git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ # cd riscv-tests ; \ + run : | + cd TEST_DIR_ROOT/riscv_tests.git ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass From 7dff9493c140f44883a1ceb5452afce73fe2efa5 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 15:55:32 -0500 Subject: [PATCH 34/51] intermediate checkin --- .github/workflows/compile.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 6e64781c4..350ea3cd6 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -20,7 +20,9 @@ jobs: # git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ # cd riscv-tests ; \ run : | - cd TEST_DIR_ROOT/riscv_tests.git ; \ + cd TEST_DIR_ROOT/ ; \ + ln -s riscv_tests.git riscv_tests; \ + cd riscv_tests ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass From d504105d59911543f84a952c24301ad7d0b0b144 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 15:59:57 -0500 Subject: [PATCH 35/51] intermediate checkin --- .github/workflows/compile.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 350ea3cd6..dce6a24bc 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -23,7 +23,9 @@ jobs: cd TEST_DIR_ROOT/ ; \ ln -s riscv_tests.git riscv_tests; \ cd riscv_tests ; \ - git checkout -t origin/riscv-tests-sail ; \ + ls -l ; + git fetch --all ; \ + git checkout -b riscv-tests-sail origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From bf59991a846a18c950cb48d4c355d69da0616d3e Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 16:02:24 -0500 Subject: [PATCH 36/51] intermediate checkin --- .github/workflows/compile.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index dce6a24bc..828983e73 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -25,6 +25,7 @@ jobs: cd riscv_tests ; \ ls -l ; git fetch --all ; \ + git branch --all ; \ git checkout -b riscv-tests-sail origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass From 739a0fb49327b14f632e3cfedf74096be299b126 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 16:12:02 -0500 Subject: [PATCH 37/51] intermediate checkin --- .github/workflows/compile.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 828983e73..75d990162 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -23,6 +23,7 @@ jobs: cd TEST_DIR_ROOT/ ; \ ln -s riscv_tests.git riscv_tests; \ cd riscv_tests ; \ + git branch --all ; \ ls -l ; git fetch --all ; \ git branch --all ; \ From c9c6c283615421506b43b91e328ddc7230a3487b Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 16:19:07 -0500 Subject: [PATCH 38/51] intermediate checkin --- .github/workflows/compile.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 75d990162..75676ad62 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -11,7 +11,8 @@ jobs: - name: Check out repository code uses: actions/checkout@HEAD with: - submodules: recursive +# submodules: recursive + submodules: true - name: Update submodule branch # run : | # git config --file=.gitmodules submodule.TEST_DIR_ROOT/riscv_tests.git.branch riscv-tests-sail ; \ From 7fa1d3b93a52c39a97f68567c3d89d969549e007 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 16:26:47 -0500 Subject: [PATCH 39/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 75676ad62..1b7159eab 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -28,7 +28,7 @@ jobs: ls -l ; git fetch --all ; \ git branch --all ; \ - git checkout -b riscv-tests-sail origin/riscv-tests-sail ; \ + git checkout -b riscv-tests-sail --track origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From 0980beb486955c70aac6789bcd8562f7881ae19d Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Thu, 2 May 2024 16:41:34 -0500 Subject: [PATCH 40/51] removed branch specifier --- .gitmodules | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 27727d20b..3b6218f0d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +1,3 @@ [submodule "TEST_DIR_ROOT/riscv_tests.git"] path = TEST_DIR_ROOT/riscv_tests.git url = git@github.com:riscv-software-src/riscv-tests.git - branch = riscv-tests-sail From 805755df37ff8da997f05829300b2e36bb847e1d Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 09:12:19 -0500 Subject: [PATCH 41/51] intermediate checkin --- .github/workflows/compile.yml | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 1b7159eab..b0fc9f2a3 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -22,13 +22,10 @@ jobs: # cd riscv-tests ; \ run : | cd TEST_DIR_ROOT/ ; \ - ln -s riscv_tests.git riscv_tests; \ - cd riscv_tests ; \ - git branch --all ; \ + cd riscv_tests.git ; \ + git branch -r ; \ ls -l ; - git fetch --all ; \ - git branch --all ; \ - git checkout -b riscv-tests-sail --track origin/riscv-tests-sail ; \ + git checkout riscv-tests-sail -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From d29664e3a6bb3868de34c5fe8a799cf4412d39d0 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 09:22:12 -0500 Subject: [PATCH 42/51] intermediate checkin --- .github/workflows/compile.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index b0fc9f2a3..74dd9afc5 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -11,8 +11,8 @@ jobs: - name: Check out repository code uses: actions/checkout@HEAD with: -# submodules: recursive - submodules: true + submodules: recursive +# submodules: true - name: Update submodule branch # run : | # git config --file=.gitmodules submodule.TEST_DIR_ROOT/riscv_tests.git.branch riscv-tests-sail ; \ @@ -21,6 +21,7 @@ jobs: # git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ # cd riscv-tests ; \ run : | + git branch ; \ cd TEST_DIR_ROOT/ ; \ cd riscv_tests.git ; \ git branch -r ; \ From d1c83fa1a1edfc4dfd50bbc6d6f2f00b7a3483d3 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 09:24:51 -0500 Subject: [PATCH 43/51] intermediate checkin --- .github/workflows/compile.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 74dd9afc5..7b6bee0fe 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -24,9 +24,10 @@ jobs: git branch ; \ cd TEST_DIR_ROOT/ ; \ cd riscv_tests.git ; \ - git branch -r ; \ + echo $PWD ; \ ls -l ; - git checkout riscv-tests-sail -t origin/riscv-tests-sail ; \ + git branch -r ; \ + git checkout -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From 07a642abdba93d600383324784eab638002d8a87 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 09:36:29 -0500 Subject: [PATCH 44/51] intermediate checkin --- .github/workflows/compile.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 7b6bee0fe..22ae207ec 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -26,6 +26,7 @@ jobs: cd riscv_tests.git ; \ echo $PWD ; \ ls -l ; + cat .gitmodules ; \ git branch -r ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; From 158246a8ea74ed74acc32bb1c8482c54df67f8a8 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 09:39:25 -0500 Subject: [PATCH 45/51] intermediate checkin --- .github/workflows/compile.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 22ae207ec..506534a22 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -21,9 +21,11 @@ jobs: # git clone https://github.com/riscv-software-src/riscv-tests.git riscv-tests ; \ # cd riscv-tests ; \ run : | + echo $PWD ; \ + cat .gitmodules ; \ git branch ; \ - cd TEST_DIR_ROOT/ ; \ - cd riscv_tests.git ; \ + git branch -r ; \ + cd TEST_DIR_ROOT/riscv_tests.git ; \ echo $PWD ; \ ls -l ; cat .gitmodules ; \ From 22125c2d837b23ace199bd62b6f2fbae6a177e9c Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 09:53:42 -0500 Subject: [PATCH 46/51] intermediate checkin --- .github/workflows/compile.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 506534a22..e3422230f 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -28,7 +28,6 @@ jobs: cd TEST_DIR_ROOT/riscv_tests.git ; \ echo $PWD ; \ ls -l ; - cat .gitmodules ; \ git branch -r ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; From 980a386cd86a7197f134a3530df30a85850fc80f Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 10:16:59 -0500 Subject: [PATCH 47/51] intermediate checkin --- .github/workflows/compile.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index e3422230f..de821c57a 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -28,6 +28,7 @@ jobs: cd TEST_DIR_ROOT/riscv_tests.git ; \ echo $PWD ; \ ls -l ; + git remote add origin git@github.com:riscv-software-src/riscv-tests.git ; \ git branch -r ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; From 1111c65a39692bca0580919675229c9e5e47c51e Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 10:19:16 -0500 Subject: [PATCH 48/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index de821c57a..014a9fbef 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -28,7 +28,7 @@ jobs: cd TEST_DIR_ROOT/riscv_tests.git ; \ echo $PWD ; \ ls -l ; - git remote add origin git@github.com:riscv-software-src/riscv-tests.git ; \ + git remote add origin2 git@github.com:riscv-software-src/riscv-tests.git ; \ git branch -r ; \ git checkout -t origin/riscv-tests-sail ; \ ls -l ; From 8f09b79f24a8e7ec654c77a37138a3730120bc4d Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 10:21:42 -0500 Subject: [PATCH 49/51] intermediate checkin --- .github/workflows/compile.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 014a9fbef..33064fa4a 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,8 +29,8 @@ jobs: echo $PWD ; \ ls -l ; git remote add origin2 git@github.com:riscv-software-src/riscv-tests.git ; \ - git branch -r ; \ - git checkout -t origin/riscv-tests-sail ; \ + git branch -a ; \ + git checkout -t origin2/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From 2bf4db4706304533db15650b010c00afdd9c3a51 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 10:40:51 -0500 Subject: [PATCH 50/51] intermediate checkin --- .github/workflows/compile.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 33064fa4a..54edaf24b 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -29,8 +29,9 @@ jobs: echo $PWD ; \ ls -l ; git remote add origin2 git@github.com:riscv-software-src/riscv-tests.git ; \ - git branch -a ; \ - git checkout -t origin2/riscv-tests-sail ; \ + git fetch --all + git branch --all ; \ + git checkout -t origin/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always From 835dd5a6bbd25034c1a3449e24e391cedac09293 Mon Sep 17 00:00:00 2001 From: William McSpaddden Date: Tue, 7 May 2024 10:42:27 -0500 Subject: [PATCH 51/51] intermediate checkin --- .github/workflows/compile.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index 54edaf24b..c880f135d 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -31,7 +31,7 @@ jobs: git remote add origin2 git@github.com:riscv-software-src/riscv-tests.git ; \ git fetch --all git branch --all ; \ - git checkout -t origin/riscv-tests-sail ; \ + git checkout -t origin2/riscv-tests-sail ; \ ls -l ; - name: Ensure pre-commit checks pass run: pip install pre-commit && pre-commit run --all-files --show-diff-on-failure --color=always