diff --git a/c_emulator/SoftFloat-3e/build/Linux-386-GCC/Makefile b/c_emulator/SoftFloat-3e/build/Linux-386-GCC/Makefile index 56c9bb016..418160051 100644 --- a/c_emulator/SoftFloat-3e/build/Linux-386-GCC/Makefile +++ b/c_emulator/SoftFloat-3e/build/Linux-386-GCC/Makefile @@ -166,12 +166,8 @@ OBJS_OTHERS = \ i64_to_f64$(OBJ) \ i64_to_extF80M$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -197,11 +193,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -227,7 +220,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -255,7 +247,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80M_to_ui32$(OBJ) \ extF80M_to_ui64$(OBJ) \ extF80M_to_i32$(OBJ) \ @@ -308,20 +299,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -332,9 +315,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile b/c_emulator/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile index 1bc4213b5..1cf6f5e1a 100644 --- a/c_emulator/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile +++ b/c_emulator/SoftFloat-3e/build/Linux-386-SSE2-GCC/Makefile @@ -166,12 +166,8 @@ OBJS_OTHERS = \ i64_to_f64$(OBJ) \ i64_to_extF80M$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -197,11 +193,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -227,7 +220,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -255,7 +247,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80M_to_ui32$(OBJ) \ extF80M_to_ui64$(OBJ) \ extF80M_to_i32$(OBJ) \ @@ -308,20 +299,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -332,9 +315,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile b/c_emulator/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile index 021841406..2565fe56c 100644 --- a/c_emulator/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile +++ b/c_emulator/SoftFloat-3e/build/Linux-ARM-VFPv2-GCC/Makefile @@ -164,12 +164,8 @@ OBJS_OTHERS = \ i64_to_f64$(OBJ) \ i64_to_extF80M$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -195,11 +191,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -225,7 +218,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -253,7 +245,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80M_to_ui32$(OBJ) \ extF80M_to_ui64$(OBJ) \ extF80M_to_i32$(OBJ) \ @@ -306,20 +297,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -330,9 +313,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Linux-RISCV-GCC/Makefile b/c_emulator/SoftFloat-3e/build/Linux-RISCV-GCC/Makefile index 3289aa5e7..c8965c8b6 100644 --- a/c_emulator/SoftFloat-3e/build/Linux-RISCV-GCC/Makefile +++ b/c_emulator/SoftFloat-3e/build/Linux-RISCV-GCC/Makefile @@ -163,12 +163,8 @@ OBJS_OTHERS = \ i64_to_extF80M$(OBJ) \ i64_to_f128$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -196,11 +192,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -228,7 +221,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -258,7 +250,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80_to_ui32$(OBJ) \ extF80_to_ui64$(OBJ) \ extF80_to_i32$(OBJ) \ @@ -364,20 +355,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -388,9 +371,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile b/c_emulator/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile index a43fc3ab9..76e2af933 100644 --- a/c_emulator/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile +++ b/c_emulator/SoftFloat-3e/build/Linux-x86_64-GCC/Makefile @@ -172,12 +172,8 @@ OBJS_OTHERS = \ i64_to_extF80M$(OBJ) \ i64_to_f128$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -205,11 +201,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -237,7 +230,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -267,7 +259,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80_to_ui32$(OBJ) \ extF80_to_ui64$(OBJ) \ extF80_to_i32$(OBJ) \ @@ -373,15 +364,7 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ @@ -397,9 +380,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Win32-MinGW/Makefile b/c_emulator/SoftFloat-3e/build/Win32-MinGW/Makefile index 56c9bb016..418160051 100644 --- a/c_emulator/SoftFloat-3e/build/Win32-MinGW/Makefile +++ b/c_emulator/SoftFloat-3e/build/Win32-MinGW/Makefile @@ -166,12 +166,8 @@ OBJS_OTHERS = \ i64_to_f64$(OBJ) \ i64_to_extF80M$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -197,11 +193,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -227,7 +220,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -255,7 +247,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80M_to_ui32$(OBJ) \ extF80M_to_ui64$(OBJ) \ extF80M_to_i32$(OBJ) \ @@ -308,20 +299,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -332,9 +315,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile b/c_emulator/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile index 1bc4213b5..1cf6f5e1a 100644 --- a/c_emulator/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile +++ b/c_emulator/SoftFloat-3e/build/Win32-SSE2-MinGW/Makefile @@ -166,12 +166,8 @@ OBJS_OTHERS = \ i64_to_f64$(OBJ) \ i64_to_extF80M$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -197,11 +193,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -227,7 +220,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -255,7 +247,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80M_to_ui32$(OBJ) \ extF80M_to_ui64$(OBJ) \ extF80M_to_i32$(OBJ) \ @@ -308,20 +299,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -332,9 +315,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/Win64-MinGW-w64/Makefile b/c_emulator/SoftFloat-3e/build/Win64-MinGW-w64/Makefile index 05f3696c6..c612c0985 100644 --- a/c_emulator/SoftFloat-3e/build/Win64-MinGW-w64/Makefile +++ b/c_emulator/SoftFloat-3e/build/Win64-MinGW-w64/Makefile @@ -172,12 +172,8 @@ OBJS_OTHERS = \ i64_to_extF80M$(OBJ) \ i64_to_f128$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -205,11 +201,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -237,7 +230,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -267,7 +259,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80_to_ui32$(OBJ) \ extF80_to_ui64$(OBJ) \ extF80_to_i32$(OBJ) \ @@ -373,15 +364,7 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ @@ -397,9 +380,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/template-FAST_INT64/Makefile b/c_emulator/SoftFloat-3e/build/template-FAST_INT64/Makefile index 630538d9b..9691a69c5 100644 --- a/c_emulator/SoftFloat-3e/build/template-FAST_INT64/Makefile +++ b/c_emulator/SoftFloat-3e/build/template-FAST_INT64/Makefile @@ -173,12 +173,8 @@ OBJS_OTHERS = \ i64_to_extF80M$(OBJ) \ i64_to_f128$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -206,11 +202,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -238,7 +231,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -268,7 +260,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80_to_ui32$(OBJ) \ extF80_to_ui64$(OBJ) \ extF80_to_i32$(OBJ) \ @@ -374,15 +365,7 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ @@ -398,9 +381,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/build/template-not-FAST_INT64/Makefile b/c_emulator/SoftFloat-3e/build/template-not-FAST_INT64/Makefile index c4f353259..49fddfd02 100644 --- a/c_emulator/SoftFloat-3e/build/template-not-FAST_INT64/Makefile +++ b/c_emulator/SoftFloat-3e/build/template-not-FAST_INT64/Makefile @@ -166,12 +166,8 @@ OBJS_OTHERS = \ i64_to_f64$(OBJ) \ i64_to_extF80M$(OBJ) \ i64_to_f128M$(OBJ) \ - f16_to_ui8$(OBJ) \ - f16_to_ui16$(OBJ) \ f16_to_ui32$(OBJ) \ f16_to_ui64$(OBJ) \ - f16_to_i8$(OBJ) \ - f16_to_i16$(OBJ) \ f16_to_i32$(OBJ) \ f16_to_i64$(OBJ) \ f16_to_ui32_r_minMag$(OBJ) \ @@ -197,11 +193,8 @@ OBJS_OTHERS = \ f16_le_quiet$(OBJ) \ f16_lt_quiet$(OBJ) \ f16_isSignalingNaN$(OBJ) \ - f16_classify$(OBJ) \ - f32_to_ui16$(OBJ) \ f32_to_ui32$(OBJ) \ f32_to_ui64$(OBJ) \ - f32_to_i16$(OBJ) \ f32_to_i32$(OBJ) \ f32_to_i64$(OBJ) \ f32_to_ui32_r_minMag$(OBJ) \ @@ -227,7 +220,6 @@ OBJS_OTHERS = \ f32_le_quiet$(OBJ) \ f32_lt_quiet$(OBJ) \ f32_isSignalingNaN$(OBJ) \ - f32_classify$(OBJ) \ f64_to_ui32$(OBJ) \ f64_to_ui64$(OBJ) \ f64_to_i32$(OBJ) \ @@ -255,7 +247,6 @@ OBJS_OTHERS = \ f64_le_quiet$(OBJ) \ f64_lt_quiet$(OBJ) \ f64_isSignalingNaN$(OBJ) \ - f64_classify$(OBJ) \ extF80M_to_ui32$(OBJ) \ extF80M_to_ui64$(OBJ) \ extF80M_to_i32$(OBJ) \ @@ -308,20 +299,12 @@ OBJS_OTHERS = \ f128M_le_quiet$(OBJ) \ f128M_lt_quiet$(OBJ) \ -OBJS_RECIPROCAL = \ - f16_rsqrte7$(OBJ) \ - f16_recip7$(OBJ) \ - f32_rsqrte7$(OBJ) \ - f32_recip7$(OBJ) \ - f64_rsqrte7$(OBJ) \ - f64_recip7$(OBJ) \ - -OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL) +OBJS_ALL = $(OBJS_PRIMITIVES) $(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_ALL): \ $(OTHER_HEADERS) platform.h $(SOURCE_DIR)/include/primitiveTypes.h \ $(SOURCE_DIR)/include/primitives.h -$(OBJS_SPECIALIZE) $(OBJS_OTHERS) $(OBJS_RECIPROCAL): \ +$(OBJS_SPECIALIZE) $(OBJS_OTHERS): \ $(SOURCE_DIR)/include/softfloat_types.h $(SOURCE_DIR)/include/internals.h \ $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/specialize.h \ $(SOURCE_DIR)/include/softfloat.h @@ -332,9 +315,6 @@ $(OBJS_PRIMITIVES) $(OBJS_OTHERS): %$(OBJ): $(SOURCE_DIR)/%.c $(OBJS_SPECIALIZE): %$(OBJ): $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/%.c $(COMPILE_C) $(SOURCE_DIR)/$(SPECIALIZE_TYPE)/$*.c -$(OBJS_RECIPROCAL): %$(OBJ): $(SOURCE_DIR)/fall_reciprocal.c - $(COMPILE_C) $(SOURCE_DIR)/fall_reciprocal.c - softfloat$(LIB): $(OBJS_ALL) $(DELETE) $@ $(MAKELIB) $^ diff --git a/c_emulator/SoftFloat-3e/source/8086-SSE/specialize.h b/c_emulator/SoftFloat-3e/source/8086-SSE/specialize.h index 4b31dc56b..5fe119a1e 100644 --- a/c_emulator/SoftFloat-3e/source/8086-SSE/specialize.h +++ b/c_emulator/SoftFloat-3e/source/8086-SSE/specialize.h @@ -51,20 +51,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | The values to return on conversions to 32-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui8_fromPosOverflow 0xFF -#define ui8_fromNegOverflow 0 -#define ui8_fromNaN 0xFF -#define i8_fromPosOverflow 0x7F -#define i8_fromNegOverflow (-0x7F - 1) -#define i8_fromNaN 0x7F - -#define ui16_fromPosOverflow 0xFFFF -#define ui16_fromNegOverflow 0 -#define ui16_fromNaN 0xFFFF -#define i16_fromPosOverflow 0x7FFF -#define i16_fromNegOverflow (-0x7FFF - 1) -#define i16_fromNaN 0x7FFF - #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0xFFFFFFFF #define ui32_fromNaN 0xFFFFFFFF diff --git a/c_emulator/SoftFloat-3e/source/8086/specialize.h b/c_emulator/SoftFloat-3e/source/8086/specialize.h index 4b31dc56b..5fe119a1e 100644 --- a/c_emulator/SoftFloat-3e/source/8086/specialize.h +++ b/c_emulator/SoftFloat-3e/source/8086/specialize.h @@ -51,20 +51,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | The values to return on conversions to 32-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui8_fromPosOverflow 0xFF -#define ui8_fromNegOverflow 0 -#define ui8_fromNaN 0xFF -#define i8_fromPosOverflow 0x7F -#define i8_fromNegOverflow (-0x7F - 1) -#define i8_fromNaN 0x7F - -#define ui16_fromPosOverflow 0xFFFF -#define ui16_fromNegOverflow 0 -#define ui16_fromNaN 0xFFFF -#define i16_fromPosOverflow 0x7FFF -#define i16_fromNegOverflow (-0x7FFF - 1) -#define i16_fromNaN 0x7FFF - #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0xFFFFFFFF #define ui32_fromNaN 0xFFFFFFFF diff --git a/c_emulator/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h b/c_emulator/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h index 593ef4ff5..2c481a259 100644 --- a/c_emulator/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h +++ b/c_emulator/SoftFloat-3e/source/ARM-VFPv2-defaultNaN/specialize.h @@ -51,20 +51,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | The values to return on conversions to 32-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui8_fromPosOverflow 0xFF -#define ui8_fromNegOverflow 0 -#define ui8_fromNaN 0xFF -#define i8_fromPosOverflow 0x7F -#define i8_fromNegOverflow (-0x7F - 1) -#define i8_fromNaN 0x7F - -#define ui16_fromPosOverflow 0xFFFF -#define ui16_fromNegOverflow 0 -#define ui16_fromNaN 0xFFFF -#define i16_fromPosOverflow 0x7FFF -#define i16_fromNegOverflow (-0x7FFF - 1) -#define i16_fromNaN 0x7FFF - #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0 #define ui32_fromNaN 0 diff --git a/c_emulator/SoftFloat-3e/source/ARM-VFPv2/specialize.h b/c_emulator/SoftFloat-3e/source/ARM-VFPv2/specialize.h index 6e9060bc1..5321f33bc 100644 --- a/c_emulator/SoftFloat-3e/source/ARM-VFPv2/specialize.h +++ b/c_emulator/SoftFloat-3e/source/ARM-VFPv2/specialize.h @@ -51,20 +51,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | The values to return on conversions to 32-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui8_fromPosOverflow 0xFF -#define ui8_fromNegOverflow 0 -#define ui8_fromNaN 0xFF -#define i8_fromPosOverflow 0x7F -#define i8_fromNegOverflow (-0x7F - 1) -#define i8_fromNaN 0x7F - -#define ui16_fromPosOverflow 0xFFFF -#define ui16_fromNegOverflow 0 -#define ui16_fromNaN 0xFFFF -#define i16_fromPosOverflow 0x7FFF -#define i16_fromNegOverflow (-0x7FFF - 1) -#define i16_fromNaN 0x7FFF - #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0 #define ui32_fromNaN 0 diff --git a/c_emulator/SoftFloat-3e/source/RISCV/specialize.h b/c_emulator/SoftFloat-3e/source/RISCV/specialize.h index fbf1e2ba9..509c241ee 100644 --- a/c_emulator/SoftFloat-3e/source/RISCV/specialize.h +++ b/c_emulator/SoftFloat-3e/source/RISCV/specialize.h @@ -51,20 +51,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | The values to return on conversions to 32-bit integer formats that raise an | invalid exception. *----------------------------------------------------------------------------*/ -#define ui8_fromPosOverflow 0xFF -#define ui8_fromNegOverflow 0 -#define ui8_fromNaN 0xFF -#define i8_fromPosOverflow 0x7F -#define i8_fromNegOverflow (-0x7F - 1) -#define i8_fromNaN 0x7F - -#define ui16_fromPosOverflow 0xFFFF -#define ui16_fromNegOverflow 0 -#define ui16_fromNaN 0xFFFF -#define i16_fromPosOverflow 0x7FFF -#define i16_fromNegOverflow (-0x7FFF - 1) -#define i16_fromNaN 0x7FFF - #define ui32_fromPosOverflow 0xFFFFFFFF #define ui32_fromNegOverflow 0 #define ui32_fromNaN 0xFFFFFFFF diff --git a/c_emulator/SoftFloat-3e/source/f16_classify.c b/c_emulator/SoftFloat-3e/source/f16_classify.c deleted file mode 100755 index 9402ff13e..000000000 --- a/c_emulator/SoftFloat-3e/source/f16_classify.c +++ /dev/null @@ -1,36 +0,0 @@ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast16_t f16_classify( float16_t a ) -{ - union ui16_f16 uA; - uint_fast16_t uiA; - - uA.f = a; - uiA = uA.ui; - - uint_fast16_t infOrNaN = expF16UI( uiA ) == 0x1F; - uint_fast16_t subnormalOrZero = expF16UI( uiA ) == 0; - bool sign = signF16UI( uiA ); - bool fracZero = fracF16UI( uiA ) == 0; - bool isNaN = isNaNF16UI( uiA ); - bool isSNaN = softfloat_isSigNaNF16UI( uiA ); - - return - ( sign && infOrNaN && fracZero ) << 0 | - ( sign && !infOrNaN && !subnormalOrZero ) << 1 | - ( sign && subnormalOrZero && !fracZero ) << 2 | - ( sign && subnormalOrZero && fracZero ) << 3 | - ( !sign && infOrNaN && fracZero ) << 7 | - ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | - ( !sign && subnormalOrZero && !fracZero ) << 5 | - ( !sign && subnormalOrZero && fracZero ) << 4 | - ( isNaN && isSNaN ) << 8 | - ( isNaN && !isSNaN ) << 9; -} - diff --git a/c_emulator/SoftFloat-3e/source/f16_to_i16.c b/c_emulator/SoftFloat-3e/source/f16_to_i16.c deleted file mode 100644 index 66fdbfa7a..000000000 --- a/c_emulator/SoftFloat-3e/source/f16_to_i16.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "specialize.h" -#include "softfloat.h" - -int_fast16_t f16_to_i16( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast8_t old_flags = softfloat_exceptionFlags; - - int_fast32_t sig32 = f16_to_i32(a, roundingMode, exact); - - if (sig32 > INT16_MAX) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return i16_fromPosOverflow; - } else if (sig32 < INT16_MIN) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return i16_fromNegOverflow; - } else { - return sig32; - } -} diff --git a/c_emulator/SoftFloat-3e/source/f16_to_i8.c b/c_emulator/SoftFloat-3e/source/f16_to_i8.c deleted file mode 100644 index a82c5ff2a..000000000 --- a/c_emulator/SoftFloat-3e/source/f16_to_i8.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "specialize.h" -#include "softfloat.h" - -int_fast8_t f16_to_i8( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast8_t old_flags = softfloat_exceptionFlags; - - int_fast32_t sig32 = f16_to_i32(a, roundingMode, exact); - - if (sig32 > INT8_MAX) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return i8_fromPosOverflow; - } else if (sig32 < INT8_MIN) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return i8_fromNegOverflow; - } else { - return sig32; - } -} diff --git a/c_emulator/SoftFloat-3e/source/f16_to_ui16.c b/c_emulator/SoftFloat-3e/source/f16_to_ui16.c deleted file mode 100644 index 2054e4f06..000000000 --- a/c_emulator/SoftFloat-3e/source/f16_to_ui16.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "specialize.h" -#include "softfloat.h" - -uint_fast16_t f16_to_ui16( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast8_t old_flags = softfloat_exceptionFlags; - - uint_fast32_t sig32 = f16_to_ui32(a, roundingMode, exact); - - if (sig32 > UINT16_MAX) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return ui16_fromPosOverflow; - } else { - return sig32; - } -} diff --git a/c_emulator/SoftFloat-3e/source/f16_to_ui8.c b/c_emulator/SoftFloat-3e/source/f16_to_ui8.c deleted file mode 100644 index 6ce158557..000000000 --- a/c_emulator/SoftFloat-3e/source/f16_to_ui8.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "specialize.h" -#include "softfloat.h" - -uint_fast8_t f16_to_ui8( float16_t a, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast8_t old_flags = softfloat_exceptionFlags; - - uint_fast32_t sig32 = f16_to_ui32(a, roundingMode, exact); - - if (sig32 > UINT8_MAX) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return ui8_fromPosOverflow; - } else { - return sig32; - } -} diff --git a/c_emulator/SoftFloat-3e/source/f32_classify.c b/c_emulator/SoftFloat-3e/source/f32_classify.c deleted file mode 100755 index 83fad878a..000000000 --- a/c_emulator/SoftFloat-3e/source/f32_classify.c +++ /dev/null @@ -1,36 +0,0 @@ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast16_t f32_classify( float32_t a ) -{ - union ui32_f32 uA; - uint_fast32_t uiA; - - uA.f = a; - uiA = uA.ui; - - uint_fast16_t infOrNaN = expF32UI( uiA ) == 0xFF; - uint_fast16_t subnormalOrZero = expF32UI( uiA ) == 0; - bool sign = signF32UI( uiA ); - bool fracZero = fracF32UI( uiA ) == 0; - bool isNaN = isNaNF32UI( uiA ); - bool isSNaN = softfloat_isSigNaNF32UI( uiA ); - - return - ( sign && infOrNaN && fracZero ) << 0 | - ( sign && !infOrNaN && !subnormalOrZero ) << 1 | - ( sign && subnormalOrZero && !fracZero ) << 2 | - ( sign && subnormalOrZero && fracZero ) << 3 | - ( !sign && infOrNaN && fracZero ) << 7 | - ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | - ( !sign && subnormalOrZero && !fracZero ) << 5 | - ( !sign && subnormalOrZero && fracZero ) << 4 | - ( isNaN && isSNaN ) << 8 | - ( isNaN && !isSNaN ) << 9; -} - diff --git a/c_emulator/SoftFloat-3e/source/f32_to_i16.c b/c_emulator/SoftFloat-3e/source/f32_to_i16.c deleted file mode 100644 index b23231a1f..000000000 --- a/c_emulator/SoftFloat-3e/source/f32_to_i16.c +++ /dev/null @@ -1,56 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "specialize.h" -#include "softfloat.h" - -int_fast16_t f32_to_i16( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast8_t old_flags = softfloat_exceptionFlags; - - int_fast32_t sig32 = f32_to_i32(a, roundingMode, exact); - - if (sig32 > INT16_MAX) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return i16_fromPosOverflow; - } else if (sig32 < INT16_MIN) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return i16_fromNegOverflow; - } else { - return sig32; - } -} diff --git a/c_emulator/SoftFloat-3e/source/f32_to_ui16.c b/c_emulator/SoftFloat-3e/source/f32_to_ui16.c deleted file mode 100644 index 073492bfa..000000000 --- a/c_emulator/SoftFloat-3e/source/f32_to_ui16.c +++ /dev/null @@ -1,53 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the -University of California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include "specialize.h" -#include "softfloat.h" - -uint_fast16_t f32_to_ui16( float32_t a, uint_fast8_t roundingMode, bool exact ) -{ - uint_fast8_t old_flags = softfloat_exceptionFlags; - - uint_fast32_t sig32 = f32_to_ui32(a, roundingMode, exact); - - if (sig32 > UINT16_MAX) { - softfloat_exceptionFlags = old_flags | softfloat_flag_invalid; - return ui16_fromPosOverflow; - } else { - return sig32; - } -} diff --git a/c_emulator/SoftFloat-3e/source/f64_classify.c b/c_emulator/SoftFloat-3e/source/f64_classify.c deleted file mode 100755 index 180abde3c..000000000 --- a/c_emulator/SoftFloat-3e/source/f64_classify.c +++ /dev/null @@ -1,36 +0,0 @@ - -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -uint_fast16_t f64_classify( float64_t a ) -{ - union ui64_f64 uA; - uint_fast64_t uiA; - - uA.f = a; - uiA = uA.ui; - - uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF; - uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0; - bool sign = signF64UI( uiA ); - bool fracZero = fracF64UI( uiA ) == 0; - bool isNaN = isNaNF64UI( uiA ); - bool isSNaN = softfloat_isSigNaNF64UI( uiA ); - - return - ( sign && infOrNaN && fracZero ) << 0 | - ( sign && !infOrNaN && !subnormalOrZero ) << 1 | - ( sign && subnormalOrZero && !fracZero ) << 2 | - ( sign && subnormalOrZero && fracZero ) << 3 | - ( !sign && infOrNaN && fracZero ) << 7 | - ( !sign && !infOrNaN && !subnormalOrZero ) << 6 | - ( !sign && subnormalOrZero && !fracZero ) << 5 | - ( !sign && subnormalOrZero && fracZero ) << 4 | - ( isNaN && isSNaN ) << 8 | - ( isNaN && !isSNaN ) << 9; -} - diff --git a/c_emulator/SoftFloat-3e/source/fall_reciprocal.c b/c_emulator/SoftFloat-3e/source/fall_reciprocal.c deleted file mode 100755 index 1c9645893..000000000 --- a/c_emulator/SoftFloat-3e/source/fall_reciprocal.c +++ /dev/null @@ -1,392 +0,0 @@ - -/*============================================================================ - -This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic -Package, Release 3d, by John R. Hauser. - -Copyright 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of -California. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions, and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions, and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - 3. Neither the name of the University nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY -EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -=============================================================================*/ - -#include -#include -#include -#include "platform.h" -#include "internals.h" -#include "specialize.h" -#include "softfloat.h" - -static inline uint64_t extract64(uint64_t val, int pos, int len) -{ - assert(pos >= 0 && len > 0 && len <= 64 - pos); - return (val >> pos) & (~UINT64_C(0) >> (64 - len)); -} - -static inline uint64_t make_mask64(int pos, int len) -{ - assert(pos >= 0 && len > 0 && pos < 64 && len <= 64); - return (UINT64_MAX >> (64 - len)) << pos; -} - -//user needs to truncate output to required length -static inline uint64_t rsqrte7(uint64_t val, int e, int s, bool sub) { - uint64_t exp = extract64(val, s, e); - uint64_t sig = extract64(val, 0, s); - uint64_t sign = extract64(val, s + e, 1); - const int p = 7; - - static const uint8_t table[] = { - 52, 51, 50, 48, 47, 46, 44, 43, - 42, 41, 40, 39, 38, 36, 35, 34, - 33, 32, 31, 30, 30, 29, 28, 27, - 26, 25, 24, 23, 23, 22, 21, 20, - 19, 19, 18, 17, 16, 16, 15, 14, - 14, 13, 12, 12, 11, 10, 10, 9, - 9, 8, 7, 7, 6, 6, 5, 4, - 4, 3, 3, 2, 2, 1, 1, 0, - 127, 125, 123, 121, 119, 118, 116, 114, - 113, 111, 109, 108, 106, 105, 103, 102, - 100, 99, 97, 96, 95, 93, 92, 91, - 90, 88, 87, 86, 85, 84, 83, 82, - 80, 79, 78, 77, 76, 75, 74, 73, - 72, 71, 70, 70, 69, 68, 67, 66, - 65, 64, 63, 63, 62, 61, 60, 59, - 59, 58, 57, 56, 56, 55, 54, 53}; - - if (sub) { - while (extract64(sig, s - 1, 1) == 0) - exp--, sig <<= 1; - - sig = (sig << 1) & make_mask64(0 ,s); - } - - int idx = ((exp & 1) << (p-1)) | (sig >> (s-p+1)); - uint64_t out_sig = (uint64_t)(table[idx]) << (s-p); - uint64_t out_exp = (3 * make_mask64(0, e - 1) + ~exp) / 2; - - return (sign << (s+e)) | (out_exp << s) | out_sig; -} - -float16_t f16_rsqrte7(float16_t in) -{ - union ui16_f16 uA; - - uA.f = in; - unsigned int ret = f16_classify(in); - bool sub = false; - switch(ret) { - case 0x001: // -inf - case 0x002: // -normal - case 0x004: // -subnormal - case 0x100: // sNaN - softfloat_exceptionFlags |= softfloat_flag_invalid; - case 0x200: //qNaN - uA.ui = defaultNaNF16UI; - break; - case 0x008: // -0 - uA.ui = 0xfc00; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x010: // +0 - uA.ui = 0x7c00; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x080: //+inf - uA.ui = 0x0; - break; - case 0x020: //+ sub - sub = true; - default: // +num - uA.ui = rsqrte7(uA.ui, 5, 10, sub); - break; - } - - return uA.f; -} - -float32_t f32_rsqrte7(float32_t in) -{ - union ui32_f32 uA; - - uA.f = in; - unsigned int ret = f32_classify(in); - bool sub = false; - switch(ret) { - case 0x001: // -inf - case 0x002: // -normal - case 0x004: // -subnormal - case 0x100: // sNaN - softfloat_exceptionFlags |= softfloat_flag_invalid; - case 0x200: //qNaN - uA.ui = defaultNaNF32UI; - break; - case 0x008: // -0 - uA.ui = 0xff800000; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x010: // +0 - uA.ui = 0x7f800000; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x080: //+inf - uA.ui = 0x0; - break; - case 0x020: //+ sub - sub = true; - default: // +num - uA.ui = rsqrte7(uA.ui, 8, 23, sub); - break; - } - - return uA.f; -} - -float64_t f64_rsqrte7(float64_t in) -{ - union ui64_f64 uA; - - uA.f = in; - unsigned int ret = f64_classify(in); - bool sub = false; - switch(ret) { - case 0x001: // -inf - case 0x002: // -normal - case 0x004: // -subnormal - case 0x100: // sNaN - softfloat_exceptionFlags |= softfloat_flag_invalid; - case 0x200: //qNaN - uA.ui = defaultNaNF64UI; - break; - case 0x008: // -0 - uA.ui = 0xfff0000000000000ul; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x010: // +0 - uA.ui = 0x7ff0000000000000ul; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x080: //+inf - uA.ui = 0x0; - break; - case 0x020: //+ sub - sub = true; - default: // +num - uA.ui = rsqrte7(uA.ui, 11, 52, sub); - break; - } - - return uA.f; -} - -//user needs to truncate output to required length -static inline uint64_t recip7(uint64_t val, int e, int s, int rm, bool sub, - bool *round_abnormal) -{ - uint64_t exp = extract64(val, s, e); - uint64_t sig = extract64(val, 0, s); - uint64_t sign = extract64(val, s + e, 1); - const int p = 7; - - static const uint8_t table[] = { - 127, 125, 123, 121, 119, 117, 116, 114, - 112, 110, 109, 107, 105, 104, 102, 100, - 99, 97, 96, 94, 93, 91, 90, 88, - 87, 85, 84, 83, 81, 80, 79, 77, - 76, 75, 74, 72, 71, 70, 69, 68, - 66, 65, 64, 63, 62, 61, 60, 59, - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, - 42, 41, 40, 40, 39, 38, 37, 36, - 35, 35, 34, 33, 32, 31, 31, 30, - 29, 28, 28, 27, 26, 25, 25, 24, - 23, 23, 22, 21, 21, 20, 19, 19, - 18, 17, 17, 16, 15, 15, 14, 14, - 13, 12, 12, 11, 11, 10, 9, 9, - 8, 8, 7, 7, 6, 5, 5, 4, - 4, 3, 3, 2, 2, 1, 1, 0}; - - if (sub) { - while (extract64(sig, s - 1, 1) == 0) - exp--, sig <<= 1; - - sig = (sig << 1) & make_mask64(0 ,s); - - if (exp != 0 && exp != UINT64_MAX) { - *round_abnormal = true; - if (rm == 1 || - (rm == 2 && !sign) || - (rm == 3 && sign)) - return ((sign << (s+e)) | make_mask64(s, e)) - 1; - else - return (sign << (s+e)) | make_mask64(s, e); - } - } - - int idx = sig >> (s-p); - uint64_t out_sig = (uint64_t)(table[idx]) << (s-p); - uint64_t out_exp = 2 * make_mask64(0, e - 1) + ~exp; - if (out_exp == 0 || out_exp == UINT64_MAX) { - out_sig = (out_sig >> 1) | make_mask64(s - 1, 1); - if (out_exp == UINT64_MAX) { - out_sig >>= 1; - out_exp = 0; - } - } - - return (sign << (s+e)) | (out_exp << s) | out_sig; -} - -float16_t f16_recip7(float16_t in) -{ - union ui16_f16 uA; - - uA.f = in; - unsigned int ret = f16_classify(in); - bool sub = false; - bool round_abnormal = false; - switch(ret) { - case 0x001: // -inf - uA.ui = 0x8000; - break; - case 0x080: //+inf - uA.ui = 0x0; - break; - case 0x008: // -0 - uA.ui = 0xfc00; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x010: // +0 - uA.ui = 0x7c00; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x100: // sNaN - softfloat_exceptionFlags |= softfloat_flag_invalid; - case 0x200: //qNaN - uA.ui = defaultNaNF16UI; - break; - case 0x004: // -subnormal - case 0x020: //+ sub - sub = true; - default: // +- normal - uA.ui = recip7(uA.ui, 5, 10, - softfloat_roundingMode, sub, &round_abnormal); - if (round_abnormal) - softfloat_exceptionFlags |= softfloat_flag_inexact | - softfloat_flag_overflow; - break; - } - - return uA.f; -} - -float32_t f32_recip7(float32_t in) -{ - union ui32_f32 uA; - - uA.f = in; - unsigned int ret = f32_classify(in); - bool sub = false; - bool round_abnormal = false; - switch(ret) { - case 0x001: // -inf - uA.ui = 0x80000000; - break; - case 0x080: //+inf - uA.ui = 0x0; - break; - case 0x008: // -0 - uA.ui = 0xff800000; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x010: // +0 - uA.ui = 0x7f800000; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x100: // sNaN - softfloat_exceptionFlags |= softfloat_flag_invalid; - case 0x200: //qNaN - uA.ui = defaultNaNF32UI; - break; - case 0x004: // -subnormal - case 0x020: //+ sub - sub = true; - default: // +- normal - uA.ui = recip7(uA.ui, 8, 23, - softfloat_roundingMode, sub, &round_abnormal); - if (round_abnormal) - softfloat_exceptionFlags |= softfloat_flag_inexact | - softfloat_flag_overflow; - break; - } - - return uA.f; -} - -float64_t f64_recip7(float64_t in) -{ - union ui64_f64 uA; - - uA.f = in; - unsigned int ret = f64_classify(in); - bool sub = false; - bool round_abnormal = false; - switch(ret) { - case 0x001: // -inf - uA.ui = 0x8000000000000000; - break; - case 0x080: //+inf - uA.ui = 0x0; - break; - case 0x008: // -0 - uA.ui = 0xfff0000000000000; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x010: // +0 - uA.ui = 0x7ff0000000000000; - softfloat_exceptionFlags |= softfloat_flag_infinite; - break; - case 0x100: // sNaN - softfloat_exceptionFlags |= softfloat_flag_invalid; - case 0x200: //qNaN - uA.ui = defaultNaNF64UI; - break; - case 0x004: // -subnormal - case 0x020: //+ sub - sub = true; - default: // +- normal - uA.ui = recip7(uA.ui, 11, 52, - softfloat_roundingMode, sub, &round_abnormal); - if (round_abnormal) - softfloat_exceptionFlags |= softfloat_flag_inexact | - softfloat_flag_overflow; - break; - } - - return uA.f; -} diff --git a/c_emulator/SoftFloat-3e/source/include/softfloat.h b/c_emulator/SoftFloat-3e/source/include/softfloat.h index a284fdc3a..b33374cd6 100644 --- a/c_emulator/SoftFloat-3e/source/include/softfloat.h +++ b/c_emulator/SoftFloat-3e/source/include/softfloat.h @@ -137,12 +137,8 @@ void i64_to_f128M( int64_t, float128_t * ); /*---------------------------------------------------------------------------- | 16-bit (half-precision) floating-point operations. *----------------------------------------------------------------------------*/ -uint_fast8_t f16_to_ui8( float16_t, uint_fast8_t, bool ); -uint_fast16_t f16_to_ui16( float16_t, uint_fast8_t, bool ); uint_fast32_t f16_to_ui32( float16_t, uint_fast8_t, bool ); uint_fast64_t f16_to_ui64( float16_t, uint_fast8_t, bool ); -int_fast8_t f16_to_i8( float16_t, uint_fast8_t, bool ); -int_fast16_t f16_to_i16( float16_t, uint_fast8_t, bool ); int_fast32_t f16_to_i32( float16_t, uint_fast8_t, bool ); int_fast64_t f16_to_i64( float16_t, uint_fast8_t, bool ); uint_fast32_t f16_to_ui32_r_minMag( float16_t, bool ); @@ -172,17 +168,12 @@ bool f16_eq_signaling( float16_t, float16_t ); bool f16_le_quiet( float16_t, float16_t ); bool f16_lt_quiet( float16_t, float16_t ); bool f16_isSignalingNaN( float16_t ); -uint_fast16_t f16_classify( float16_t ); -float16_t f16_rsqrte7( float16_t ); -float16_t f16_recip7( float16_t ); /*---------------------------------------------------------------------------- | 32-bit (single-precision) floating-point operations. *----------------------------------------------------------------------------*/ -uint_fast16_t f32_to_ui16( float32_t, uint_fast8_t, bool ); uint_fast32_t f32_to_ui32( float32_t, uint_fast8_t, bool ); uint_fast64_t f32_to_ui64( float32_t, uint_fast8_t, bool ); -int_fast16_t f32_to_i16( float32_t, uint_fast8_t, bool ); int_fast32_t f32_to_i32( float32_t, uint_fast8_t, bool ); int_fast64_t f32_to_i64( float32_t, uint_fast8_t, bool ); uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool ); @@ -212,9 +203,6 @@ bool f32_eq_signaling( float32_t, float32_t ); bool f32_le_quiet( float32_t, float32_t ); bool f32_lt_quiet( float32_t, float32_t ); bool f32_isSignalingNaN( float32_t ); -uint_fast16_t f32_classify( float32_t ); -float32_t f32_rsqrte7( float32_t ); -float32_t f32_recip7( float32_t ); /*---------------------------------------------------------------------------- | 64-bit (double-precision) floating-point operations. @@ -250,9 +238,6 @@ bool f64_eq_signaling( float64_t, float64_t ); bool f64_le_quiet( float64_t, float64_t ); bool f64_lt_quiet( float64_t, float64_t ); bool f64_isSignalingNaN( float64_t ); -uint_fast16_t f64_classify( float64_t ); -float64_t f64_rsqrte7( float64_t ); -float64_t f64_recip7( float64_t ); /*---------------------------------------------------------------------------- | Rounding precision for 80-bit extended double-precision floating-point. diff --git a/c_emulator/riscv_softfloat.c b/c_emulator/riscv_softfloat.c index 6834afc28..e9992a38d 100644 --- a/c_emulator/riscv_softfloat.c +++ b/c_emulator/riscv_softfloat.c @@ -251,177 +251,9 @@ unit softfloat_f64sqrt(mach_bits rm, mach_bits v) { return UNIT; } -unit softfloat_f16rsqrte7(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float16_t a, res; - a.v = v; - res = f16_rsqrte7(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f32rsqrte7(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float32_t a, res; - a.v = v; - res = f32_rsqrte7(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f64rsqrte7(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float64_t a, res; - a.v = v; - res = f64_rsqrte7(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f16recip7(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float16_t a, res; - a.v = v; - res = f16_recip7(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f32recip7(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float32_t a, res; - a.v = v; - res = f32_recip7(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f64recip7(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float64_t a, res; - a.v = v; - res = f64_recip7(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f16class(mach_bits v) { - SOFTFLOAT_PRELUDE(0); - - float16_t a; - float64_t res; - a.v = v; - res.v = f16_classify(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f32class(mach_bits v) { - SOFTFLOAT_PRELUDE(0); - - float32_t a; - float64_t res; - a.v = v; - res.v = f32_classify(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f64class(mach_bits v) { - SOFTFLOAT_PRELUDE(0); - - float64_t a, res; - a.v = v; - res.v = f64_classify(a); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - // The boolean 'true' argument in the conversion calls below selects // 'exact' conversion, which sets the Inexact exception flag if // needed. -unit softfloat_f16toi8(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float16_t a; - int_fast8_t res; - uint_fast8_t rm8 = uint8_of_rm(rm); - a.v = v; - res = f16_to_i8(a, rm8, true); - - zfloat_result = res; - zfloat_fflags |= (mach_bits) softfloat_exceptionFlags; - - return UNIT; -} - -unit softfloat_f16toui8(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float16_t a; - uint_fast8_t res; - uint_fast8_t rm8 = uint8_of_rm(rm); - a.v = v; - res = f16_to_ui8(a, rm8, true); - - zfloat_result = res; - zfloat_fflags |= (mach_bits) softfloat_exceptionFlags; - - return UNIT; -} - -unit softfloat_f16toi16(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float16_t a; - float16_t res; - uint_fast8_t rm8 = uint8_of_rm(rm); - a.v = v; - res.v = f16_to_i8(a, rm8, true); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f16toui16(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float16_t a; - float16_t res; - uint_fast8_t rm8 = uint8_of_rm(rm); - a.v = v; - res.v = f16_to_ui8(a, rm8, true); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - unit softfloat_f16toi32(mach_bits rm, mach_bits v) { SOFTFLOAT_PRELUDE(rm); @@ -478,34 +310,6 @@ unit softfloat_f16toui64(mach_bits rm, mach_bits v) { return UNIT; } -unit softfloat_f32toi16(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float32_t a; - float16_t res; - uint_fast8_t rm8 = uint8_of_rm(rm); - a.v = v; - res.v = f32_to_i16(a, rm8, true); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - -unit softfloat_f32toui16(mach_bits rm, mach_bits v) { - SOFTFLOAT_PRELUDE(rm); - - float32_t a; - float16_t res; - uint_fast8_t rm8 = uint8_of_rm(rm); - a.v = v; - res.v = f32_to_ui16(a, rm8, true); - - SOFTFLOAT_POSTLUDE(res); - - return UNIT; -} - unit softfloat_f32toi32(mach_bits rm, mach_bits v) { SOFTFLOAT_PRELUDE(rm); diff --git a/c_emulator/riscv_softfloat.h b/c_emulator/riscv_softfloat.h index 3af149011..39a541799 100644 --- a/c_emulator/riscv_softfloat.h +++ b/c_emulator/riscv_softfloat.h @@ -23,29 +23,11 @@ unit softfloat_f16sqrt(mach_bits rm, mach_bits v); unit softfloat_f32sqrt(mach_bits rm, mach_bits v); unit softfloat_f64sqrt(mach_bits rm, mach_bits v); -unit softfloat_f16toi8(mach_bits rm, mach_bits v); -unit softfloat_f16toui8(mach_bits rm, mach_bits v); -unit softfloat_f16toi16(mach_bits rm, mach_bits v); -unit softfloat_f16toui16(mach_bits rm, mach_bits v); unit softfloat_f16toi32(mach_bits rm, mach_bits v); unit softfloat_f16toui32(mach_bits rm, mach_bits v); unit softfloat_f16toi64(mach_bits rm, mach_bits v); unit softfloat_f16toui64(mach_bits rm, mach_bits v); -unit softfloat_f16rsqrte7(mach_bits rm, mach_bits v); -unit softfloat_f32rsqrte7(mach_bits rm, mach_bits v); -unit softfloat_f64rsqrte7(mach_bits rm, mach_bits v); - -unit softfloat_f16recip7(mach_bits rm, mach_bits v); -unit softfloat_f32recip7(mach_bits rm, mach_bits v); -unit softfloat_f64recip7(mach_bits rm, mach_bits v); - -unit softfloat_f16class(mach_bits v); -unit softfloat_f32class(mach_bits v); -unit softfloat_f64class(mach_bits v); - -unit softfloat_f32toi16(mach_bits rm, mach_bits v); -unit softfloat_f32toui16(mach_bits rm, mach_bits v); unit softfloat_f32toi32(mach_bits rm, mach_bits v); unit softfloat_f32toui32(mach_bits rm, mach_bits v); unit softfloat_f32toi64(mach_bits rm, mach_bits v); diff --git a/handwritten_support/0.11/riscv_extras_fdext.lem b/handwritten_support/0.11/riscv_extras_fdext.lem index 04c6785c0..ef70b1583 100644 --- a/handwritten_support/0.11/riscv_extras_fdext.lem +++ b/handwritten_support/0.11/riscv_extras_fdext.lem @@ -66,45 +66,6 @@ let softfloat_f32_sqrt _ _ = () val softfloat_f64_sqrt : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit let softfloat_f64_sqrt _ _ = () -val softfloat_f16_rsqrte7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_rsqrte7 _ _ = () - -val softfloat_f32_rsqrte7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_rsqrte7 _ _ = () - -val softfloat_f64_rsqrte7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f64_rsqrte7 _ _ = () - -val softfloat_f16_recip7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_recip7 _ _ = () - -val softfloat_f32_recip7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_recip7 _ _ = () - -val softfloat_f64_recip7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f64_recip7 _ _ = () - -val softfloat_f16_class : forall 's. Size 's => bitvector 's -> unit -let softfloat_f16_class _ = () - -val softfloat_f32_class : forall 's. Size 's => bitvector 's -> unit -let softfloat_f32_class _ = () - -val softfloat_f64_class : forall 's. Size 's => bitvector 's -> unit -let softfloat_f64_class _ = () - - -val softfloat_f16_to_i8: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_i8 _ _ = () - -val softfloat_f16_to_ui8: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_ui8 _ _ = () - -val softfloat_f16_to_i16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_i16 _ _ = () - -val softfloat_f16_to_ui16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_ui16 _ _ = () val softfloat_f16_to_i32: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit let softfloat_f16_to_i32 _ _ = () @@ -131,12 +92,6 @@ val softfloat_ui64_to_f16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> let softfloat_ui64_to_f16 _ _ = () -val softfloat_f32_to_i16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_to_i16 _ _ = () - -val softfloat_f32_to_ui16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_to_ui16 _ _ = () - val softfloat_f32_to_i32: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit let softfloat_f32_to_i32 _ _ = () diff --git a/handwritten_support/riscv_extras_fdext.lem b/handwritten_support/riscv_extras_fdext.lem index ead2806ea..0ef766c67 100644 --- a/handwritten_support/riscv_extras_fdext.lem +++ b/handwritten_support/riscv_extras_fdext.lem @@ -134,45 +134,6 @@ let softfloat_f32_sqrt _ _ = () val softfloat_f64_sqrt : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit let softfloat_f64_sqrt _ _ = () -val softfloat_f16_rsqrte7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_rsqrte7 _ _ = () - -val softfloat_f32_rsqrte7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_rsqrte7 _ _ = () - -val softfloat_f64_rsqrte7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f64_rsqrte7 _ _ = () - -val softfloat_f16_recip7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_recip7 _ _ = () - -val softfloat_f32_recip7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_recip7 _ _ = () - -val softfloat_f64_recip7 : forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f64_recip7 _ _ = () - -val softfloat_f16_class : forall 's. Size 's => bitvector 's -> unit -let softfloat_f16_class _ = () - -val softfloat_f32_class : forall 's. Size 's => bitvector 's -> unit -let softfloat_f32_class _ = () - -val softfloat_f64_class : forall 's. Size 's => bitvector 's -> unit -let softfloat_f64_class _ = () - - -val softfloat_f16_to_i8: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_i8 _ _ = () - -val softfloat_f16_to_ui8: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_ui8 _ _ = () - -val softfloat_f16_to_i16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_i16 _ _ = () - -val softfloat_f16_to_ui16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f16_to_ui16 _ _ = () val softfloat_f16_to_i32: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit let softfloat_f16_to_i32 _ _ = () @@ -199,12 +160,6 @@ val softfloat_ui64_to_f16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> let softfloat_ui64_to_f16 _ _ = () -val softfloat_f32_to_i16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_to_i16 _ _ = () - -val softfloat_f32_to_ui16: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit -let softfloat_f32_to_ui16 _ _ = () - val softfloat_f32_to_i32: forall 'rm 's. Size 'rm, Size 's => bitvector 'rm -> bitvector 's -> unit let softfloat_f32_to_i32 _ _ = () diff --git a/model/prelude.sail b/model/prelude.sail index 8eb5efaf9..4ba0f0897 100644 --- a/model/prelude.sail +++ b/model/prelude.sail @@ -140,17 +140,7 @@ val xor_vec = {c: "xor_bits", _: "xor_vec"} : forall 'n. (bits('n), bits('n)) -> val int_power = {ocaml: "int_power", interpreter: "int_power", lem: "pow", coq: "pow", c: "pow_int"} : (int, int) -> int -val xor_bool : (bool, bool) -> bool -function xor_bool(b1, b2) = { - match (b1, b2) { - (false, false) => false, - (false, true) => true, - (true, false) => true, - (true, true) => false - } -} - -overload operator ^ = {xor_vec, int_power, concat_str, xor_bool} +overload operator ^ = {xor_vec, int_power, concat_str} val sub_vec = {c: "sub_bits", _: "sub_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) @@ -208,8 +198,11 @@ overload zeros = {zeros_implicit} val ones : forall 'n, 'n >= 0 . implicit('n) -> bits('n) function ones (n) = sail_ones (n) +val bool_to_bit : bool -> bit +function bool_to_bit x = if x then bitone else bitzero + val bool_to_bits : bool -> bits(1) -function bool_to_bits x = if x then 0b1 else 0b0 +function bool_to_bits x = [bool_to_bit(x)] val bit_to_bool : bit -> bool function bit_to_bool b = match b { @@ -217,12 +210,6 @@ function bit_to_bool b = match b { bitzero => false } -val bool_to_bit : bool -> bit -function bool_to_bit b = match b { - true => bitone, - false => bitzero -} - val to_bits : forall 'l, 'l >= 0.(atom('l), int) -> bits('l) function to_bits (l, n) = get_slice_int(l, n, 0) @@ -349,7 +336,7 @@ val "print_int" : (string, int) -> unit overload operator / = {quot_round_zero} overload operator * = {mult_atom, mult_int} -/* helper for vector extension +/* helper for vector extension * 1. EEW between 8 and 64 * 2. EMUL in vmvr.v instructions between 1 and 8 */ diff --git a/model/riscv_insts_vext_arith.sail b/model/riscv_insts_vext_arith.sail index 86e5da6df..0035e96c8 100644 --- a/model/riscv_insts_vext_arith.sail +++ b/model/riscv_insts_vext_arith.sail @@ -61,7 +61,7 @@ mapping encdec_vvfunct6 : vvfunct6 <-> bits(6) = { VV_VSADDU <-> 0b100000, VV_VSADD <-> 0b100001, VV_VSSUBU <-> 0b100010, - VV_VSSUB <-> 0b100011, + VV_VSSUB <-> 0b100011, VV_VSLL <-> 0b100101, VV_VSMUL <-> 0b100111, VV_VSRL <-> 0b101000, @@ -148,7 +148,7 @@ function clause execute(VVTYPE(funct6, vm, vs2, vs1, vd)) = { let idx = unsigned(vs1_val[i]); let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); assert(VLMAX <= 'n); - if idx < VLMAX then vs2_val[idx] else zeros() + if idx < VLMAX then vs2_val[idx] else zeros() }, VV_VRGATHEREI16 => { if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; @@ -157,14 +157,14 @@ function clause execute(VVTYPE(funct6, vm, vs2, vs1, vd)) = { let idx = unsigned(vs1_new[i]); let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); assert(VLMAX <= 'n); - if idx < VLMAX then vs2_val[idx] else zeros() + if idx < VLMAX then vs2_val[idx] else zeros() } } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -250,7 +250,7 @@ function clause execute(NVSTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -318,7 +318,7 @@ function clause execute(NVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -360,10 +360,9 @@ function clause execute(MASKTYPEV(vs2, vs1, vd)) = { if i < start_element then { result[i] = vd_val[i] } else if i > end_element | i >= real_num_elem then { - if tail_ag == UNDISTURBED then { - result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { - result[i] = vd_val[i] /* TODO: configuration support */ + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ } } else { /* the merge operates on all body elements */ @@ -372,7 +371,7 @@ function clause execute(MASKTYPEV(vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -408,7 +407,7 @@ function clause execute(MOVETYPEV(vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -518,7 +517,7 @@ function clause execute(VXTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -568,7 +567,7 @@ function clause execute(NXSTYPE(funct6, vm, vs2, rs1, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -603,7 +602,7 @@ function clause execute(NXSTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -635,7 +634,7 @@ function clause execute(NXTYPE(funct6, vm, vs2, rs1, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -657,11 +656,11 @@ function clause execute(NXTYPE(funct6, vm, vs2, rs1, vd)) = { let shift_amount = get_shift_amount(rs1_val, SEW_widen); let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); result[i] = match funct6 { - NX_VNCLIPU => { + NX_VNCLIPU => { let result_wide = (vs2_val[i] >> shift_amount) + EXTZ('o, rounding_incr); unsigned_saturation('m, result_wide) }, - NX_VNCLIP => { + NX_VNCLIP => { let v_double : bits('m * 4) = EXTS(vs2_val[i]); let result_wide = slice(v_double >> shift_amount, 0, 'o) + EXTZ('o, rounding_incr); signed_saturation('m, result_wide) @@ -671,7 +670,7 @@ function clause execute(NXTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -733,16 +732,16 @@ function clause execute(VXSG(funct6, vm, vs2, rs1, vd)) = { if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); assert(VLMAX > 0 & VLMAX <= 'n); - if rs1_val < VLMAX then vs2_val[rs1_val] else zeros() + if rs1_val < VLMAX then vs2_val[rs1_val] else zeros() } } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS -} +} mapping vxsg_mnemonic : vxsgfunct6 <-> string = { VX_VSLIDEUP <-> "vslideup.vx", @@ -783,10 +782,9 @@ function clause execute(MASKTYPEX(vs2, rs1, vd)) = { if i < start_element then { result[i] = vd_val[i] } else if i > end_element | i >= real_num_elem then { - if tail_ag == UNDISTURBED then { - result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { - result[i] = vd_val[i] /* TODO: configuration support */ + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ } } else { /* the merge operates on all body elements */ @@ -795,12 +793,12 @@ function clause execute(MASKTYPEX(vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } mapping clause assembly = MASKTYPEX(vs2, rs1, vd) - <-> "vmerge.vxm" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ "v0" + <-> "vmerge.vxm" ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ sep() ^ "v0" /* ********************** OPIVX (Integer Move Instruction) *********************** */ union clause ast = MOVETYPEX : (regidx, regidx) @@ -831,7 +829,7 @@ function clause execute(MOVETYPEX(rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -917,7 +915,7 @@ function clause execute(VITYPE(funct6, vm, vs2, simm, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -994,7 +992,7 @@ function clause execute(NISTYPE(funct6, vm, vs2, simm, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1004,7 +1002,7 @@ mapping nistype_mnemonic : nisfunct6 <-> string = { } mapping clause assembly = NISTYPE(funct6, vm, vs2, simm, vd) - <-> nistype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ maybe_vmask(vm) + <-> nistype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ hex_bits_5(simm) ^ maybe_vmask(vm) /* ************************** OPIVI (WITYPE Narrowing) *************************** */ /* *************** Vector Narrowing Fixed-Point Clip Instructions **************** */ @@ -1048,11 +1046,11 @@ function clause execute(NITYPE(funct6, vm, vs2, simm, vd)) = { let shift_amount = get_shift_amount(imm_val, SEW_widen); let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); result[i] = match funct6 { - NI_VNCLIPU => { + NI_VNCLIPU => { let result_wide = (vs2_val[i] >> shift_amount) + EXTZ('o, rounding_incr); unsigned_saturation('m, result_wide) }, - NI_VNCLIP => { + NI_VNCLIP => { let v_double : bits('m * 4) = EXTS(vs2_val[i]); let result_wide = slice(v_double >> shift_amount, 0, 'o) + EXTZ('o, rounding_incr); signed_saturation('m, result_wide) @@ -1062,7 +1060,7 @@ function clause execute(NITYPE(funct6, vm, vs2, simm, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1124,16 +1122,16 @@ function clause execute(VISG(funct6, vm, vs2, simm, vd)) = { if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); assert(VLMAX > 0 & VLMAX <= 'n); - if imm_val < VLMAX then vs2_val[imm_val] else zeros() + if imm_val < VLMAX then vs2_val[imm_val] else zeros() } } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS -} +} mapping visg_mnemonic : visgfunct6 <-> string = { VI_VSLIDEUP <-> "vslideup.vi", @@ -1174,10 +1172,9 @@ function clause execute(MASKTYPEI(vs2, simm, vd)) = { if i < start_element then { result[i] = vd_val[i] } else if i > end_element | i >= real_num_elem then { - if tail_ag == UNDISTURBED then { - result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { - result[i] = vd_val[i] /* TODO: configuration support */ + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ } } else { /* the merge operates on all body elements */ @@ -1186,7 +1183,7 @@ function clause execute(MASKTYPEI(vs2, simm, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1222,7 +1219,7 @@ function clause execute(MOVETYPEI(vd, simm)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1258,9 +1255,9 @@ function clause execute(VMVRTYPE(vs2, simm, vd)) = { }; write_vreg(num_elem, SEW, EMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS -} +} mapping simm_string : bits(5) <-> string = { 0b00000 <-> "1", @@ -1313,12 +1310,12 @@ function clause execute(MVVTYPE(funct6, vm, vs2, vs1, vd)) = { (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); foreach (i from 0 to (num_elem - 1)) { - if mask[i] then{ + if mask[i] then { result[i] = match funct6 { MVV_VAADDU => { let result_add = EXTZ('m + 1, vs2_val[i]) + EXTZ('m + 1, vs1_val[i]); let rounding_incr = get_fixed_rounding_incr(result_add, 1); - slice(result_add >> 1, 0, 'm) + EXTZ('m, rounding_incr) + slice(result_add >> 1, 0, 'm) + EXTZ('m, rounding_incr) }, MVV_VAADD => { let result_add = EXTS('m + 1, vs2_val[i]) + EXTS('m + 1, vs1_val[i]); @@ -1328,7 +1325,7 @@ function clause execute(MVVTYPE(funct6, vm, vs2, vs1, vd)) = { MVV_VASUBU => { let result_sub = EXTZ('m + 1, vs2_val[i]) - EXTZ('m + 1, vs1_val[i]); let rounding_incr = get_fixed_rounding_incr(result_sub, 1); - slice(result_sub >> 1, 0, 'm) + EXTZ('m, rounding_incr) + slice(result_sub >> 1, 0, 'm) + EXTZ('m, rounding_incr) }, MVV_VASUB => { let result_sub = EXTS('m + 1, vs2_val[i]) - EXTS('m + 1, vs1_val[i]); @@ -1337,7 +1334,7 @@ function clause execute(MVVTYPE(funct6, vm, vs2, vs1, vd)) = { }, MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), - MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), MVV_VDIVU => { let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); @@ -1366,7 +1363,7 @@ function clause execute(MVVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1421,8 +1418,8 @@ function clause execute(MVVMATYPE(funct6, vm, vs2, vs1, vd)) = { (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - foreach (i from 0 to (num_elem - 1)){ - if mask[i] then{ + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { result[i] = match funct6 { MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i], MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0), @@ -1433,7 +1430,7 @@ function clause execute(MVVMATYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1471,7 +1468,7 @@ function clause execute(WVVTYPE(funct6, vm, vs2, vs1, vd)) = { if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | - not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -1502,7 +1499,7 @@ function clause execute(WVVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1540,7 +1537,7 @@ function clause execute(WVTYPE(funct6, vm, vs2, vs1, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -1568,7 +1565,7 @@ function clause execute(WVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1603,8 +1600,8 @@ function clause execute(WMVVTYPE(funct6, vm, vs2, vs1, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | - not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -1624,14 +1621,14 @@ function clause execute(WMVVTYPE(funct6, vm, vs2, vs1, vd)) = { if mask[i] then { result[i] = match funct6 { WMVV_VWMACC => to_bits(SEW_widen, signed(vs1_val[i]) * signed(vs2_val[i])) + vd_val[i], - WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i], + WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i], WMVV_VWMACCSU => to_bits(SEW_widen, signed(vs1_val[i]) * unsigned(vs2_val[i]))+ vd_val[i] } } }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1664,7 +1661,7 @@ function clause execute(VEXT2TYPE(funct6, vm, vs2, vd)) = { let LMUL_pow_half = LMUL_pow - 1; if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | - not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) + not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -1690,7 +1687,7 @@ function clause execute(VEXT2TYPE(funct6, vm, vs2, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1748,7 +1745,7 @@ function clause execute(VEXT4TYPE(funct6, vm, vs2, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1806,7 +1803,7 @@ function clause execute(VEXT8TYPE(funct6, vm, vs2, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1838,7 +1835,7 @@ function clause execute(VMVXS(vs2, rd)) = { X(rd) = if sizeof(xlen) < SEW then slice(vs2_val[0], 0, sizeof(xlen)) else if sizeof(xlen) > SEW then EXTS(vs2_val[0]) else vs2_val[0]; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1887,15 +1884,16 @@ function clause execute(MVVCOMPRESS(vs2, vs1, vd)) = { if vd_idx < num_elem then { let tail_ag : agtype = get_vtype_vta(); let 'p = vd_idx; - if tail_ag == UNDISTURBED then { - foreach (i from 'p to (num_elem - 1)) result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { /* TODO: configuration support */ - foreach (i from 'p to (num_elem - 1)) result[i] = vd_val[i] + foreach (i from 'p to (num_elem - 1)) { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1923,7 +1921,7 @@ mapping encdec_mvxfunct6 : mvxfunct6 <-> bits(6) = { } mapping clause encdec = MVXTYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_mvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() + <-> encdec_mvxfunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() function clause execute(MVXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -1950,7 +1948,7 @@ function clause execute(MVXTYPE(funct6, vm, vs2, rs1, vd)) = { MVX_VAADDU => { let result_add = EXTZ('m + 1, vs2_val[i]) + EXTZ('m + 1, rs1_val); let rounding_incr = get_fixed_rounding_incr(result_add, 1); - slice(result_add >> 1, 0, 'm) + EXTZ('m, rounding_incr) + slice(result_add >> 1, 0, 'm) + EXTZ('m, rounding_incr) }, MVX_VAADD => { let result_add = EXTS('m + 1, vs2_val[i]) + EXTS('m + 1, rs1_val); @@ -1960,7 +1958,7 @@ function clause execute(MVXTYPE(funct6, vm, vs2, rs1, vd)) = { MVX_VASUBU => { let result_sub = EXTZ('m + 1, vs2_val[i]) - EXTZ('m + 1, rs1_val); let rounding_incr = get_fixed_rounding_incr(result_sub, 1); - slice(result_sub >> 1, 0, 'm) + EXTZ('m, rounding_incr) + slice(result_sub >> 1, 0, 'm) + EXTZ('m, rounding_incr) }, MVX_VASUB => { let result_sub = EXTS('m + 1, vs2_val[i]) - EXTS('m + 1, rs1_val); @@ -2007,7 +2005,7 @@ function clause execute(MVXTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -2029,7 +2027,7 @@ mapping mvxtype_mnemonic : mvxfunct6 <-> string = { } mapping clause assembly = MVXTYPE(funct6, vm, vs2, rs1, vd) - <-> mvxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm) + <-> mvxtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ reg_name(rs1) ^ maybe_vmask(vm) /* ************************* OPMVX (VXtype Multiply-Add) ************************* */ /* Multiply-Add instructions switch the order of source operands in assembly (vs1/rs1 before vs2) */ @@ -2043,7 +2041,7 @@ mapping encdec_mvxmafunct6 : mvxmafunct6 <-> bits(6) = { } mapping clause encdec = MVXMATYPE(funct6, vm, vs2, rs1, vd) if haveRVV() - <-> encdec_mvxmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() + <-> encdec_mvxmafunct6(funct6) @ vm @ vs2 @ rs1 @ 0b110 @ vd @ 0b1010111 if haveRVV() function clause execute(MVXMATYPE(funct6, vm, vs2, rs1, vd)) = { let SEW = get_sew(); @@ -2064,8 +2062,8 @@ function clause execute(MVXMATYPE(funct6, vm, vs2, rs1, vd)) = { (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); - foreach (i from 0 to (num_elem - 1)){ - if mask[i] then{ + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { result[i] = match funct6 { MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i], MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0), @@ -2076,7 +2074,7 @@ function clause execute(MVXMATYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -2145,7 +2143,7 @@ function clause execute(WVXTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -2182,7 +2180,7 @@ function clause execute(WXTYPE(funct6, vm, vs2, rs1, vd)) = { let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; - if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; let 'n = num_elem; @@ -2210,7 +2208,7 @@ function clause execute(WXTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -2274,7 +2272,7 @@ function clause execute(WMVXTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -2317,14 +2315,15 @@ function clause execute(VMVSX(rs1, vd)) = { /* others treated as tail elements */ let tail_ag : agtype = get_vtype_vta(); - if tail_ag == UNDISTURBED then { - foreach (i from 1 to (num_elem - 1)) result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { - foreach (i from 1 to (num_elem - 1)) result[i] = vd_val[i] /* TODO: configuration support */ + foreach (i from 1 to (num_elem - 1)) { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } }; write_vreg(num_elem, SEW, 0, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } diff --git a/model/riscv_insts_vext_fp.sail b/model/riscv_insts_vext_fp.sail index b2871f49b..e103437ea 100755 --- a/model/riscv_insts_vext_fp.sail +++ b/model/riscv_insts_vext_fp.sail @@ -75,7 +75,7 @@ function clause execute(FVVTYPE(funct6, vm, vs2, vs1, vd)) = { let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); - let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; @@ -98,7 +98,7 @@ function clause execute(FVVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -150,7 +150,7 @@ function clause execute(FVVMATYPE(funct6, vm, vs2, vs1, vd)) = { let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); - let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; @@ -167,12 +167,12 @@ function clause execute(FVVMATYPE(funct6, vm, vs2, vs1, vd)) = { FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) - } + } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -211,8 +211,8 @@ function clause execute(FWVVTYPE(funct6, vm, vs2, vs1, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | - not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); @@ -240,7 +240,7 @@ function clause execute(FWVVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -276,7 +276,7 @@ function clause execute(FWVVMATYPE(funct6, vm, vs1, vs2, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); @@ -306,7 +306,7 @@ function clause execute(FWVVMATYPE(funct6, vm, vs1, vs2, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -367,7 +367,7 @@ function clause execute(FWVTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -422,8 +422,8 @@ function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) }; - write_fflags(fflags); - elem + accrue_fflags(fflags); + elem }, FV_CVT_X_F => { let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { @@ -431,8 +431,8 @@ function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) }; - write_fflags(fflags); - elem + accrue_fflags(fflags); + elem }, FV_CVT_F_XU => { let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { @@ -450,7 +450,7 @@ function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) }; write_fflags(fflags); - elem + elem }, FV_CVT_RTZ_XU_F => { let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { @@ -458,7 +458,7 @@ function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { 32 => riscv_f32ToUi32(0b001, vs2_val[i]), 64 => riscv_f64ToUi64(0b001, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem }, FV_CVT_RTZ_X_F => { @@ -467,7 +467,7 @@ function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { 32 => riscv_f32ToI32(0b001, vs2_val[i]), 64 => riscv_f64ToI64(0b001, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem } } @@ -475,7 +475,7 @@ function clause execute(VFUNARY0(vm, vs2, vfunary0, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -542,7 +542,7 @@ function clause execute(VFWUNARY0(vm, vs2, vfwunary0, vd)) = { 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) }; write_fflags(fflags); - elem + elem }, FWV_CVT_X_F => { let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { @@ -603,7 +603,7 @@ function clause execute(VFWUNARY0(vm, vs2, vfwunary0, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -670,7 +670,7 @@ function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = { 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem }, FNV_CVT_X_F => { @@ -679,7 +679,7 @@ function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = { 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem }, FNV_CVT_F_XU => { @@ -724,7 +724,7 @@ function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = { 16 => riscv_f32ToUi16(0b001, vs2_val[i]), 32 => riscv_f64ToUi32(0b001, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem }, FNV_CVT_RTZ_X_F => { @@ -733,15 +733,15 @@ function clause execute(VFNUNARY0(vm, vs2, vfnunary0, vd)) = { 16 => riscv_f32ToI16(0b001, vs2_val[i]), 32 => riscv_f64ToI32(0b001, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem - } + } } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -779,6 +779,7 @@ function clause execute(VFUNARY1(vm, vs2, vfunary1, vd)) = { let num_elem = get_num_elem(LMUL_pow, SEW); if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); let 'n = num_elem; let 'm = SEW; @@ -809,7 +810,7 @@ function clause execute(VFUNARY1(vm, vs2, vfunary1, vd)) = { 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]), 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i]) }; - write_fflags(fflags); + accrue_fflags(fflags); elem }, FVV_VREC7 => { @@ -818,31 +819,23 @@ function clause execute(VFUNARY1(vm, vs2, vfunary1, vd)) = { 32 => riscv_f32Recip7(rm_3b, vs2_val[i]), 64 => riscv_f64Recip7(rm_3b, vs2_val[i]) }; - write_fflags(fflags); - elem - }, - FVV_VCLASS => { - let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { - 16 => riscv_f16Class(vs2_val[i]), - 32 => riscv_f32Class(vs2_val[i]), - 64 => riscv_f64Class(vs2_val[i]) - }; - write_fflags(fflags); + accrue_fflags(fflags); elem - } + }, + FVV_VCLASS => fp_class(vs2_val[i]) } } }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } mapping vfunary1_mnemonic : vfunary1 <-> string = { FVV_VSQRT <-> "vfsqrt.v", FVV_VRSQRT7 <-> "vfrsqrt7.v", - FVV_VREC7 <-> "vfrec7.v", + FVV_VREC7 <-> "vfrec7.v", FVV_VCLASS <-> "vfclass.v" } @@ -868,9 +861,8 @@ function clause execute(VFMVFS(vs2, rd)) = { let 'm = SEW; let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); - F(rd) = if sizeof(flen) == SEW then vs2_val[0] - else NaN_box(vs2_val[0]); - vstart = EXTZ(0b0); + F(rd) = nan_box_vector(vs2_val[0]); + vstart = zeros(); RETIRE_SUCCESS } @@ -915,7 +907,7 @@ function clause execute(FVFTYPE(funct6, vm, vs2, rs1, vd)) = { let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); - let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; @@ -949,7 +941,7 @@ function clause execute(FVFTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1005,7 +997,7 @@ function clause execute(FVFMATYPE(funct6, vm, vs2, rs1, vd)) = { let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); - let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); result : vector('n, dec, bits('m)) = undefined; mask : vector('n, dec, bool) = undefined; @@ -1027,7 +1019,7 @@ function clause execute(FVFMATYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1066,7 +1058,7 @@ function clause execute(FWVFTYPE(funct6, vm, vs2, rs1, vd)) = { let LMUL_pow_widen = LMUL_pow + 1; if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | - not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) then { handle_illegal(); return RETIRE_FAIL }; assert(SEW >= 16 & SEW_widen <= 64); @@ -1094,7 +1086,7 @@ function clause execute(FWVFTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1159,7 +1151,7 @@ function clause execute(FWVFMATYPE(funct6, vm, rs1, vs2, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1219,7 +1211,7 @@ function clause execute(FWFTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1264,10 +1256,9 @@ function clause execute(VFMERGE(vs2, rs1, vd)) = { if i < start_element then { result[i] = vd_val[i] } else if i > end_element | i >= real_num_elem then { - if tail_ag == UNDISTURBED then { - result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { - result[i] = vd_val[i] /* TODO: configuration support */ + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ } } else { /* the merge operates on all body elements */ @@ -1276,7 +1267,7 @@ function clause execute(VFMERGE(vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1315,7 +1306,7 @@ function clause execute(VFMV(rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1352,14 +1343,15 @@ function clause execute(VFMVSF(rs1, vd)) = { /* others treated as tail elements */ let tail_ag : agtype = get_vtype_vta(); - if tail_ag == UNDISTURBED then { - foreach (i from 1 to (num_elem - 1)) result[i] = vd_val[i] - } else if tail_ag == AGNOSTIC then { - foreach (i from 1 to (num_elem - 1)) result[i] = vd_val[i] /* TODO: configuration support */ + foreach (i from 1 to (num_elem - 1)) { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } }; write_vreg(num_elem, SEW, 0, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } diff --git a/model/riscv_insts_vext_mask.sail b/model/riscv_insts_vext_mask.sail index 5f1be7af6..53340956c 100755 --- a/model/riscv_insts_vext_mask.sail +++ b/model/riscv_insts_vext_mask.sail @@ -78,22 +78,21 @@ function clause execute(MMTYPE(funct6, vs2, vs1, vd)) = { foreach (i from 0 to (num_elem - 1)) { if mask[i] then { - let res : bool = match funct6 { + result[i] = match funct6 { MM_VMAND => vs2_val[i] & vs1_val[i], MM_VMNAND => not(vs2_val[i] & vs1_val[i]), MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), - MM_VMXOR => vs2_val[i] ^ vs1_val[i], + MM_VMXOR => vs2_val[i] != vs1_val[i], MM_VMOR => vs2_val[i] | vs1_val[i], MM_VMNOR => not(vs2_val[i] | vs1_val[i]), MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), - MM_VMXNOR => not(vs2_val[i] ^ vs1_val[i]) - }; - result[i] = res; + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } } }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -140,7 +139,7 @@ function clause execute(VCPOP_M(vm, vs2, rd)) = { }; X(rd) = to_bits(sizeof(xlen), count); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -178,7 +177,7 @@ function clause execute(VFIRST_M(vm, vs2, rd)) = { }; X(rd) = to_bits(sizeof(xlen), index); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -219,7 +218,7 @@ function clause execute(VMSBF_M(vm, vs2, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -260,7 +259,7 @@ function clause execute(VMSIF_M(vm, vs2, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -305,7 +304,7 @@ function clause execute(VMSOF_M(vm, vs2, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -346,7 +345,7 @@ function clause execute(VIOTA_M(vm, vs2, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -381,7 +380,7 @@ function clause execute(VID_V(vm, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } diff --git a/model/riscv_insts_vext_mem.sail b/model/riscv_insts_vext_mem.sail index 30ed6ac0b..8f0cbe809 100644 --- a/model/riscv_insts_vext_mem.sail +++ b/model/riscv_insts_vext_mem.sail @@ -53,14 +53,14 @@ mapping nfields_int : bits(3) <-> {|1, 2, 3, 4, 5, 6, 7, 8|} = { } mapping nfields_string : bits(3) <-> string = { - 0b000 <-> "1", - 0b001 <-> "2", - 0b010 <-> "3", - 0b011 <-> "4", - 0b100 <-> "5", - 0b101 <-> "6", - 0b110 <-> "7", - 0b111 <-> "8" + 0b000 <-> "", + 0b001 <-> "seg2", + 0b010 <-> "seg3", + 0b011 <-> "seg4", + 0b100 <-> "seg5", + 0b101 <-> "seg6", + 0b110 <-> "seg7", + 0b111 <-> "seg8" } mapping vlewidth_bitsnumberstr : vlewidth <-> string = { @@ -98,558 +98,7 @@ mapping bytes_wordwidth : {|1, 2, 4, 8|} <-> word_width = { 8 <-> DOUBLE } -/* ******************** Vector Load Unit-Stride Normal (nf=0, mop=0, lumop=0) ******************** */ -union clause ast = VLETYPE : (bits(1), regidx, vlewidth, regidx) - -mapping clause encdec = VLETYPE(vm, rs1, width, vd) if haveRVV() - <-> 0b000 @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() - -val process_vle : forall 'b 'n 'p, ('b in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vle (vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = { - let width_type : word_width = bytes_wordwidth(load_width_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vd_val : vector('n, dec, bits('b * 8)) = read_vreg(num_elem, load_width_bytes * 8, EMUL_pow, vd); - - let (total, mask) = init_masked_result(num_elem, load_width_bytes * 8, EMUL_pow, vd_val, vm_val); - - foreach (i from 0 to (num_elem - 1)) { - if mask[i] then { /* active elements */ - vstart = to_bits(16, i); - let elem_offset = i * load_width_bytes; - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width_type) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - TR_Address(paddr, _) => { - match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, result), - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - } - } - } - } - } else { /* prestart, masked or tail elements */ - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, total[i]) - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VLETYPE(vm, rs1, width, vd)) = { - let load_width_bytes = vlewidth_bytesnumber(width); - let EEW = load_width_bytes * 8; - let EEW_pow = vlewidth_pow(width); - let SEW_pow = get_sew_pow(); - let LMUL_pow = get_lmul_pow(); - let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; - let num_elem = get_num_elem(EMUL_pow, EEW); - - if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - - process_vle(vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) -} - -mapping vletype_mnemonic : vlewidth <-> string = { - VLE8 <-> "vle8.v", - VLE16 <-> "vle16.v", - VLE32 <-> "vle32.v", - VLE64 <-> "vle64.v" -} - -mapping clause assembly = VLETYPE(vm, rs1, width, vd) - <-> vletype_mnemonic(width) ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) - -/* ******************** Vector Store Unit-Stride Normal (nf=0, mop=0, sumop=0) ******************* */ -union clause ast = VSETYPE : (bits(1), regidx, vlewidth, regidx) - -mapping clause encdec = VSETYPE(vm, rs1, width, vs3) if haveRVV() - <-> 0b000 @ 0b0 @ 0b00 @ vm @ 0b00000 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() - -val process_vse : forall 'b 'n 'p, ('b in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vse (vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) = { - let width_type : word_width = bytes_wordwidth(load_width_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vs3_val : vector('n, dec, bits('b * 8)) = read_vreg(num_elem, load_width_bytes * 8, EMUL_pow, vs3); - let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_pow, vm_val); - - foreach (i from 0 to (num_elem - 1)) { - if mask[i] then { /* active elements */ - vstart = to_bits(16, i); - let elem_offset = i * load_width_bytes; - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width_type) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false); - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - MemValue(_) => { - let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, vs3_val[i], false, false, false); - match (res) { - MemValue(true) => (), - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - } - } - } - } - } - } - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VSETYPE(vm, rs1, width, vs3)) = { - let load_width_bytes = vlewidth_bytesnumber(width); - let EEW = load_width_bytes * 8; - let EEW_pow = vlewidth_pow(width); - let SEW_pow = get_sew_pow(); - let LMUL_pow = get_lmul_pow(); - let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; - let num_elem = get_num_elem(EMUL_pow, EEW); - - if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - - process_vse(vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) -} - -mapping vsetype_mnemonic : vlewidth <-> string = { - VLE8 <-> "vse8.v", - VLE16 <-> "vse16.v", - VLE32 <-> "vse32.v", - VLE64 <-> "vse64.v" -} - -mapping clause assembly = VSETYPE(vm, rs1, width, vs3) - <-> vsetype_mnemonic(width) ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) - -/* ************************** Vector Load Strided Normal (nf=0, mop=10) ************************** */ -union clause ast = VLSETYPE : (bits(1), regidx, regidx, vlewidth, regidx) - -mapping clause encdec = VLSETYPE(vm, rs2, rs1, width, vd) if haveRVV() - <-> 0b000 @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() - -val process_vlse : forall 'b 'n 'p, ('b in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vlse (vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) = { - let width_type : word_width = bytes_wordwidth(load_width_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vd_val : vector('n, dec, bits('b * 8)) = read_vreg(num_elem, load_width_bytes * 8, EMUL_pow, vd); - let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen))); - - let (total, mask) = init_masked_result(num_elem, load_width_bytes * 8, EMUL_pow, vd_val, vm_val); - - foreach (i from 0 to (num_elem - 1)) { - if mask[i] then { /* active elements */ - vstart = to_bits(16, i); - let elem_offset = i * rs2_val; - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width_type) - then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - TR_Address(paddr, _) => { - match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, result), - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - } - } - } - } - } else { /* prestart, masked or tail elements */ - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, total[i]) - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VLSETYPE(vm, rs2, rs1, width, vd)) = { - let load_width_bytes = vlewidth_bytesnumber(width); - let EEW = load_width_bytes * 8; - let EEW_pow = vlewidth_pow(width); - let SEW_pow = get_sew_pow(); - let LMUL_pow = get_lmul_pow(); - let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; - let num_elem = get_num_elem(EMUL_pow, EEW); - - if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - - process_vlse(vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) -} - -mapping vlsetype_mnemonic : vlewidth <-> string = { - VLE8 <-> "vlse8.v", - VLE16 <-> "vlse16.v", - VLE32 <-> "vlse32.v", - VLE64 <-> "vlse64.v" -} - -mapping clause assembly = VLSETYPE(vm, rs2, rs1, width, vd) - <-> vlsetype_mnemonic(width) ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(rs2)^ maybe_vmask(vm) - -/* ************************** Vector Store Strided Normal (nf=0, mop=10) ************************* */ -union clause ast = VSSETYPE : (bits(1), regidx, regidx, vlewidth, regidx) - -mapping clause encdec = VSSETYPE(vm, rs2, rs1, width, vs3) if haveRVV() - <-> 0b000 @ 0b0 @ 0b10 @ vm @ rs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() - -val process_vsse : forall 'b 'n 'p, ('b in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('b), regidx, regidx, int('p), int('n)) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vsse (vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) = { - let width_type : word_width = bytes_wordwidth(load_width_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vs3_val : vector('n, dec, bits('b * 8)) = read_vreg(num_elem, load_width_bytes * 8, EMUL_pow, vs3); - let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen))); - let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_pow, vm_val); - - foreach (i from 0 to (num_elem - 1)) { - if mask[i] then { /* active elements */ - vstart = to_bits(16, i); - let elem_offset = i * rs2_val; - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width_type) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = mem_write_ea(paddr, load_width_bytes, false, false, false); - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - MemValue(_) => { - let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, vs3_val[i], false, false, false); - match (res) { - MemValue(true) => (), - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - } - } - } - } - } - } - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VSSETYPE(vm, rs2, rs1, width, vs3)) = { - let load_width_bytes = vlewidth_bytesnumber(width); - let EEW = load_width_bytes * 8; - let EEW_pow = vlewidth_pow(width); - let SEW_pow = get_sew_pow(); - let LMUL_pow = get_lmul_pow(); - let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; - let num_elem = get_num_elem(EMUL_pow, EEW); - - if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - - process_vsse(vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) -} - -mapping vssetype_mnemonic : vlewidth <-> string = { - VLE8 <-> "vsse8.v", - VLE16 <-> "vsse16.v", - VLE32 <-> "vsse32.v", - VLE64 <-> "vsse64.v" -} - -mapping clause assembly = VSSETYPE(vm, rs2, rs1, width, vs3) - <-> vssetype_mnemonic(width) ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(rs2)^ maybe_vmask(vm) - -/* ************************ Vector Load Indexed Unordered (nf=0, mop=01) ************************* */ -union clause ast = VLUXEITYPE : (bits(1), regidx, regidx, vlewidth, regidx) - -mapping clause encdec = VLUXEITYPE(vm, vs2, rs1, width, vd) if haveRVV() - <-> 0b000 @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() - -val process_vlxei : forall 'ib 'db 'ip 'dp 'n, ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vlxei (vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, mop) = { - let width_type : word_width = bytes_wordwidth(EEW_data_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vd_val : vector('n, dec, bits('db * 8)) = read_vreg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, vd); - let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2); - - let (total, mask) = init_masked_result(num_elem, EEW_data_bytes * 8, EMUL_data_pow, vd_val, vm_val); - - /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */ - foreach (i from 0 to (num_elem - 1)) { - if mask[i] then { /* active elements */ - vstart = to_bits(16, i); - let elem_offset = signed(vs2_val[i]); - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width_type) then - { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } - else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - TR_Address(paddr, _) => { - match mem_read(Read(Data), paddr, EEW_data_bytes, false, false, false) { - MemValue(result) => write_single_element(EEW_data_bytes * 8, i, EMUL_data_pow, vd, result), - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - } - } - } - } - } else { /* prestart, masked or tail elements */ - write_single_element(EEW_data_bytes * 8, i, EMUL_data_pow, vd, total[i]) - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VLUXEITYPE(vm, vs2, rs1, width, vd)) = { - let EEW_index_pow = vlewidth_pow(width); - let EEW_index_bytes = vlewidth_bytesnumber(width); - let EEW_data_pow = get_sew_pow(); - let EEW_data_bytes = get_sew_bytes(); - let EMUL_data_pow = get_lmul_pow(); - let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; - let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); - - if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - - process_vlxei(vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) -} - -mapping clause assembly = VLUXEITYPE(vm, vs2, rs1, width, vd) - <-> "vluxei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) - -/* ************************* Vector Load Indexed Ordered (nf=0, mop=11) ************************** */ -union clause ast = VLOXEITYPE : (bits(1), regidx, regidx, vlewidth, regidx) - -mapping clause encdec = VLOXEITYPE(vm, vs2, rs1, width, vd) if haveRVV() - <-> 0b000 @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() - -function clause execute(VLOXEITYPE(vm, vs2, rs1, width, vd)) = { - let EEW_index_pow = vlewidth_pow(width); - let EEW_index_bytes = vlewidth_bytesnumber(width); - let EEW_data_pow = get_sew_pow(); - let EEW_data_bytes = get_sew_bytes(); - let EMUL_data_pow = get_lmul_pow(); - let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; - let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); - - if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - - process_vlxei(vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) -} - -mapping clause assembly = VLOXEITYPE(vm, vs2, rs1, width, vd) - <-> "vloxei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) - -/* ************************ Vector Store Indexed Unordered (nf=0, mop=01) ************************ */ -union clause ast = VSUXEITYPE : (bits(1), regidx, regidx, vlewidth, regidx) - -mapping clause encdec = VSUXEITYPE(vm, vs2, rs1, width, vs3) if haveRVV() - <-> 0b000 @ 0b0 @ 0b01 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() - -val process_vsxei : forall 'ib 'db 'ip 'dp 'n, ('ib in {1, 2, 4, 8}) & ('db in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('ib), int('db), int('ip), int('dp), regidx, regidx, int('n), int) -> Retired effect {eamem, escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vsxei (vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, mop) = { - let width_type : word_width = bytes_wordwidth(EEW_data_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vs3_val : vector('n, dec, bits('db * 8)) = read_vreg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, vs3); - let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2); - let mask : vector('n, dec, bool) = init_masked_source(num_elem, EMUL_data_pow, vm_val); - - /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */ - foreach (i from 0 to (num_elem - 1)) { - if mask[i] then { /* active elements */ - vstart = to_bits(16, i); - let elem_offset = signed(vs2_val[i]); - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Write(Data), width_type) { - Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => - if check_misaligned(vaddr, width_type) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); return RETIRE_FAIL } - else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - TR_Address(paddr, _) => { - let eares : MemoryOpResult(unit) = mem_write_ea(paddr, EEW_data_bytes, false, false, false); - match (eares) { - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, - MemValue(_) => { - let res : MemoryOpResult(bool) = mem_write_value(paddr, EEW_data_bytes, vs3_val[i], false, false, false); - match (res) { - MemValue(true) => (), - MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), - MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - } - } - } - } - } - } - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VSUXEITYPE(vm, vs2, rs1, width, vs3)) = { - let EEW_index_pow = vlewidth_pow(width); - let EEW_index_bytes = vlewidth_bytesnumber(width); - let EEW_data_pow = get_sew_pow(); - let EEW_data_bytes = get_sew_bytes(); - let EMUL_data_pow = get_lmul_pow(); - let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; - let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ - - if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - - process_vsxei(vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) -} - -mapping clause assembly = VSUXEITYPE(vm, vs2, rs1, width, vs3) - <-> "vsuxei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) - -/* ************************* Vector Store Indexed Ordered (nf=0, mop=11) ************************* */ -union clause ast = VSOXEITYPE : (bits(1), regidx, regidx, vlewidth, regidx) - -mapping clause encdec = VSOXEITYPE(vm, vs2, rs1, width, vs3) if haveRVV() - <-> 0b000 @ 0b0 @ 0b11 @ vm @ vs2 @ rs1 @ encdec_vlewidth(width) @ vs3 @ 0b0100111 if haveRVV() - -function clause execute(VSOXEITYPE(vm, vs2, rs1, width, vs3)) = { - let EEW_index_pow = vlewidth_pow(width); - let EEW_index_bytes = vlewidth_bytesnumber(width); - let EEW_data_pow = get_sew_pow(); - let EEW_data_bytes = get_sew_bytes(); - let EMUL_data_pow = get_lmul_pow(); - let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; - let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ - - if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; - - process_vsxei(vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) -} - -mapping clause assembly = VSOXEITYPE(vm, vs2, rs1, width, vs3) - <-> "vsoxei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) - -/* ************* Vector Load Unit-Stride Fault-Only-First (nf=0, mop=0, lumop=10000) ************* */ -union clause ast = VLEFFTYPE : (bits(1), regidx, vlewidth, regidx) - -mapping clause encdec = VLEFFTYPE(vm, rs1, width, vd) if haveRVV() - <-> 0b000 @ 0b0 @ 0b00 @ vm @ 0b10000 @ rs1 @ encdec_vlewidth(width) @ vd @ 0b0000111 if haveRVV() - -val process_vleff : forall 'b 'n 'p, ('b in {1, 2, 4, 8}) & ('n >= 0). (bits(1), regidx, int('b), regidx, int('p), int('n)) -> Retired effect {escape, rmem, rmemt, rreg, undef, wmv, wmvt, wreg} -function process_vleff (vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = { - let width_type : word_width = bytes_wordwidth(load_width_bytes); - let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); - let vd_val : vector('n, dec, bits('b * 8)) = read_vreg(num_elem, load_width_bytes * 8, EMUL_pow, vd); - let tail_ag : agtype = get_vtype_vta(); - - let (total, mask) = init_masked_result(num_elem, load_width_bytes * 8, EMUL_pow, vd_val, vm_val); - - trimmed : bool = false; - foreach (i from 0 to (num_elem - 1)) { - if not(trimmed) then { - if mask[i] then { /* active elements */ - let elem_offset = i * load_width_bytes; - match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { - Ext_DataAddr_Error(e) => { - if i == 0 then { ext_handle_data_check_error(e); return RETIRE_FAIL } - else { - vl = to_bits(sizeof(xlen), i); - print_reg("CSR vl <- " ^ BitStr(vl)); - trimmed = true - } - }, - Ext_DataAddr_OK(vaddr) => { - if check_misaligned(vaddr, width_type) then { - if i == 0 then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } - else { - vl = to_bits(sizeof(xlen), i); - print_reg("CSR vl <- " ^ BitStr(vl)); - trimmed = true - } - } else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { - if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - else { - vl = to_bits(sizeof(xlen), i); - print_reg("CSR vl <- " ^ BitStr(vl)); - trimmed = true - } - }, - TR_Address(paddr, _) => { - match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, result), - MemException(e) => { - if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL } - else { - vl = to_bits(sizeof(xlen), i); - print_reg("CSR vl <- " ^ BitStr(vl)); - trimmed = true - } - } - } - } - } - } - } - } else { /* prestart, masked or tail elements */ - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, total[i]) - } - } else { - /* if vl is trimmed, elements past the new vl are treated as tail elements */ - if tail_ag == AGNOSTIC then { - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd, vd_val[i]) - /* TODO: configuration support for agnostic behavior */ - } - } - }; - - vstart = EXTZ(0b0); - RETIRE_SUCCESS -} - -function clause execute(VLEFFTYPE(vm, rs1, width, vd)) = { - let load_width_bytes = vlewidth_bytesnumber(width); - let EEW = load_width_bytes * 8; - let EEW_pow = vlewidth_pow(width); - let SEW_pow = get_sew_pow(); - let LMUL_pow = get_lmul_pow(); - let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; - let num_elem = get_num_elem(EMUL_pow, EEW); - - if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; - - process_vleff(vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) -} - -mapping vlefftype_mnemonic : vlewidth <-> string = { - VLE8 <-> "vle8ff.v", - VLE16 <-> "vle16ff.v", - VLE32 <-> "vle32ff.v", - VLE64 <-> "vle64ff.v" -} - -mapping clause assembly = VLEFFTYPE(vm, rs1, width, vd) - <-> vlefftype_mnemonic(width) ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) - -/* ******************** Vector Load Unit-Stride Segment (mop=0, lumop=00000) ********************* */ +/* ******************** Vector Load Unit-Stride Normal & Segment (mop=0b00, lumop=0b00000) ********************* */ union clause ast = VLSEGTYPE : (bits(3), bits(1), regidx, vlewidth, regidx) mapping clause encdec = VLSEGTYPE(nf, vm, rs1, width, vd) if haveRVV() @@ -662,7 +111,7 @@ function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd); - let (total, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val); + let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { /* active segments */ @@ -671,14 +120,14 @@ function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = let elem_offset = (i * nf + j) * load_width_bytes; match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => + Ext_DataAddr_OK(vaddr) => if check_misaligned(vaddr, width_type) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), result), + MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem), MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } } } @@ -687,13 +136,13 @@ function process_vlseg (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) = } } else { /* prestart, masked or tail segments */ foreach (j from 0 to (nf - 1)) { - let elem_val = (total[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), elem_val) + let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; + write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem) } } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -707,15 +156,15 @@ function clause execute(VLSEGTYPE(nf, vm, rs1, width, vd)) = { let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ let nf_int = nfields_int(nf); - if illegal_segment_load(vd, vm, nf_int, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } mapping clause assembly = VLSEGTYPE(nf, vm, rs1, width, vd) - <-> "vlseg" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) + <-> "vl" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) -/* ************ Vector Load Unit-Stride Segment Fault-Only-First (mop=0, lumop=10000) ************ */ +/* ************ Vector Load Unit-Stride Normal & Segment Fault-Only-First (mop=0b00, lumop=0b10000) ************ */ union clause ast = VLSEGFFTYPE : (bits(3), bits(1), regidx, vlewidth, regidx) mapping clause encdec = VLSEGFFTYPE(nf, vm, rs1, width, vd) if haveRVV() @@ -729,7 +178,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd); let tail_ag : agtype = get_vtype_vta(); - let (total, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val); + let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val); trimmed : bool = false; foreach (i from 0 to (num_elem - 1)) { @@ -738,7 +187,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) foreach (j from 0 to (nf - 1)) { let elem_offset = (i * nf + j) * load_width_bytes; match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { - Ext_DataAddr_Error(e) => { + Ext_DataAddr_Error(e) => { if i == 0 then { ext_handle_data_check_error(e); return RETIRE_FAIL } else { vl = to_bits(sizeof(xlen), i); @@ -755,7 +204,7 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) trimmed = true } } else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e, _) => { + TR_Failure(e, _) => { if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL } else { vl = to_bits(sizeof(xlen), i); @@ -765,8 +214,8 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), result), - MemException(e) => { + MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem), + MemException(e) => { if i == 0 then { handle_mem_exception(vaddr, e); return RETIRE_FAIL } else { vl = to_bits(sizeof(xlen), i); @@ -782,23 +231,23 @@ function process_vlsegff (nf, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } } else { /* prestart, masked or tail segments */ foreach (j from 0 to (nf - 1)) { - let elem_val = (total[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), elem_val) + let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; + write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem) } } } else { /* if vl is trimmed, elements past the new vl are treated as tail elements */ if tail_ag == AGNOSTIC then { foreach (j from 0 to (nf - 1)) { - let elem_val = (vd_seg[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), elem_val) + let skipped_elem = (vd_seg[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; + write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem) } /* TODO: configuration support for agnostic behavior */ } } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -812,15 +261,15 @@ function clause execute(VLSEGFFTYPE(nf, vm, rs1, width, vd)) = { let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - if illegal_segment_load(vd, vm, nf_int, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) } -mapping clause assembly = VLSEGTYPE(nf, vm, rs1, width, vd) - <-> "vlseg" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ "ff.v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) +mapping clause assembly = VLSEGFFTYPE(nf, vm, rs1, width, vd) + <-> "vl" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ "ff.v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) -/* ******************** Vector Store Unit-Stride Segment (mop=0, sumop=00000) ******************** */ +/* ******************** Vector Store Unit-Stride Normal & Segment (mop=0b00, sumop=0b00000) ******************** */ union clause ast = VSSEGTYPE : (bits(3), bits(1), regidx, vlewidth, regidx) mapping clause encdec = VSSEGTYPE(nf, vm, rs1, width, vs3) if haveRVV() @@ -851,7 +300,7 @@ function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) match (eares) { MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, MemValue(_) => { - let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, EMUL_pow, vs3 + to_bits(5, j * EMUL_reg)); + let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, j * EMUL_reg)); let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false); match (res) { MemValue(true) => (), @@ -867,7 +316,7 @@ function process_vsseg (nf, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -881,15 +330,15 @@ function clause execute(VSSEGTYPE(nf, vm, rs1, width, vs3)) = { let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - if illegal_segment_store(nf_int, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) } mapping clause assembly = VSSEGTYPE(nf, vm, rs1, width, vs3) - <-> "vsseg" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) + <-> "vs" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ maybe_vmask(vm) -/* **************************** Vector Load Strided Segment (mop=10) ***************************** */ +/* ****************************** Vector Load Strided Normal & Segment (mop=0b10) ****************************** */ union clause ast = VLSSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) mapping clause encdec = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd) if haveRVV() @@ -903,7 +352,7 @@ function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_e let vd_seg : vector('n, dec, bits('f * 'b * 8)) = read_vreg_seg(num_elem, load_width_bytes * 8, EMUL_pow, nf, vd); let rs2_val : int = signed(get_scalar(rs2, sizeof(xlen))); - let (total, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val); + let (result, mask) = init_masked_result(num_elem, nf * load_width_bytes * 8, EMUL_pow, vd_seg, vm_val); foreach (i from 0 to (num_elem - 1)) { if mask[i] then { /* active segments */ @@ -912,14 +361,14 @@ function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_e let elem_offset = i * rs2_val + j * load_width_bytes; match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => + Ext_DataAddr_OK(vaddr) => if check_misaligned(vaddr, width_type) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), result), + MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), elem), MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } } } @@ -928,13 +377,13 @@ function process_vlsseg (nf, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_e } } else { /* prestart, masked or tail segments */ foreach (j from 0 to (nf - 1)) { - let elem_val = (total[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; - write_single_element(load_width_bytes * 8, i, EMUL_pow, vd + to_bits(5, j * EMUL_reg), elem_val) + let skipped_elem = (result[i] >> (j * load_width_bytes * 8))[(load_width_bytes * 8 - 1) .. 0]; + write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j * EMUL_reg), skipped_elem) } } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -948,15 +397,15 @@ function clause execute(VLSSEGTYPE(nf, vm, rs2, rs1, width, vd)) = { let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - if illegal_segment_load(vd, vm, nf_int, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } mapping clause assembly = VLSSEGTYPE(nf, vm, rs2, rs1, width, vd) - <-> "vlsseg" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(rs2) ^ maybe_vmask(vm) + <-> "vls" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(rs2) ^ maybe_vmask(vm) -/* **************************** Vector Store Strided Segment (mop=10) **************************** */ +/* ***************************** Vector Store Strided Normal & Segment (mop=0b10) ****************************** */ union clause ast = VSSSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) mapping clause encdec = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3) if haveRVV() @@ -988,7 +437,7 @@ function process_vssseg (nf, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_ match (eares) { MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, MemValue(_) => { - let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, EMUL_pow, vs3 + to_bits(5, j * EMUL_reg)); + let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, j * EMUL_reg)); let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false); match (res) { MemValue(true) => (), @@ -1004,7 +453,7 @@ function process_vssseg (nf, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_ } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1018,15 +467,15 @@ function clause execute(VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3)) = { let num_elem = get_num_elem(EMUL_pow, EEW); let nf_int = nfields_int(nf); - if illegal_segment_store(nf_int, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) } mapping clause assembly = VSSSEGTYPE(nf, vm, rs2, rs1, width, vs3) - <-> "vssseg" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(rs2) ^ maybe_vmask(vm) + <-> "vss" ^ nfields_string(nf) ^ "e" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(rs2) ^ maybe_vmask(vm) -/* *********************** Vector Load Indexed Unordered Segment (mop=01) ************************ */ +/* ************************* Vector Load Indexed Unordered Normal & Segment (mop=0b01) ************************* */ union clause ast = VLUXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) mapping clause encdec = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveRVV() @@ -1040,7 +489,7 @@ function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index let vd_seg : vector('n, dec, bits('f * 'db * 8)) = read_vreg_seg(num_elem, EEW_data_bytes * 8, EMUL_data_pow, nf, vd); let vs2_val : vector('n, dec, bits('ib * 8)) = read_vreg(num_elem, EEW_index_bytes * 8, EMUL_index_pow, vs2); - let (total, mask) = init_masked_result(num_elem, nf * EEW_data_bytes * 8, EMUL_data_pow, vd_seg, vm_val); + let (result, mask) = init_masked_result(num_elem, nf * EEW_data_bytes * 8, EMUL_data_pow, vd_seg, vm_val); /* currently mop = 1 (unordered) or 3 (ordered) do the same operations */ foreach (i from 0 to (num_elem - 1)) { @@ -1050,14 +499,14 @@ function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index let elem_offset : int = signed(vs2_val[i]) + j * EEW_data_bytes; match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => + Ext_DataAddr_OK(vaddr) => if check_misaligned(vaddr, width_type) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, EEW_data_bytes, false, false, false) { - MemValue(result) => write_single_element(EEW_data_bytes * 8, i, EMUL_data_pow, vd + to_bits(5, j * EMUL_data_reg), result), + MemValue(elem) => write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), elem), MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } } } @@ -1066,13 +515,13 @@ function process_vlxseg (nf, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index } } else { /* prestart, masked or tail segments */ foreach (j from 0 to (nf - 1)) { - let elem_val = (total[i] >> (j * EEW_data_bytes * 8))[(EEW_data_bytes * 8 - 1) .. 0]; - write_single_element(EEW_data_bytes * 8, i, EMUL_data_pow, vd + to_bits(5, j * EMUL_data_reg), elem_val) + let skipped_elem = (result[i] >> (j * EEW_data_bytes * 8))[(EEW_data_bytes * 8 - 1) .. 0]; + write_single_element(EEW_data_bytes * 8, i, vd + to_bits(5, j * EMUL_data_reg), skipped_elem) } } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1086,15 +535,15 @@ function clause execute(VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd)) = { let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - if illegal_segment_load(vd, vm, nf_int, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } mapping clause assembly = VLUXSEGTYPE(nf, vm, vs2, rs1, width, vd) - <-> "vluxseg" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) + <-> "vlux" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) -/* ************************ Vector Load Indexed Ordered Segment (mop=11) ************************* */ +/* ************************** Vector Load Indexed Ordered Normal & Segment (mop=0b11) ************************** */ union clause ast = VLOXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) mapping clause encdec = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd) if haveRVV() @@ -1110,15 +559,15 @@ function clause execute(VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd)) = { let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); let nf_int = nfields_int(nf); - if illegal_segment_load(vd, vm, nf_int, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } mapping clause assembly = VLOXSEGTYPE(nf, vm, vs2, rs1, width, vd) - <-> "vloxseg" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) + <-> "vlox" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) -/* *********************** Vector Store Indexed Unordered Segment (mop=01) *********************** */ +/* ************************ Vector Store Indexed Unordered Normal & Segment (mop=0b01) ************************* */ union clause ast = VSUXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) mapping clause encdec = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveRVV() @@ -1151,7 +600,7 @@ function process_vsxseg (nf, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_inde match (eares) { MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, MemValue(_) => { - let elem_val : bits('db * 8) = read_single_element(EEW_data_bytes * 8, i, EMUL_data_pow, vs3 + to_bits(5, j * EMUL_data_reg)); + let elem_val : bits('db * 8) = read_single_element(EEW_data_bytes * 8, i, vs3 + to_bits(5, j * EMUL_data_reg)); let res : MemoryOpResult(bool) = mem_write_value(paddr, EEW_data_bytes, elem_val, false, false, false); match (res) { MemValue(true) => (), @@ -1167,7 +616,7 @@ function process_vsxseg (nf, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_inde } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1181,15 +630,15 @@ function clause execute(VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = { let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - if illegal_segment_store(nf_int, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) } mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) - <-> "vsuxseg" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) + <-> "vsux" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) -/* ************************ Vector Store Indexed Ordered Segment (mop=11) ************************ */ +/* ************************* Vector Store Indexed Ordered Normal & Segment (mop=0b11) ************************** */ union clause ast = VSOXSEGTYPE : (bits(3), bits(1), regidx, regidx, vlewidth, regidx) mapping clause encdec = VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3) if haveRVV() @@ -1205,15 +654,15 @@ function clause execute(VSOXSEGTYPE(nf, vm, vs2, rs1, width, vs3)) = { let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ let nf_int = nfields_int(nf); - if illegal_segment_store(nf_int, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) } mapping clause assembly = VSUXSEGTYPE(nf, vm, vs2, rs1, width, vs3) - <-> "vsoxseg" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) + <-> "vsox" ^ nfields_string(nf) ^ "ei" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" ^ sep() ^ reg_name(vs2) ^ maybe_vmask(vm) -/* ************** Vector Load Unit-Stride Whole Register (vm=1, mop=0, lumop=01000) ************** */ +/* ***************** Vector Load Unit-Stride Whole Register (vm=0b1, mop=0b00, lumop=0b01000) ****************** */ union clause ast = VLRETYPE : (bits(3), regidx, vlewidth, regidx) mapping clause encdec = VLRETYPE(nf, rs1, width, vd) if haveRVV() @@ -1234,14 +683,14 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = { let elem_offset = cur_elem * load_width_bytes; match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => + Ext_DataAddr_OK(vaddr) => if check_misaligned(vaddr, width_type) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, 0, vd + to_bits(5, cur_field), result), + MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, cur_field), elem), MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } } } @@ -1258,14 +707,14 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = { let elem_offset = cur_elem * load_width_bytes; match ext_data_get_addr(rs1, to_bits(sizeof(xlen), elem_offset), Read(Data), width_type) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => + Ext_DataAddr_OK(vaddr) => if check_misaligned(vaddr, width_type) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, load_width_bytes, false, false, false) { - MemValue(result) => write_single_element(load_width_bytes * 8, i, 0, vd + to_bits(5, j) , result), + MemValue(elem) => write_single_element(load_width_bytes * 8, i, vd + to_bits(5, j), elem), MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } } } @@ -1275,7 +724,7 @@ function process_vlre (nf, vd, load_width_bytes, rs1, elem_per_reg) = { } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1295,7 +744,7 @@ function clause execute(VLRETYPE(nf, rs1, width, vd)) = { mapping clause assembly = VLRETYPE(nf, rs1, width, vd) <-> "vl" ^ nfields_string(nf) ^ "re" ^ vlewidth_bitsnumberstr(width) ^ ".v" ^ spc() ^ vreg_name(vd) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" -/* ************* Vector Store Unit-Stride Whole Register (vm=1, mop=0, lumop=01000) ************** */ +/* ***************** Vector Store Unit-Stride Whole Register (vm=0b1, mop=0b00, lumop=0b01000) ***************** */ union clause ast = VSRETYPE : (bits(3), regidx, regidx) mapping clause encdec = VSRETYPE(nf, rs1, vs3) if haveRVV() @@ -1326,8 +775,8 @@ function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = { match (eares) { MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, MemValue(_) => { - let elem_val : bits('b * 8) = read_single_element(load_width_bytes * 8, i, 0, vs3 + to_bits(5, cur_field)); - let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem_val, false, false, false); + let elem : bits('b * 8) = read_single_element(load_width_bytes * 8, i, vs3 + to_bits(5, cur_field)); + let res : MemoryOpResult(bool) = mem_write_value(paddr, load_width_bytes, elem, false, false, false); match (res) { MemValue(true) => (), MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), @@ -1375,7 +824,7 @@ function process_vsre (nf, load_width_bytes, rs1, vs3, elem_per_reg) = { } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -1395,7 +844,7 @@ function clause execute(VSRETYPE(nf, rs1, vs3)) = { mapping clause assembly = VSRETYPE(nf, rs1, vs3) <-> "vs" ^ nfields_string(nf) ^ "r.v" ^ spc() ^ vreg_name(vs3) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" -/* *********** Vector Mask Load/Store Unit-Stride (nf=0, mop=0, lumop or sumop=01011) ************ */ +/* ************** Vector Mask Load/Store Unit-Stride (nf=0b000, mop=0b00, lumop or sumop=0b01011) ************** */ union clause ast = VMTYPE : (regidx, regidx, vmlsop) mapping encdec_lsop : vmlsop <-> bits(7) = { @@ -1418,14 +867,14 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = { if op == VLM then { /* load */ match ext_data_get_addr(rs1, to_bits(sizeof(xlen), i), Read(Data), width_type) { Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); return RETIRE_FAIL }, - Ext_DataAddr_OK(vaddr) => + Ext_DataAddr_OK(vaddr) => if check_misaligned(vaddr, width_type) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); return RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { TR_Failure(e, _) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL }, TR_Address(paddr, _) => { match mem_read(Read(Data), paddr, 1, false, false, false) { - MemValue(result) => write_single_element(8, i, 0, vd_or_vs3, result), + MemValue(elem) => write_single_element(8, i, vd_or_vs3, elem), MemException(e) => { handle_mem_exception(vaddr, e); return RETIRE_FAIL } } } @@ -1458,13 +907,13 @@ function process_vm(vd_or_vs3, rs1, num_elem, evl, op) = { } } else { /* tail elements for mask load, always with agnostic policy */ if op == VLM then { - write_single_element(8, i, 0, vd_or_vs3, vd_or_vs3_val[i]) + write_single_element(8, i, vd_or_vs3, vd_or_vs3_val[i]) /* TODO: configuration support for agnostic behavior */ } } }; - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } diff --git a/model/riscv_insts_vext_red.sail b/model/riscv_insts_vext_red.sail index 6118c7dbd..9a1b26752 100755 --- a/model/riscv_insts_vext_red.sail +++ b/model/riscv_insts_vext_red.sail @@ -74,25 +74,21 @@ function clause execute(RIVVTYPE(funct6, vm, vs2, vs1, vd)) = { let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - let scalar : bits('o) = read_single_element(SEW_widen, 0, 0, vs1); /* vs1 regardless of LMUL setting */ - sum : bits('o) = match funct6 { - IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(scalar)), - IVV_VWREDSUM => to_bits(SEW_widen, signed(scalar)) - }; - + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { - sum = match funct6 { - IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(sum)), - IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i]) + signed(sum)) - } + let elem : bits('o) = match funct6 { + IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i])), + IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i])) + }; + sum = sum + elem } }; - write_single_element(SEW_widen, 0, 0, vd, sum); + write_single_element(SEW_widen, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -135,12 +131,12 @@ function clause execute(RMVVTYPE(funct6, vm, vs2, vs1, vd)) = { let 'd = num_elem_vd; let 'm = SEW; - let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); - let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); - let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); - let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - sum : bits('m) = read_single_element(SEW, 0, 0, vs1); /* vs1 regardless of LMUL setting */ + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { sum = match funct6 { @@ -156,10 +152,10 @@ function clause execute(RMVVTYPE(funct6, vm, vs2, vs1, vd)) = { } }; - write_single_element(SEW, 0, 0, vd, sum); + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -175,7 +171,7 @@ mapping rmvvtype_mnemonic : rmvvfunct6 <-> string = { } mapping clause assembly = RMVVTYPE(funct6, vm, vs2, vs1, vd) - <-> rmvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm) + <-> rmvvtype_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2) ^ sep() ^ vreg_name(vs1) ^ maybe_vmask(vm) /* ********************** OPFVV (Floating-Point Reduction) *********************** */ union clause ast = RFVVTYPE : (rfvvfunct6, bits(1), regidx, regidx, regidx) @@ -211,7 +207,7 @@ function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_po let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - sum : bits('m) = read_single_element(SEW, 0, 0, vs1); /* vs1 regardless of LMUL setting */ + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { sum = match funct6 { @@ -224,10 +220,10 @@ function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_po } }; - write_single_element(SEW, 0, 0, vd, sum); + write_single_element(SEW, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -248,12 +244,12 @@ function process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow let 'm = SEW; let 'o = SEW_widen; - let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); - let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); - let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); - let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); - sum : bits('o) = read_single_element(SEW_widen, 0, 0, vs1); /* vs1 regardless of LMUL setting */ + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ foreach (i from 0 to (num_elem_vs - 1)) { if mask[i] then { /* currently ordered/unordered sum reductions do the same operations */ @@ -261,10 +257,10 @@ function process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow } }; - write_single_element(SEW_widen, 0, 0, vd, sum); + write_single_element(SEW_widen, 0, vd, sum); /* other elements in vd are treated as tail elements, currently remain unchanged */ /* TODO: configuration support for agnostic behavior */ - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -273,7 +269,7 @@ function clause execute(RFVVTYPE(funct6, vm, vs2, vs1, vd)) = { let LMUL_pow = get_lmul_pow(); let num_elem_vs = get_num_elem(LMUL_pow, SEW); - if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) else process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) diff --git a/model/riscv_insts_vext_utils.sail b/model/riscv_insts_vext_utils.sail index ef0d5b1e2..cb3e272e1 100755 --- a/model/riscv_insts_vext_utils.sail +++ b/model/riscv_insts_vext_utils.sail @@ -6,6 +6,7 @@ /* Yifei Zhu */ /* Shenwei Hu */ /* Kalvin Vu */ +/* Lei Chen */ /* Other contributors: */ /* Jessica Clarke */ /* Victor Moya */ @@ -46,7 +47,10 @@ mapping maybe_vmask : string <-> bits(1) = { sep() ^ "v0.t" <-> 0b0 } -/* Check for valid EEW and EMUL values in vector widening/narrowing instructions */ +/* Check for valid EEW and EMUL values in: + * 1. vector widening/narrowing instructions + * 2. vector load/store instructions + */ val valid_eew_emul : (int, int) -> bool effect {rreg} function valid_eew_emul(EEW, EMUL_pow) = { let ELEN = int_power(2, get_elen_pow()); @@ -75,14 +79,14 @@ function assert_vstart(i) = { val valid_fp_op : ({|8, 16, 32, 64|}, bits(3)) -> bool function valid_fp_op(SEW, rm_3b) = { /* 128-bit floating-point values will be supported in future extensions */ - let valid_sew = (SEW >= 16 & SEW <= 128); + let valid_sew = (SEW >= 16 & SEW <= 128); let valid_rm = not(rm_3b == 0b101 | rm_3b == 0b110 | rm_3b == 0b111); valid_sew & valid_rm } -/* Check for valid destination register when vector masking is enabled: - * The destination vector register group for a masked vector instruction - * cannot overlap the source mask register (v0), +/* Check for valid destination register when vector masking is enabled: + * The destination vector register group for a masked vector instruction + * cannot overlap the source mask register (v0), * unless the destination vector register is being written with a mask value (e.g., compares) * or the scalar result of a reduction. */ @@ -103,13 +107,12 @@ function valid_reg_overlap(rs, rd, EMUL_pow_rs, EMUL_pow_rd) = { let rd_group = if EMUL_pow_rd > 0 then int_power(2, EMUL_pow_rd) else 1; let rs_int = unsigned(rs); let rd_int = unsigned(rd); - let is_valid = if EMUL_pow_rs < EMUL_pow_rd then { - (rs_int + rs_group <= rd_int) | (rs_int >= rd_int + rd_group) | - ((rs_int + rs_group == rd_int + rd_group) & (EMUL_pow_rs >= 0)) - } else if EMUL_pow_rs > EMUL_pow_rd then { - (rd_int <= rs_int) | (rd_int >= rs_int + rs_group) - } else true; - is_valid + if EMUL_pow_rs < EMUL_pow_rd then { + (rs_int + rs_group <= rd_int) | (rs_int >= rd_int + rd_group) | + ((rs_int + rs_group == rd_int + rd_group) & (EMUL_pow_rs >= 0)) + } else if EMUL_pow_rs > EMUL_pow_rd then { + (rd_int <= rs_int) | (rd_int >= rs_int + rs_group) + } else true; } /* Check for valid register grouping in vector segment load/store instructions: @@ -141,8 +144,7 @@ function illegal_vd_masked(vd) = { /* c. Unmasked check for: * 1. instructions encoded with vm = 1 * 2. instructions with scalar rd: vcpop.m, vfirst.m - * 3. instructions with vs3 rather than vd: vector stores - * 4. vd as mask register (eew = 1): + * 3. vd as mask register (eew = 1): * vmadc.vvm/vxm/vim, vmsbc.vvm/vxm, mask logical, integer compare, vlm.v, vsm.v */ val illegal_vd_unmasked : unit -> bool @@ -168,7 +170,7 @@ function illegal_reduction() = { not(valid_vtype()) | not(assert_vstart(0)) } -/* f. Variable width check for widening reduction instructions */ +/* f. Variable width check for widening reduction instructions */ val illegal_reduction_widen : (int, int) -> bool function illegal_reduction_widen(SEW_widen, LMUL_pow_widen) = { not(valid_vtype()) | not(assert_vstart(0)) | not(valid_eew_emul(SEW_widen, LMUL_pow_widen)) @@ -195,7 +197,7 @@ function illegal_fp_vd_unmasked(SEW, rm_3b) = { /* j. Variable width check for floating-point widening/narrowing instructions */ val illegal_fp_variable_width : (regidx, bits(1), {|8, 16, 32, 64|}, bits(3), int, int) -> bool function illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_new, LMUL_pow_new) = { - not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_fp_op(SEW, rm_3b)) | + not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_fp_op(SEW, rm_3b)) | not(valid_eew_emul(SEW_new, LMUL_pow_new)) } @@ -212,29 +214,42 @@ function illegal_fp_reduction_widen(SEW, rm_3b, SEW_widen, LMUL_pow_widen) = { not(valid_eew_emul(SEW_widen, LMUL_pow_widen)) } -/* m. Normal check for segment load instructions */ -val illegal_segment_load : (regidx, bits(1), int, int) -> bool -function illegal_segment_load(vd, vm, nf, EMUL_pow) = { - not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | not(valid_segment(nf, EMUL_pow)) +/* m. Non-indexed load instruction check */ +val illegal_load : (regidx, bits(1), int, int, int) -> bool +function illegal_load(vd, vm, nf, EEW, EMUL_pow) = { + not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | + not(valid_eew_emul(EEW, EMUL_pow)) | not(valid_segment(nf, EMUL_pow)) +} + +/* n. Non-indexed store instruction check (with vs3 rather than vd) */ +val illegal_store : (int, int, int) -> bool +function illegal_store(nf, EEW, EMUL_pow) = { + not(valid_vtype()) | not(valid_eew_emul(EEW, EMUL_pow)) | not(valid_segment(nf, EMUL_pow)) } -/* m. Normal check for segment store instructions (no vd) */ -val illegal_segment_store : (int, int) -> bool -function illegal_segment_store(nf, EMUL_pow) = { - not(valid_vtype()) | not(valid_segment(nf, EMUL_pow)) +/* o. Indexed load instruction check */ +val illegal_indexed_load : (regidx, bits(1), int, int, int, int) -> bool +function illegal_indexed_load(vd, vm, nf, EEW_index, EMUL_pow_index, EMUL_pow_data) = { + not(valid_vtype()) | not(valid_rd_mask(vd, vm)) | + not(valid_eew_emul(EEW_index, EMUL_pow_index)) | not(valid_segment(nf, EMUL_pow_data)) +} + +/* p. Indexed store instruction check (with vs3 rather than vd) */ +val illegal_indexed_store : (int, int, int, int) -> bool +function illegal_indexed_store(nf, EEW_index, EMUL_pow_index, EMUL_pow_data) = { + not(valid_vtype()) | not(valid_eew_emul(EEW_index, EMUL_pow_index)) | + not(valid_segment(nf, EMUL_pow_data)) } /* Scalar register shaping */ -val get_scalar : forall 'n, 'n >= 8. (regidx, int('n)) -> bits('n) effect {escape, rreg} +val get_scalar : forall 'm, 'm >= 8. (regidx, int('m)) -> bits('m) effect {escape, rreg} function get_scalar(rs1, SEW) = { - if sizeof(xlen) > SEW then { + if SEW <= sizeof(xlen) then { /* Least significant SEW bits */ X(rs1)[SEW - 1 .. 0] - } else if sizeof(xlen) < SEW then { + } else { /* Sign extend to SEW */ EXTS(SEW, X(rs1)) - } else { - X(rs1) } } @@ -255,10 +270,7 @@ function get_start_element() = { /* Get the ending element index from csr vl */ val get_end_element : unit -> int effect {escape, rreg, wreg} -function get_end_element() = { - let end_element = unsigned(vl) - 1; - end_element -} +function get_end_element() = unsigned(vl) - 1 /* Mask handling; creates a pre-masked result vector for vstart, vl, vta/vma, and vm */ /* vm should be baked into vm_val from doing read_vmask */ @@ -288,26 +300,23 @@ function init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val) = { mask[i] = false } else if i > end_element then { /* Tail elements defined by vl */ - if tail_ag == UNDISTURBED then { - result[i] = vd_val[i]; - } else if tail_ag == AGNOSTIC then { - result[i] = vd_val[i]; /* TODO: configuration support */ + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ }; mask[i] = false } else if i >= real_num_elem then { /* Tail elements defined by lmul < 1 */ - if tail_ag == UNDISTURBED then { - result[i] = vd_val[i]; - } else if tail_ag == AGNOSTIC then { - result[i] = vd_val[i]; /* TODO: configuration support */ + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ }; mask[i] = false } else if not(vm_val[i]) then { /* Inactive body elements defined by vm */ - if mask_ag == UNDISTURBED then { - result[i] = vd_val[i] - } else if mask_ag == AGNOSTIC then { - result[i] = vd_val[i] /* TODO: configuration support */ + result[i] = match mask_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ }; mask[i] = false } else { @@ -319,7 +328,7 @@ function init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val) = { (result, mask) } -/* For instructions like vector reduction and vector store, +/* For instructions like vector reduction and vector store, * masks on prestart, inactive and tail elements only affect the validation of source register elements * (vs3 for store and vs2 for reduction). There's no destination register to be masked. * In these cases, this function can be called to simply get the mask vector for vs (without the prepared vd result vector). @@ -423,10 +432,9 @@ function init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val) = { mask[i] = false } else if not(vm_val[i]) then { /* Inactive body elements defined by vm */ - if mask_ag == UNDISTURBED then { - result[i] = vd_val[i] - } else if mask_ag == AGNOSTIC then { - result[i] = vd_val[i] /* TODO: configuration support */ + result[i] = match mask_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ }; mask[i] = false } else { @@ -440,7 +448,7 @@ function init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val) = { /* For vector load/store segment instructions: * Read multiple register groups and concatenate them in parallel - * The whole segments with the same element index are combined together + * The whole segments with the same element index are combined together */ val read_vreg_seg : forall 'n 'm 'p 'q. (int('n), int('m), int('p), int('q), regidx) -> vector('n, dec, bits('q * 'm)) effect {escape, rreg, undef} function read_vreg_seg(num_elem, SEW, LMUL_pow, nf, vrid) = { @@ -454,85 +462,147 @@ function read_vreg_seg(num_elem, SEW, LMUL_pow, nf, vrid) = { foreach (i from 0 to (num_elem - 1)) { result[i] = zeros('q * 'm); foreach (j from 0 to (nf - 1)) { - result[i] = result[i] | EXTZ(vreg_list[j][i] << (j * 'm)) + result[i] = result[i] | (EXTZ(vreg_list[j][i]) << (j * 'm)) } }; result } -/* Floating point canonical NaN for 16-bit, 32-bit, 64-bit and 128-bit types */ -val canonical_NaN : forall 'm, 'm in {16, 32, 64, 128}. int('m) -> bits('m) +/* Floating point canonical NaN for 16-bit, 32-bit and 64-bit types */ +val canonical_NaN : forall 'm, 'm in {16, 32, 64}. int('m) -> bits('m) function canonical_NaN('m) = { match 'm { - 16 => 0x_7e00, - 32 => 0x_7fc0_0000, - 64 => 0x_7ff8_0000_0000_0000, - 128 => 0x_7fff_8000_0000_0000_0000_0000_0000_0000 + 16 => canonical_NaN_H(), + 32 => canonical_NaN_S(), + 64 => canonical_NaN_D() + } +} + +/* Floating point NaN boxing / unboxing that support 16-bit to 64-bit types */ +val nan_box_vector : forall 'm, ('m in {16, 32, 64} & 'm <= flen). bits('m) -> flenbits +function nan_box_vector(unboxed) = { + match 'm { + 16 => nan_box(unboxed), + 32 => nan_box(unboxed), + 64 => unboxed } } -/* Floating point NaN boxing / unboxing that support 16-bit to 128-bit types */ -val NaN_box : forall 'm, ('m in {16, 32, 64, 128} & 'm <= flen). bits('m) -> flenbits -function NaN_box unboxed = { - if sizeof(flen) == 'm then unboxed - else ones(sizeof(flen) - 'm) @ unboxed +val nan_unbox_vector : forall 'm, ('m in {16, 32, 64} & 'm <= flen). (flenbits, int('m)) -> bits('m) +function nan_unbox_vector(regval, 'm) = { + match 'm { + 16 => nan_unbox(regval), + 32 => nan_unbox(regval), + 64 => regval + } +} + +/* Floating point classification functions */ +val f_is_neg_inf : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_neg_inf(xf) = { + match 'm { + 16 => f_is_neg_inf_H(xf), + 32 => f_is_neg_inf_S(xf), + 64 => f_is_neg_inf_D(xf) + } } -val NaN_unbox : forall 'm, ('m in {16, 32, 64, 128} & 'm <= flen). (flenbits, int('m)) -> bits('m) -function NaN_unbox(regval, 'm) = { - if sizeof(flen) == 'm then regval - else if regval[sizeof(flen) - 1 .. 'm] == ones() then regval['m - 1 .. 0] - else canonical_NaN('m) +val f_is_neg_norm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_neg_norm(xf) = { + match 'm { + 16 => f_is_neg_norm_H(xf), + 32 => f_is_neg_norm_S(xf), + 64 => f_is_neg_norm_D(xf) + } +} + +val f_is_neg_subnorm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_neg_subnorm(xf) = { + match 'm { + 16 => f_is_neg_subnorm_H(xf), + 32 => f_is_neg_subnorm_S(xf), + 64 => f_is_neg_subnorm_D(xf) + } } -/* Check if the floating point number is a signaling NaN */ -val f_is_SNaN : forall 'm, 'm in {16, 32, 64, 128}. bits('m) -> bool -function f_is_SNaN xf = { +val f_is_neg_zero : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_neg_zero(xf) = { match 'm { - 16 => (xf[14..10] == ones()) & (xf[9..9] == zeros()) & (xf[8..0] != zeros()), - 32 => (xf[30..23] == ones()) & (xf[22..22] == zeros()) & (xf[21..0] != zeros()), - 64 => (xf[62..52] == ones()) & (xf[51..51] == zeros()) & (xf[50..0] != zeros()), - 128 => (xf[126..112] == ones()) & (xf[111..111] == zeros()) & (xf[110..0] != zeros()) + 16 => f_is_neg_zero_H(xf), + 32 => f_is_neg_zero_S(xf), + 64 => f_is_neg_zero_D(xf) } } -/* Either QNaN or SNan */ -val f_is_NaN : forall 'm, 'm in {16, 32, 64, 128}. bits('m) -> bool -function f_is_NaN xf = { +val f_is_pos_zero : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_pos_zero(xf) = { match 'm { - 16 => (xf[14..10] == ones()) & (xf[9..0] != zeros()), - 32 => (xf[30..23] == ones()) & (xf[22..0] != zeros()), - 64 => (xf[62..52] == ones()) & (xf[51..0] != zeros()), - 128 => (xf[126..112] == ones()) & (xf[111..0] != zeros()) + 16 => f_is_pos_zero_H(xf), + 32 => f_is_pos_zero_S(xf), + 64 => f_is_pos_zero_D(xf) } } -val f_is_neg_zero : forall 'm, 'm in {16, 32, 64, 128}. bits('m) -> bool -function f_is_neg_zero xf = { +val f_is_pos_subnorm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_pos_subnorm(xf) = { match 'm { - 16 => (xf[15..15] == ones()) & (xf[14..0] == zeros()), - 32 => (xf[31..31] == ones()) & (xf[30..0] == zeros()), - 64 => (xf[63..63] == ones()) & (xf[62..0] == zeros()), - 128 => (xf[127..127] == ones()) & (xf[126..0] == zeros()) + 16 => f_is_pos_subnorm_H(xf), + 32 => f_is_pos_subnorm_S(xf), + 64 => f_is_pos_subnorm_D(xf) } } -val f_is_pos_zero : forall 'm, 'm in {16, 32, 64, 128}. bits('m) -> bool -function f_is_pos_zero xf = { +val f_is_pos_norm : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_pos_norm(xf) = { match 'm { - 16 => (xf == zeros()), - 32 => (xf == zeros()), - 64 => (xf == zeros()), - 128 => (xf == zeros()) + 16 => f_is_pos_norm_H(xf), + 32 => f_is_pos_norm_S(xf), + 64 => f_is_pos_norm_D(xf) + } +} + +val f_is_pos_inf : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_pos_inf(xf) = { + match 'm { + 16 => f_is_pos_inf_H(xf), + 32 => f_is_pos_inf_S(xf), + 64 => f_is_pos_inf_D(xf) + } +} + +val f_is_SNaN : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_SNaN(xf) = { + match 'm { + 16 => f_is_SNaN_H(xf), + 32 => f_is_SNaN_S(xf), + 64 => f_is_SNaN_D(xf) + } +} + +val f_is_QNaN : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_QNaN(xf) = { + match 'm { + 16 => f_is_QNaN_H(xf), + 32 => f_is_QNaN_S(xf), + 64 => f_is_QNaN_D(xf) + } +} + +val f_is_NaN : forall 'm, 'm in {16, 32, 64}. bits('m) -> bool +function f_is_NaN(xf) = { + match 'm { + 16 => f_is_NaN_H(xf), + 32 => f_is_NaN_S(xf), + 64 => f_is_NaN_D(xf) } } /* Scalar register shaping for floating point operations */ -val get_scalar_fp : forall 'n, 'n in {16, 32, 64, 128}. (regidx, int('n)) -> bits('n) effect {escape, rreg} +val get_scalar_fp : forall 'n, 'n in {16, 32, 64}. (regidx, int('n)) -> bits('n) effect {escape, rreg} function get_scalar_fp(rs1, SEW) = { if sizeof(flen) >= SEW then { /* Least significant SEW bits */ - NaN_unbox(F(rs1), SEW) + nan_unbox_vector(F(rs1), SEW) } else { assert(false, "invalid vector floating-point type width: FLEN < SEW"); zeros() @@ -560,16 +630,16 @@ function get_fixed_rounding_incr(vec_elem, shift_amount) = { 0b10 => 0b0, 0b11 => bool_to_bits( not(slice(vec_elem, shift_amount, 1) == 0b1) & (slice(vec_elem, 0, shift_amount) != zeros())) - } + } } } /* Fixed point unsigned saturation */ -val unsigned_saturation : forall ('m 'n: Int), ('n >= 'm > 0). (int('m), bits('n)) -> bits('m) effect {escape, rreg, undef, wreg} +val unsigned_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m) effect {escape, rreg, undef, wreg} function unsigned_saturation(len, elem) = { if unsigned(elem) > unsigned(ones('m)) then { vxsat = 0b1; - EXTZ('m, ones('m)) + ones('m) } else { vxsat = 0b0; elem['m - 1 .. 0] @@ -577,14 +647,14 @@ function unsigned_saturation(len, elem) = { } /* Fixed point signed saturation */ -val signed_saturation : forall ('m 'n: Int), ('n >= 'm > 0). (int('m), bits('n)) -> bits('m) effect {escape, rreg, undef, wreg} +val signed_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m) effect {escape, rreg, undef, wreg} function signed_saturation(len, elem) = { - if signed(elem) > signed(EXTZ('m, ones('m - 1))) then { + if signed(elem) > signed(0b0 @ ones('m - 1)) then { vxsat = 0b1; - EXTZ('m, ones('m - 1)) - } else if signed(elem) < signed(EXTZ('m, 0b1) << ('m - 1)) then { + 0b0 @ ones('m - 1) + } else if signed(elem) < signed(0b1 @ zeros('m - 1)) then { vxsat = 0b1; - to_bits('m, signed(EXTZ('m, 0b1) << ('m - 1))) + 0b1 @ zeros('m - 1) } else { vxsat = 0b0; elem['m - 1 .. 0] @@ -595,32 +665,20 @@ function signed_saturation(len, elem) = { val get_fp_rounding_mode : unit -> rounding_mode effect {rreg} function get_fp_rounding_mode() = encdec_rounding_mode(fcsr.FRM()) -/* Split sign and the remain of floating point number */ -val fsplitsign : forall 'n, 'n in {16, 32, 64}. bits('n) -> (bits(1), bits('n - 1)) -function fsplitsign (xf) = { - match 'n { - 16 => (xf[15..15], xf[14..0]), - 32 => (xf[31..31], xf[30..0]), - 64 => (xf[63..63], xf[62..0]) - } -} - -/* Make a floating point number by sign and the remains bits */ -val fmakesign : forall 'n, 'n in {16, 32, 64}. (bits(1), bits('n - 1)) -> bits('n) -function fmakesign (sign, remain) = sign @ remain - /* Negate a floating point number */ -val negate_fp : forall 'n, 'n in {16, 32, 64}. bits('n) -> bits('n) -function negate_fp (xf) = { - let (sign, remain) = fsplitsign(xf); - let new_sign = if (sign == 0b0) then 0b1 else 0b0; - fmakesign (new_sign, remain) +val negate_fp : forall 'm, 'm in {16, 32, 64}. bits('m) -> bits('m) +function negate_fp(xf) = { + match 'm { + 16 => negate_H(xf), + 32 => negate_S(xf), + 64 => negate_D(xf) + } } -/* Floating point functions */ -val fp_add: forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +/* Floating point functions using softfloat interface */ +val fp_add: forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_add(rm_3b, op1, op2) = { - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16Add(rm_3b, op1, op2), 32 => riscv_f32Add(rm_3b, op1, op2), 64 => riscv_f64Add(rm_3b, op1, op2) @@ -629,9 +687,9 @@ function fp_add(rm_3b, op1, op2) = { result_val } -val fp_sub: forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_sub: forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_sub(rm_3b, op1, op2) = { - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16Sub(rm_3b, op1, op2), 32 => riscv_f32Sub(rm_3b, op1, op2), 64 => riscv_f64Sub(rm_3b, op1, op2) @@ -640,15 +698,15 @@ function fp_sub(rm_3b, op1, op2) = { result_val } -val fp_min : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_min : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_min(op1, op2) = { - let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'n { + let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Lt_quiet(op1, op2), 32 => riscv_f32Lt_quiet(op1, op2), 64 => riscv_f64Lt_quiet(op1, op2) }; - let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('n) + let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('m) else if f_is_NaN(op1) then op2 else if f_is_NaN(op2) then op1 else if (f_is_neg_zero(op1) & f_is_pos_zero(op2)) then op1 @@ -659,15 +717,15 @@ function fp_min(op1, op2) = { result_val } -val fp_max : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_max : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_max(op1, op2) = { - let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'n { + let (fflags, op1_lt_op2) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Lt_quiet(op1, op2), 32 => riscv_f32Lt_quiet(op1, op2), 64 => riscv_f64Lt_quiet(op1, op2) }; - let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('n) + let result_val = if (f_is_NaN(op1) & f_is_NaN(op2)) then canonical_NaN('m) else if f_is_NaN(op1) then op2 else if f_is_NaN(op2) then op1 else if (f_is_neg_zero(op1) & f_is_pos_zero(op2)) then op2 @@ -678,9 +736,9 @@ function fp_max(op1, op2) = { result_val } -val fp_eq : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bool effect {escape, rreg, undef, wreg} +val fp_eq : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool effect {escape, rreg, undef, wreg} function fp_eq(op1, op2) = { - let (fflags, result_val) : (bits_fflags, bool) = match 'n { + let (fflags, result_val) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Eq(op1, op2), 32 => riscv_f32Eq(op1, op2), 64 => riscv_f64Eq(op1, op2) @@ -689,9 +747,9 @@ function fp_eq(op1, op2) = { result_val } -val fp_gt : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bool effect {escape, rreg, undef, wreg} +val fp_gt : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool effect {escape, rreg, undef, wreg} function fp_gt(op1, op2) = { - let (fflags, temp_val) : (bits_fflags, bool) = match 'n { + let (fflags, temp_val) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Le(op1, op2), 32 => riscv_f32Le(op1, op2), 64 => riscv_f64Le(op1, op2) @@ -701,9 +759,9 @@ function fp_gt(op1, op2) = { result_val } -val fp_ge : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bool effect {escape, rreg, undef, wreg} +val fp_ge : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool effect {escape, rreg, undef, wreg} function fp_ge(op1, op2) = { - let (fflags, temp_val) : (bits_fflags, bool) = match 'n { + let (fflags, temp_val) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Lt(op1, op2), 32 => riscv_f32Lt(op1, op2), 64 => riscv_f64Lt(op1, op2) @@ -713,9 +771,9 @@ function fp_ge(op1, op2) = { result_val } -val fp_lt : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bool effect {escape, rreg, undef, wreg} +val fp_lt : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool effect {escape, rreg, undef, wreg} function fp_lt(op1, op2) = { - let (fflags, result_val) : (bits_fflags, bool) = match 'n { + let (fflags, result_val) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Lt(op1, op2), 32 => riscv_f32Lt(op1, op2), 64 => riscv_f64Lt(op1, op2) @@ -724,9 +782,9 @@ function fp_lt(op1, op2) = { result_val } -val fp_le : forall 'n, 'n in {16, 32, 64}. (bits('n), bits('n)) -> bool effect {escape, rreg, undef, wreg} +val fp_le : forall 'm, 'm in {16, 32, 64}. (bits('m), bits('m)) -> bool effect {escape, rreg, undef, wreg} function fp_le(op1, op2) = { - let (fflags, result_val) : (bits_fflags, bool) = match 'n { + let (fflags, result_val) : (bits_fflags, bool) = match 'm { 16 => riscv_f16Le(op1, op2), 32 => riscv_f32Le(op1, op2), 64 => riscv_f64Le(op1, op2) @@ -735,9 +793,9 @@ function fp_le(op1, op2) = { result_val } -val fp_mul : forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_mul : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_mul(rm_3b, op1, op2) = { - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16Mul(rm_3b, op1, op2), 32 => riscv_f32Mul(rm_3b, op1, op2), 64 => riscv_f64Mul(rm_3b, op1, op2) @@ -746,9 +804,9 @@ function fp_mul(rm_3b, op1, op2) = { result_val } -val fp_div : forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_div : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_div(rm_3b, op1, op2) = { - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16Div(rm_3b, op1, op2), 32 => riscv_f32Div(rm_3b, op1, op2), 64 => riscv_f64Div(rm_3b, op1, op2) @@ -757,9 +815,9 @@ function fp_div(rm_3b, op1, op2) = { result_val } -val fp_muladd : forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_muladd : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_muladd(rm_3b, op1, op2, opadd) = { - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16MulAdd(rm_3b, op1, op2, opadd), 32 => riscv_f32MulAdd(rm_3b, op1, op2, opadd), 64 => riscv_f64MulAdd(rm_3b, op1, op2, opadd) @@ -768,10 +826,10 @@ function fp_muladd(rm_3b, op1, op2, opadd) = { result_val } -val fp_nmuladd : forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_nmuladd : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_nmuladd(rm_3b, op1, op2, opadd) = { let op1 = negate_fp(op1); - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16MulAdd(rm_3b, op1, op2, opadd), 32 => riscv_f32MulAdd(rm_3b, op1, op2, opadd), 64 => riscv_f64MulAdd(rm_3b, op1, op2, opadd) @@ -780,10 +838,10 @@ function fp_nmuladd(rm_3b, op1, op2, opadd) = { result_val } -val fp_mulsub : forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_mulsub : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_mulsub(rm_3b, op1, op2, opsub) = { let opsub = negate_fp(opsub); - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16MulAdd(rm_3b, op1, op2, opsub), 32 => riscv_f32MulAdd(rm_3b, op1, op2, opsub), 64 => riscv_f64MulAdd(rm_3b, op1, op2, opsub) @@ -792,11 +850,11 @@ function fp_mulsub(rm_3b, op1, op2, opsub) = { result_val } -val fp_nmulsub : forall 'n, 'n in {16, 32, 64}. (bits(3), bits('n), bits('n), bits('n)) -> bits('n) effect {escape, rreg, undef, wreg} +val fp_nmulsub : forall 'm, 'm in {16, 32, 64}. (bits(3), bits('m), bits('m), bits('m)) -> bits('m) effect {escape, rreg, undef, wreg} function fp_nmulsub(rm_3b, op1, op2, opsub) = { let opsub = negate_fp(opsub); let op1 = negate_fp(op1); - let (fflags, result_val) : (bits_fflags, bits('n)) = match 'n { + let (fflags, result_val) : (bits_fflags, bits('m)) = match 'm { 16 => riscv_f16MulAdd(rm_3b, op1, op2, opsub), 32 => riscv_f32MulAdd(rm_3b, op1, op2, opsub), 64 => riscv_f64MulAdd(rm_3b, op1, op2, opsub) @@ -805,6 +863,24 @@ function fp_nmulsub(rm_3b, op1, op2, opsub) = { result_val } +val fp_class : forall 'm, 'm in {16, 32, 64}. bits('m) -> bits('m) +function fp_class(xf) = { + let result_val_10b : bits(10) = + if f_is_neg_inf (xf) then 0b_00_0000_0001 + else if f_is_neg_norm (xf) then 0b_00_0000_0010 + else if f_is_neg_subnorm (xf) then 0b_00_0000_0100 + else if f_is_neg_zero (xf) then 0b_00_0000_1000 + else if f_is_pos_zero (xf) then 0b_00_0001_0000 + else if f_is_pos_subnorm (xf) then 0b_00_0010_0000 + else if f_is_pos_norm (xf) then 0b_00_0100_0000 + else if f_is_pos_inf (xf) then 0b_00_1000_0000 + else if f_is_SNaN (xf) then 0b_01_0000_0000 + else if f_is_QNaN (xf) then 0b_10_0000_0000 + else zeros(); + + EXTZ(result_val_10b) +} + val fp_widen : forall 'm, 'm in {16, 32}. bits('m) -> bits('m * 2) effect {escape, rreg, undef, wreg} function fp_widen(nval) = { let rm_3b = fcsr.FRM(); @@ -815,3 +891,275 @@ function fp_widen(nval) = { accrue_fflags(fflags); wval } + +/* Floating point functions without softfloat support */ +val riscv_f16ToI16 : (bits_rm, bits_H) -> (bits_fflags, bits(16)) effect {rreg} +function riscv_f16ToI16 (rm, v) = { + let (_, sig32) = riscv_f16ToI32(rm, v); + if signed(sig32) > signed(0b0 @ ones(15)) then (nvFlag(), 0b0 @ ones(15)) + else if signed(sig32) < signed(0b1 @ zeros(15)) then (nvFlag(), 0b1 @ zeros(15)) + else (zeros(5), sig32[15 .. 0]); +} + +val riscv_f16ToI8 : (bits_rm, bits_H) -> (bits_fflags, bits(8)) effect {rreg} +function riscv_f16ToI8 (rm, v) = { + let (_, sig32) = riscv_f16ToI32(rm, v); + if signed(sig32) > signed(0b0 @ ones(7)) then (nvFlag(), 0b0 @ ones(7)) + else if signed(sig32) < signed(0b1 @ zeros(7)) then (nvFlag(), 0b1 @ zeros(7)) + else (zeros(5), sig32[7 .. 0]); +} + +val riscv_f32ToI16 : (bits_rm, bits_S) -> (bits_fflags, bits(16)) effect {rreg} +function riscv_f32ToI16 (rm, v) = { + let (_, sig32) = riscv_f32ToI32(rm, v); + if signed(sig32) > signed(0b0 @ ones(15)) then (nvFlag(), 0b0 @ ones(15)) + else if signed(sig32) < signed(0b1 @ zeros(15)) then (nvFlag(), 0b1 @ zeros(15)) + else (zeros(5), sig32[15 .. 0]); +} + +val riscv_f16ToUi16 : (bits_rm, bits_H) -> (bits_fflags, bits(16)) effect {rreg} +function riscv_f16ToUi16 (rm, v) = { + let (_, sig32) = riscv_f16ToUi32(rm, v); + if unsigned(sig32) > unsigned(ones(16)) then (nvFlag(), ones(16)) + else (zeros(5), sig32[15 .. 0]); +} + +val riscv_f16ToUi8 : (bits_rm, bits_H) -> (bits_fflags, bits(8)) effect {rreg} +function riscv_f16ToUi8 (rm, v) = { + let (_, sig32) = riscv_f16ToUi32(rm, v); + if unsigned(sig32) > unsigned(ones(8)) then (nvFlag(), ones(8)) + else (zeros(5), sig32[7 .. 0]); +} + +val riscv_f32ToUi16 : (bits_rm, bits_S) -> (bits_fflags, bits(16)) effect {rreg} +function riscv_f32ToUi16 (rm, v) = { + let (_, sig32) = riscv_f32ToUi32(rm, v); + if unsigned(sig32) > unsigned(ones(16)) then (nvFlag(), ones(16)) + else (zeros(5), sig32[15 .. 0]); +} + +val count_leadingzeros : (bits(64), int) -> int +function count_leadingzeros (sig, len) = { + idx : int = -1; + assert(len == 10 | len == 23 | len == 52); + foreach (i from 0 to (len - 1)) { + if sig[i] == bitone then idx = i; + }; + len - idx - 1 +} + +val rsqrt7 : forall 'm, 'm in {16, 32, 64}. (bits('m), bool) -> bits_D +function rsqrt7 (v, sub) = { + let (sig, exp, sign, e, s) : (bits(64), bits(64), bits(1), nat, nat) = match 'm { + 16 => (EXTZ(64, v[9 .. 0]), EXTZ(64, v[14 .. 10]), [v[15]], 5, 10), + 32 => (EXTZ(64, v[22 .. 0]), EXTZ(64, v[30 .. 23]), [v[31]], 8, 23), + 64 => (EXTZ(64, v[51 .. 0]), EXTZ(64, v[62 .. 52]), [v[63]], 11, 52) + }; + assert(s == 10 & e == 5 | s == 23 & e == 8 | s == 52 & e == 11); + let table : vector(128, dec, int) = [ + 52, 51, 50, 48, 47, 46, 44, 43, + 42, 41, 40, 39, 38, 36, 35, 34, + 33, 32, 31, 30, 30, 29, 28, 27, + 26, 25, 24, 23, 23, 22, 21, 20, + 19, 19, 18, 17, 16, 16, 15, 14, + 14, 13, 12, 12, 11, 10, 10, 9, + 9, 8, 7, 7, 6, 6, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0, + 127, 125, 123, 121, 119, 118, 116, 114, + 113, 111, 109, 108, 106, 105, 103, 102, + 100, 99, 97, 96, 95, 93, 92, 91, + 90, 88, 87, 86, 85, 84, 83, 82, + 80, 79, 78, 77, 76, 75, 74, 73, + 72, 71, 70, 70, 69, 68, 67, 66, + 65, 64, 63, 63, 62, 61, 60, 59, + 59, 58, 57, 56, 56, 55, 54, 53]; + + let (normalized_exp, normalized_sig) = + if sub then { + let nr_leadingzeros = count_leadingzeros(sig, s); + assert(nr_leadingzeros >= 0); + (to_bits(64, (0 - nr_leadingzeros)), EXTZ(64, sig[(s - 1) .. 0] << (1 + nr_leadingzeros))) + } else { + (exp, sig) + }; + + let idx : nat = match 'm { + 16 => unsigned([normalized_exp[0]] @ normalized_sig[9 .. 4]), + 32 => unsigned([normalized_exp[0]] @ normalized_sig[22 .. 17]), + 64 => unsigned([normalized_exp[0]] @ normalized_sig[51 .. 46]) + }; + assert(idx >= 0 & idx < 128); + let out_sig = to_bits(s, table[(127 - idx)]) << (s - 7); + let out_exp = to_bits(e, (3 * (2^(e - 1) - 1) - 1 - signed(normalized_exp)) / 2); + EXTZ(64, sign @ out_exp @ out_sig) +} + +val riscv_f16Rsqrte7 : (bits_rm, bits_H) -> (bits_fflags, bits_H) effect {rreg} +function riscv_f16Rsqrte7 (rm, v) = { + let class = fp_class(v); + let (fflags, result) : (bits_fflags, bits_H)= match class { + 0x0001 => (nvFlag(), 0x7e00), + 0x0002 => (nvFlag(), 0x7e00), + 0x0004 => (nvFlag(), 0x7e00), + 0x0100 => (nvFlag(), 0x7e00), + 0x0200 => (zeros(5), 0x7e00), + 0x0008 => (dzFlag(), 0xfc00), + 0x0010 => (dzFlag(), 0x7c00), + 0x0080 => (zeros(5), 0x0000), + 0x0020 => (zeros(5), rsqrt7(v, true)[15 .. 0]), + _ => (zeros(5), rsqrt7(v, false)[15 .. 0]) + }; + (fflags, result) +} + +val riscv_f32Rsqrte7 : (bits_rm, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Rsqrte7 (rm, v) = { + let class = fp_class(v); + let (fflags, result) : (bits_fflags, bits_S)= match class[15 .. 0] { + 0x0001 => (nvFlag(), 0x7fc00000), + 0x0002 => (nvFlag(), 0x7fc00000), + 0x0004 => (nvFlag(), 0x7fc00000), + 0x0100 => (nvFlag(), 0x7fc00000), + 0x0200 => (zeros(5), 0x7fc00000), + 0x0008 => (dzFlag(), 0xff800000), + 0x0010 => (dzFlag(), 0x7f800000), + 0x0080 => (zeros(5), 0x00000000), + 0x0020 => (zeros(5), rsqrt7(v, true)[31 .. 0]), + _ => (zeros(5), rsqrt7(v, false)[31 .. 0]) + }; + (fflags, result) +} + +val riscv_f64Rsqrte7 : (bits_rm, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Rsqrte7 (rm, v) = { + let class = fp_class(v); + let (fflags, result) : (bits_fflags, bits_D)= match class[15 .. 0] { + 0x0001 => (nvFlag(), 0x7ff8000000000000), + 0x0002 => (nvFlag(), 0x7ff8000000000000), + 0x0004 => (nvFlag(), 0x7ff8000000000000), + 0x0100 => (nvFlag(), 0x7ff8000000000000), + 0x0200 => (zeros(5), 0x7ff8000000000000), + 0x0008 => (dzFlag(), 0xfff0000000000000), + 0x0010 => (dzFlag(), 0x7ff0000000000000), + 0x0080 => (zeros(5), zeros(64)), + 0x0020 => (zeros(5), rsqrt7(v, true)[63 .. 0]), + _ => (zeros(5), rsqrt7(v, false)[63 .. 0]) + }; + (fflags, result) +} + +val recip7 : forall 'm, 'm in {16, 32, 64}. (bits('m), bits(3), bool) -> (bool, bits_D) +function recip7 (v, rm_3b, sub) = { + let (sig, exp, sign, e, s) : (bits(64), bits(64), bits(1), nat, nat) = match 'm { + 16 => (EXTZ(64, v[9 .. 0]), EXTZ(64, v[14 .. 10]), [v[15]], 5, 10), + 32 => (EXTZ(64, v[22 .. 0]), EXTZ(64, v[30 .. 23]), [v[31]], 8, 23), + 64 => (EXTZ(64, v[51 .. 0]), EXTZ(64, v[62 .. 52]), [v[63]], 11, 52) + }; + assert(s == 10 & e == 5 | s == 23 & e == 8 | s == 52 & e == 11); + let table : vector(128, dec, int) = [ + 127, 125, 123, 121, 119, 117, 116, 114, + 112, 110, 109, 107, 105, 104, 102, 100, + 99, 97, 96, 94, 93, 91, 90, 88, + 87, 85, 84, 83, 81, 80, 79, 77, + 76, 75, 74, 72, 71, 70, 69, 68, + 66, 65, 64, 63, 62, 61, 60, 59, + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 40, 40, 39, 38, 37, 36, + 35, 35, 34, 33, 32, 31, 31, 30, + 29, 28, 28, 27, 26, 25, 25, 24, + 23, 23, 22, 21, 21, 20, 19, 19, + 18, 17, 17, 16, 15, 15, 14, 14, + 13, 12, 12, 11, 11, 10, 9, 9, + 8, 8, 7, 7, 6, 5, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0]; + + let nr_leadingzeros = count_leadingzeros(sig, s); + assert(nr_leadingzeros >= 0); + let (normalized_exp, normalized_sig) = + if sub then { + (to_bits(64, (0 - nr_leadingzeros)), EXTZ(64, sig[(s - 1) .. 0] << (1 + nr_leadingzeros))) + } else { + (exp, sig) + }; + + let idx : nat = match 'm { + 16 => unsigned(normalized_sig[9 .. 3]), + 32 => unsigned(normalized_sig[22 .. 16]), + 64 => unsigned(normalized_sig[51 .. 45]) + }; + assert(idx >= 0 & idx < 128); + let mid_exp = to_bits(e, 2 * (2^(e - 1) - 1) - 1 - signed(normalized_exp)); + let mid_sig = to_bits(s, table[(127 - idx)]) << (s - 7); + + let (out_exp, out_sig)= + if mid_exp == zeros(e) then { + (mid_exp, mid_sig >> 1 | 0b1 @ zeros(s - 1)) + } else if mid_exp == ones(e) then { + (zeros(e), mid_sig >> 2 | 0b01 @ zeros(s - 2)) + } else (mid_exp, mid_sig); + + if sub & nr_leadingzeros > 1 then { + if (rm_3b == 0b001 | rm_3b == 0b010 & sign == 0b0 | rm_3b == 0b011 & sign == 0b1) then { + (true, EXTZ(64, sign @ ones(e - 1) @ 0b0 @ ones(s))) + } + else (true, EXTZ(64, sign @ ones(e) @ zeros(s))) + } else (false, EXTZ(64, sign @ out_exp @ out_sig)) +} + +val riscv_f16Recip7 : (bits_rm, bits_H) -> (bits_fflags, bits_H) effect {rreg} +function riscv_f16Recip7 (rm, v) = { + let class = fp_class(v); + let (round_abnormal_true, res_true) = recip7(v, rm, true); + let (round_abnormal_false, res_false) = recip7(v, rm, false); + let (fflags, result) : (bits_fflags, bits_H) = match class { + 0x0001 => (zeros(5), 0x8000), + 0x0080 => (zeros(5), 0x0000), + 0x0008 => (dzFlag(), 0xfc00), + 0x0010 => (dzFlag(), 0x7c00), + 0x0100 => (nvFlag(), 0x7e00), + 0x0200 => (zeros(5), 0x7e00), + 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[15 .. 0]) else (zeros(5), res_true[15 .. 0]), + 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[15 .. 0]) else (zeros(5), res_true[15 .. 0]), + _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[15 .. 0]) else (zeros(5), res_false[15 .. 0]) + }; + (fflags, result) +} + +val riscv_f32Recip7 : (bits_rm, bits_S) -> (bits_fflags, bits_S) effect {rreg} +function riscv_f32Recip7 (rm, v) = { + let class = fp_class(v); + let (round_abnormal_true, res_true) = recip7(v, rm, true); + let (round_abnormal_false, res_false) = recip7(v, rm, false); + let (fflags, result) : (bits_fflags, bits_S) = match class[15 .. 0] { + 0x0001 => (zeros(5), 0x80000000), + 0x0080 => (zeros(5), 0x00000000), + 0x0008 => (dzFlag(), 0xff800000), + 0x0010 => (dzFlag(), 0x7f800000), + 0x0100 => (nvFlag(), 0x7fc00000), + 0x0200 => (zeros(5), 0x7fc00000), + 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[31 .. 0]) else (zeros(5), res_true[31 .. 0]), + 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[31 .. 0]) else (zeros(5), res_true[31 .. 0]), + _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[31 .. 0]) else (zeros(5), res_false[31 .. 0]) + }; + (fflags, result) +} + +val riscv_f64Recip7 : (bits_rm, bits_D) -> (bits_fflags, bits_D) effect {rreg} +function riscv_f64Recip7 (rm, v) = { + let class = fp_class(v); + let (round_abnormal_true, res_true) = recip7(v, rm, true); + let (round_abnormal_false, res_false) = recip7(v, rm, false); + let (fflags, result) : (bits_fflags, bits_D) = match class[15 .. 0] { + 0x0001 => (zeros(5), 0x8000000000000000), + 0x0080 => (zeros(5), 0x0000000000000000), + 0x0008 => (dzFlag(), 0xfff0000000000000), + 0x0010 => (dzFlag(), 0x7ff0000000000000), + 0x0100 => (nvFlag(), 0x7ff8000000000000), + 0x0200 => (zeros(5), 0x7ff8000000000000), + 0x0004 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[63 .. 0]) else (zeros(5), res_true[63 .. 0]), + 0x0020 => if round_abnormal_true then (nxFlag() | ofFlag(), res_true[63 .. 0]) else (zeros(5), res_true[63 .. 0]), + _ => if round_abnormal_false then (nxFlag() | ofFlag(), res_false[63 .. 0]) else (zeros(5), res_false[63 .. 0]) + }; + (fflags, result) +} diff --git a/model/riscv_insts_vext_vm.sail b/model/riscv_insts_vext_vm.sail index 6784ce7e4..a741bbce8 100755 --- a/model/riscv_insts_vext_vm.sail +++ b/model/riscv_insts_vext_vm.sail @@ -85,7 +85,7 @@ function clause execute(VVMTYPE(funct6, vs2, vs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -140,7 +140,7 @@ function clause execute(VVMCTYPE(funct6, vs2, vs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -201,7 +201,7 @@ function clause execute(VVMSTYPE(funct6, vs2, vs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -263,7 +263,7 @@ function clause execute(VVCMPTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -323,7 +323,7 @@ function clause execute(VXMTYPE(funct6, vs2, rs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -378,7 +378,7 @@ function clause execute(VXMCTYPE(funct6, vs2, rs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -439,7 +439,7 @@ function clause execute(VXMSTYPE(funct6, vs2, rs1, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -505,7 +505,7 @@ function clause execute(VXCMPTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -565,7 +565,7 @@ function clause execute(VIMTYPE(funct6, vs2, simm, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -617,7 +617,7 @@ function clause execute(VIMCTYPE(funct6, vs2, simm, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -675,7 +675,7 @@ function clause execute(VIMSTYPE(funct6, vs2, simm, vd)) = { }; write_vreg(num_elem, SEW, LMUL_pow, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -736,7 +736,7 @@ function clause execute(VICMPTYPE(funct6, vm, vs2, simm, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -781,7 +781,7 @@ function clause execute(FVVMTYPE(funct6, vm, vs2, vs1, vd)) = { let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); - let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; @@ -800,7 +800,7 @@ function clause execute(FVVMTYPE(funct6, vm, vs2, vs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } @@ -845,7 +845,7 @@ function clause execute(FVFMTYPE(funct6, vm, vs2, rs1, vd)) = { let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); - let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); result : vector('n, dec, bool) = undefined; mask : vector('n, dec, bool) = undefined; @@ -866,7 +866,7 @@ function clause execute(FVFMTYPE(funct6, vm, vs2, rs1, vd)) = { }; write_vmask(num_elem, vd, result); - vstart = EXTZ(0b0); + vstart = zeros(); RETIRE_SUCCESS } diff --git a/model/riscv_insts_vext_vset.sail b/model/riscv_insts_vext_vset.sail index 2ae1854b3..a37a65e50 100644 --- a/model/riscv_insts_vext_vset.sail +++ b/model/riscv_insts_vext_vset.sail @@ -79,14 +79,14 @@ mapping encdec_vsetop : vsetop <-> bits(4) ={ VSETVL <-> 0b1000 } -mapping clause encdec = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) if haveRVV() +mapping clause encdec = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) if haveRVV() <-> encdec_vsetop(op) @ ma @ ta @ sew @ lmul @ rs1 @ 0b111 @ rd @ 0b1010111 if haveRVV() function clause execute VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) = { let VLEN_pow = get_vlen_pow(); let ELEN_pow = get_elen_pow(); let LMUL_pow_ori = get_lmul_pow(); - let SEW_pow_ori = get_sew_pow(); + let SEW_pow_ori = get_sew_pow(); let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; /* set vtype */ @@ -127,7 +127,7 @@ function clause execute VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) = { } else { /* keep existing vl */ let AVL = unsigned(vl); let ratio_pow_new = SEW_pow_new - LMUL_pow_new; - if (ratio_pow_new != ratio_pow_ori) then { + if (ratio_pow_new != ratio_pow_ori) then { vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ vl = EXTZ(0b0); } @@ -136,7 +136,7 @@ function clause execute VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) = { print_reg("CSR vl <- " ^ BitStr(vl)); /* reset vstart to 0 */ - vstart = EXTZ(0b0); + vstart = zeros(); print_reg("CSR vstart <- " ^ BitStr(vstart)); RETIRE_SUCCESS @@ -147,20 +147,20 @@ mapping vsettype_mnemonic : vsetop <-> string ={ VSETVL <-> "vsetvli" } -mapping clause assembly = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) +mapping clause assembly = VSET_TYPE(op, ma, ta, sew, lmul, rs1, rd) <-> vsettype_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ sew_flag(sew) ^ maybe_lmul_flag(lmul) ^ maybe_ta_flag(ta) ^ maybe_ma_flag(ma) /* ********************************* vsetivli ************************************ */ union clause ast = VSETI_TYPE : ( bits(1), bits(1), bits(3), bits(3), regidx, regidx) -mapping clause encdec = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) if haveRVV() +mapping clause encdec = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) if haveRVV() <-> 0b1100 @ ma @ ta @ sew @ lmul @ uimm @ 0b111 @ rd @ 0b1010111 if haveRVV() function clause execute VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) = { let VLEN_pow = get_vlen_pow(); let ELEN_pow = get_elen_pow(); let LMUL_pow_ori = get_lmul_pow(); - let SEW_pow_ori = get_sew_pow(); + let SEW_pow_ori = get_sew_pow(); let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; /* set vtype */ @@ -188,11 +188,11 @@ function clause execute VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) = { print_reg("CSR vl <- " ^ BitStr(vl)); /* reset vstart to 0 */ - vstart = EXTZ(0b0); + vstart = zeros(); print_reg("CSR vstart <- " ^ BitStr(vstart)); RETIRE_SUCCESS } -mapping clause assembly = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) +mapping clause assembly = VSETI_TYPE(ma, ta, sew, lmul, uimm, rd) <-> "vsetivli" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_5(uimm) ^ sep() ^ sew_flag(sew) ^ maybe_lmul_flag(lmul) ^ maybe_ta_flag(ta) ^ maybe_ma_flag(ma) diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index 56b78974e..e27893882 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -133,7 +133,7 @@ function readCSR csr : csreg -> xlenbits = { (0xB80, 32) => mcycle[63 .. 32], (0xB82, 32) => minstret[63 .. 32], - /* vector csr*/ + /* vector */ (0x008, _) => EXTZ(vstart), (0x009, _) => EXTZ(vxsat), (0x00A, _) => EXTZ(vxrm), @@ -250,11 +250,11 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = { /* user mode: seed (entropy source). writes are ignored */ (0x015, _) => write_seed_csr(), - /* vector csr */ + /* vector */ (0x008, _) => { let vstart_length = get_vlen_pow(); vstart = EXTZ(16, value[(vstart_length - 1) .. 0]); Some(EXTZ(vstart)) }, (0x009, _) => { vxsat = value[0 .. 0]; Some(EXTZ(vxsat)) }, (0x00A, _) => { vxrm = value[1 .. 0]; Some(EXTZ(vxrm)) }, - (0x00F, _) => { vcsr->bits() = value[2 ..0]; Some(EXTZ(vcsr.bits())) }, + (0x00F, _) => { vcsr->bits() = value[2 ..0]; Some(EXTZ(vcsr.bits())) }, (0xC20, _) => { vl = value; Some(vl) }, (0xC21, _) => { vtype->bits() = value; Some(vtype.bits()) }, (0xC22, _) => { vlenb = value; Some(vlenb) }, diff --git a/model/riscv_softfloat_interface.sail b/model/riscv_softfloat_interface.sail index 6a3c06ec4..712c3e791 100644 --- a/model/riscv_softfloat_interface.sail +++ b/model/riscv_softfloat_interface.sail @@ -245,109 +245,9 @@ function riscv_f64Sqrt (rm, v) = { (float_fflags[4 .. 0], float_result) } -/* **************************************************************** */ -/* RECIPROCAL SQUARE ROOT ESTIMATE */ - -val extern_f16Rsqrte7 = {c: "softfloat_f16rsqrte7", ocaml: "Softfloat.f16_rsqrte7", lem: "softfloat_f16_rsqrte7"} : (bits_rm, bits_H) -> unit -val riscv_f16Rsqrte7 : (bits_rm, bits_H) -> (bits_fflags, bits_H) effect {rreg} -function riscv_f16Rsqrte7 (rm, v) = { - extern_f16Rsqrte7(rm, v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} - -val extern_f32Rsqrte7 = {c: "softfloat_f32rsqrte7", ocaml: "Softfloat.f32_rsqrte7", lem: "softfloat_f32_rsqrte7"} : (bits_rm, bits_S) -> unit -val riscv_f32Rsqrte7 : (bits_rm, bits_S) -> (bits_fflags, bits_S) effect {rreg} -function riscv_f32Rsqrte7 (rm, v) = { - extern_f32Rsqrte7(rm, v); - (float_fflags[4 .. 0], float_result[31 .. 0]) -} - -val extern_f64Rsqrte7 = {c: "softfloat_f64rsqrte7", ocaml: "Softfloat.f64_rsqrte7", lem: "softfloat_f64_rsqrte7"} : (bits_rm, bits_D) -> unit -val riscv_f64Rsqrte7 : (bits_rm, bits_D) -> (bits_fflags, bits_D) effect {rreg} -function riscv_f64Rsqrte7 (rm, v) = { - extern_f64Rsqrte7(rm, v); - (float_fflags[4 .. 0], float_result) -} - -/* **************************************************************** */ -/* RECIPROCAL ESTIMATE */ - -val extern_f16Recip7 = {c: "softfloat_f16recip7", ocaml: "Softfloat.f16_recip7", lem: "softfloat_f16_recip7"} : (bits_rm, bits_H) -> unit -val riscv_f16Recip7 : (bits_rm, bits_H) -> (bits_fflags, bits_H) effect {rreg} -function riscv_f16Recip7 (rm, v) = { - extern_f16Recip7(rm, v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} - -val extern_f32Recip7 = {c: "softfloat_f32recip7", ocaml: "Softfloat.f32_recip7", lem: "softfloat_f32_recip7"} : (bits_rm, bits_S) -> unit -val riscv_f32Recip7 : (bits_rm, bits_S) -> (bits_fflags, bits_S) effect {rreg} -function riscv_f32Recip7 (rm, v) = { - extern_f32Recip7(rm, v); - (float_fflags[4 .. 0], float_result[31 .. 0]) -} - -val extern_f64Recip7 = {c: "softfloat_f64recip7", ocaml: "Softfloat.f64_recip7", lem: "softfloat_f64_recip7"} : (bits_rm, bits_D) -> unit -val riscv_f64Recip7 : (bits_rm, bits_D) -> (bits_fflags, bits_D) effect {rreg} -function riscv_f64Recip7 (rm, v) = { - extern_f64Recip7(rm, v); - (float_fflags[4 .. 0], float_result) -} - -/* **************************************************************** */ -/* CLASSIFY */ - -val extern_f16Class = {c: "softfloat_f16class", ocaml: "Softfloat.f16_class", lem: "softfloat_f16_class"} : bits_H -> unit -val riscv_f16Class : bits_H -> (bits_fflags, bits_H) effect {rreg} -function riscv_f16Class (v) = { - extern_f16Class(v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} - -val extern_f32Class = {c: "softfloat_f32class", ocaml: "Softfloat.f32_class", lem: "softfloat_f32_class"} : bits_S -> unit -val riscv_f32Class : bits_S -> (bits_fflags, bits_S) effect {rreg} -function riscv_f32Class (v) = { - extern_f32Class(v); - (float_fflags[4 .. 0], float_result[31 .. 0]) -} - -val extern_f64Class = {c: "softfloat_f64class", ocaml: "Softfloat.f64_class", lem: "softfloat_f64_class"} : bits_D -> unit -val riscv_f64Class : bits_D -> (bits_fflags, bits_D) effect {rreg} -function riscv_f64Class (v) = { - extern_f64Class(v); - (float_fflags[4 .. 0], float_result) -} - /* **************************************************************** */ /* CONVERSIONS */ -val extern_f16ToI8 = {c: "softfloat_f16toi8", ocaml: "Softfloat.f16_to_i8", lem: "softfloat_f16_to_i8"} : (bits_rm, bits_H) -> unit -val riscv_f16ToI8 : (bits_rm, bits_H) -> (bits_fflags, bits(8)) effect {rreg} -function riscv_f16ToI8 (rm, v) = { - extern_f16ToI8(rm, v); - (float_fflags[4 .. 0], float_result[7 .. 0]) -} - -val extern_f16ToUi8 = {c: "softfloat_f16toui8", ocaml: "Softfloat.f16_to_ui8", lem: "softfloat_f16_to_ui8"} : (bits_rm, bits_H) -> unit -val riscv_f16ToUi8 : (bits_rm, bits_H) -> (bits_fflags, bits(8)) effect {rreg} -function riscv_f16ToUi8 (rm, v) = { - extern_f16ToUi8(rm, v); - (float_fflags[4 .. 0], float_result[7 .. 0]) -} - -val extern_f16ToI16 = {c: "softfloat_f16toi16", ocaml: "Softfloat.f16_to_i16", lem: "softfloat_f16_to_i16"} : (bits_rm, bits_H) -> unit -val riscv_f16ToI16 : (bits_rm, bits_H) -> (bits_fflags, bits(16)) effect {rreg} -function riscv_f16ToI16 (rm, v) = { - extern_f16ToI16(rm, v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} - -val extern_f16ToUi16 = {c: "softfloat_f16toui16", ocaml: "Softfloat.f16_to_ui16", lem: "softfloat_f16_to_ui16"} : (bits_rm, bits_H) -> unit -val riscv_f16ToUi16 : (bits_rm, bits_H) -> (bits_fflags, bits(16)) effect {rreg} -function riscv_f16ToUi16 (rm, v) = { - extern_f16ToUi16(rm, v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} - val extern_f16ToI32 = {c: "softfloat_f16toi32", ocaml: "Softfloat.f16_to_i32", lem: "softfloat_f16_to_i32"} : (bits_rm, bits_H) -> unit val riscv_f16ToI32 : (bits_rm, bits_H) -> (bits_fflags, bits_W) effect {rreg} function riscv_f16ToI32 (rm, v) = { @@ -404,19 +304,6 @@ function riscv_ui64ToF16 (rm, v) = { (float_fflags[4 .. 0], float_result[15 .. 0]) } -val extern_f32ToI16 = {c: "softfloat_f32toi16", ocaml: "Softfloat.f32_to_i16", lem: "softfloat_f32_to_i16"} : (bits_rm, bits_S) -> unit -val riscv_f32ToI16 : (bits_rm, bits_S) -> (bits_fflags, bits(16)) effect {rreg} -function riscv_f32ToI16 (rm, v) = { - extern_f32ToI16(rm, v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} - -val extern_f32ToUi16 = {c: "softfloat_f32toui16", ocaml: "Softfloat.f32_to_ui16", lem: "softfloat_f32_to_ui16"} : (bits_rm, bits_S) -> unit -val riscv_f32ToUi16 : (bits_rm, bits_S) -> (bits_fflags, bits(16)) effect {rreg} -function riscv_f32ToUi16 (rm, v) = { - extern_f32ToUi16(rm, v); - (float_fflags[4 .. 0], float_result[15 .. 0]) -} val extern_f32ToI32 = {c: "softfloat_f32toi32", ocaml: "Softfloat.f32_to_i32", lem: "softfloat_f32_to_i32"} : (bits_rm, bits_S) -> unit val riscv_f32ToI32 : (bits_rm, bits_S) -> (bits_fflags, bits_W) effect {rreg} diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 7e3bff11b..98310546a 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -610,7 +610,7 @@ function init_sys() -> unit = { vtype->vta() = 0b0; vtype->vsew() = 0b000; vtype->vlmul() = 0b000; - vlenb = EXTZ(0b0); + vlenb = EXTZ(0b0); init_pmp(); diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 5169e73f9..17954fa88 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -897,18 +897,16 @@ function get_lmul_pow() = { enum agtype = { UNDISTURBED, AGNOSTIC } -val get_vtype_vma : unit -> agtype effect {rreg} -function get_vtype_vma() = { - match vtype.vma() { +val decode_agtype : bits(1) -> agtype +function decode_agtype(ag) = { + match ag { 0b0 => UNDISTURBED, 0b1 => AGNOSTIC } } +val get_vtype_vma : unit -> agtype effect {rreg} +function get_vtype_vma() = decode_agtype(vtype.vma()) + val get_vtype_vta : unit -> agtype effect {rreg} -function get_vtype_vta() = { - match vtype.vta() { - 0b0 => UNDISTURBED, - 0b1 => AGNOSTIC - } -} +function get_vtype_vta() = decode_agtype(vtype.vta()) diff --git a/model/riscv_vext_regs.sail b/model/riscv_vext_regs.sail index cd85ff737..3abaa25ff 100644 --- a/model/riscv_vext_regs.sail +++ b/model/riscv_vext_regs.sail @@ -238,7 +238,7 @@ function init_vregs () = { vr31 = zero_vreg } -/* Vector CSR */ +/* Vector CSR */ bitfield Vcsr : bits(3) = { vxrm : 2 .. 1, vxsat : 0 @@ -307,7 +307,7 @@ function read_vreg(num_elem, SEW, LMUL_pow, vrid) = { /* vrid must be a multiple of emul */ assert(false, "invalid register group: vrid is not a multiple of EMUL") } else { - if LMUL_pow < 0 then { + if LMUL_pow < 0 then { result = read_single_vreg('n, SEW, vrid); } else { let 'num_elem_single : int = VLEN / SEW; @@ -330,20 +330,20 @@ function read_vreg(num_elem, SEW, LMUL_pow, vrid) = { } /* Single element reading operation */ -val read_single_element : forall 'm 'x 'p, 8 <= 'm <= 128. (int('m), int('x), int('p), regidx) -> bits('m) effect {escape, rreg, undef} -function read_single_element(EEW, index, EMUL_pow, vrid) = { +val read_single_element : forall 'm 'x, 8 <= 'm <= 128. (int('m), int('x), regidx) -> bits('m) effect {escape, rreg, undef} +function read_single_element(EEW, index, vrid) = { let VLEN = int_power(2, get_vlen_pow()); assert(VLEN >= EEW); let 'elem_per_reg : int = VLEN / EEW; - let real_vrid : regidx = if EMUL_pow > 0 then vrid + to_bits(5, index / 'elem_per_reg) else vrid; - let real_index : int = if EMUL_pow > 0 then index % 'elem_per_reg else index; + let real_vrid : regidx = vrid + to_bits(5, index / 'elem_per_reg); + let real_index : int = index % 'elem_per_reg; let vrid_val : vector('elem_per_reg, dec, bits('m)) = read_single_vreg('elem_per_reg, EEW, real_vrid); assert(0 <= real_index & real_index < 'elem_per_reg); vrid_val[real_index] } /* The general vreg writing operation with num_elem as max(VLMAX,VLEN/SEW)) */ -val write_vreg : forall 'n 'm 'p. (int('n), int('m), int('p), regidx, vector('n, dec, bits('m))) -> unit effect {escape, rreg, undef, wreg} +val write_vreg : forall 'n 'm 'p. (int('n), int('m), int('p), regidx, vector('n, dec, bits('m))) -> unit effect {escape, rreg, undef, wreg} function write_vreg(num_elem, SEW, LMUL_pow, vrid, vec) = { let VLEN = int_power(2, get_vlen_pow()); let LMUL_pow_reg = if LMUL_pow < 0 then 0 else LMUL_pow; @@ -365,12 +365,12 @@ function write_vreg(num_elem, SEW, LMUL_pow, vrid, vec) = { } /* Single element writing operation */ -val write_single_element : forall 'm 'x 'p, 8 <= 'm <= 128. (int('m), int('x), int('p), regidx, bits('m)) -> unit effect {escape, rreg, undef, wreg} -function write_single_element(EEW, index, EMUL_pow, vrid, value) = { +val write_single_element : forall 'm 'x, 8 <= 'm <= 128. (int('m), int('x), regidx, bits('m)) -> unit effect {escape, rreg, undef, wreg} +function write_single_element(EEW, index, vrid, value) = { let VLEN = int_power(2, get_vlen_pow()); let 'elem_per_reg : int = VLEN / EEW; - let real_vrid : regidx = if EMUL_pow > 0 then vrid + to_bits(5, index / 'elem_per_reg) else vrid; - let real_index : int = if EMUL_pow > 0 then index % 'elem_per_reg else index; + let real_vrid : regidx = vrid + to_bits(5, index / 'elem_per_reg); + let real_index : int = index % 'elem_per_reg; let vrid_val : vector('elem_per_reg, dec, bits('m)) = read_single_vreg('elem_per_reg, EEW, real_vrid); r : vregtype = zeros(); diff --git a/model/riscv_vreg_type.sail b/model/riscv_vreg_type.sail index de44a5c56..6f553757b 100755 --- a/model/riscv_vreg_type.sail +++ b/model/riscv_vreg_type.sail @@ -46,8 +46,8 @@ type vregtype = vreglenbits /* vector instruction types */ enum vsetop = { VSETVLI, VSETVL } -enum vvfunct6 = { VV_VADD, VV_VSUB, VV_VMINU, VV_VMIN, VV_VMAXU, VV_VMAX, VV_VAND, VV_VOR, VV_VXOR, - VV_VRGATHER, VV_VRGATHEREI16, VV_VSADDU, VV_VSADD, VV_VSSUBU, VV_VSSUB, VV_VSLL, VV_VSMUL, +enum vvfunct6 = { VV_VADD, VV_VSUB, VV_VMINU, VV_VMIN, VV_VMAXU, VV_VMAX, VV_VAND, VV_VOR, VV_VXOR, + VV_VRGATHER, VV_VRGATHEREI16, VV_VSADDU, VV_VSADD, VV_VSSUBU, VV_VSSUB, VV_VSLL, VV_VSMUL, VV_VSRL, VV_VSRA, VV_VSSRL, VV_VSSRA } enum vvcmpfunct6 = { VVCMP_VMSEQ, VVCMP_VMSNE, VVCMP_VMSLTU, VVCMP_VMSLT, VVCMP_VMSLEU, VVCMP_VMSLE } @@ -70,7 +70,7 @@ enum vimcfunct6 = { VIMC_VMADC } enum vimsfunct6 = { VIMS_VADC } -enum vxcmpfunct6 = { VXCMP_VMSEQ, VXCMP_VMSNE, VXCMP_VMSLTU, VXCMP_VMSLT, VXCMP_VMSLEU, VXCMP_VMSLE, +enum vxcmpfunct6 = { VXCMP_VMSEQ, VXCMP_VMSNE, VXCMP_VMSLTU, VXCMP_VMSLT, VXCMP_VMSLEU, VXCMP_VMSLE, VXCMP_VMSGTU, VXCMP_VMSGT } enum vicmpfunct6 = { VICMP_VMSEQ, VICMP_VMSNE, VICMP_VMSLEU, VICMP_VMSLE, VICMP_VMSGTU, VICMP_VMSGT } @@ -103,33 +103,33 @@ enum vext4funct6 = { VEXT4_ZVF4, VEXT4_SVF4 } enum vext8funct6 = { VEXT8_ZVF8, VEXT8_SVF8 } -enum vxfunct6 = { VX_VADD, VX_VSUB, VX_VRSUB, VX_VMINU, VX_VMIN, VX_VMAXU, VX_VMAX, +enum vxfunct6 = { VX_VADD, VX_VSUB, VX_VRSUB, VX_VMINU, VX_VMIN, VX_VMAXU, VX_VMAX, VX_VAND, VX_VOR, VX_VXOR, VX_VSADDU, VX_VSADD, VX_VSSUBU, VX_VSSUB, VX_VSLL, VX_VSMUL, VX_VSRL, VX_VSRA, VX_VSSRL, VX_VSSRA } -enum vifunct6 = { VI_VADD, VI_VRSUB, VI_VAND, VI_VOR, VI_VXOR, VI_VSADDU, VI_VSADD, +enum vifunct6 = { VI_VADD, VI_VRSUB, VI_VAND, VI_VOR, VI_VXOR, VI_VSADDU, VI_VSADD, VI_VSLL, VI_VSRL, VI_VSRA, VI_VSSRL, VI_VSSRA } enum vxsgfunct6 = { VX_VSLIDEUP, VX_VSLIDEDOWN, VX_VRGATHER } enum visgfunct6 = { VI_VSLIDEUP, VI_VSLIDEDOWN, VI_VRGATHER } -enum mvvfunct6 = { MVV_VAADDU, MVV_VAADD, MVV_VASUBU, MVV_VASUB, MVV_VMUL, MVV_VMULH, +enum mvvfunct6 = { MVV_VAADDU, MVV_VAADD, MVV_VASUBU, MVV_VASUB, MVV_VMUL, MVV_VMULH, MVV_VMULHU, MVV_VMULHSU, MVV_VDIVU, MVV_VDIV, MVV_VREMU, MVV_VREM } enum mvvmafunct6 = { MVV_VMACC, MVV_VNMSAC, MVV_VMADD, MVV_VNMSUB } -enum rmvvfunct6 = { MVV_VREDSUM, MVV_VREDAND, MVV_VREDOR, MVV_VREDXOR, +enum rmvvfunct6 = { MVV_VREDSUM, MVV_VREDAND, MVV_VREDOR, MVV_VREDXOR, MVV_VREDMINU, MVV_VREDMIN, MVV_VREDMAXU, MVV_VREDMAX } enum rivvfunct6 = { IVV_VWREDSUMU, IVV_VWREDSUM } -enum rfvvfunct6 = { FVV_VFREDOSUM, FVV_VFREDUSUM, FVV_VFREDMAX, FVV_VFREDMIN, +enum rfvvfunct6 = { FVV_VFREDOSUM, FVV_VFREDUSUM, FVV_VFREDMAX, FVV_VFREDMIN, FVV_VFWREDOSUM, FVV_VFWREDUSUM } enum wmvvfunct6 = { WMVV_VWMACCU, WMVV_VWMACC, WMVV_VWMACCSU } -enum mvxfunct6 = { MVX_VAADDU, MVX_VAADD, MVX_VASUBU, MVX_VASUB, MVX_VSLIDE1UP, MVX_VSLIDE1DOWN, +enum mvxfunct6 = { MVX_VAADDU, MVX_VAADD, MVX_VASUBU, MVX_VASUB, MVX_VSLIDE1UP, MVX_VSLIDE1DOWN, MVX_VMUL, MVX_VMULH, MVX_VMULHU, MVX_VMULHSU, MVX_VDIVU, MVX_VDIV, MVX_VREMU, MVX_VREM } enum mvxmafunct6 = { MVX_VMACC, MVX_VNMSAC, MVX_VMADD, MVX_VNMSUB } @@ -140,7 +140,7 @@ enum maskfunct3 = { VV_VMERGE, VI_VMERGE, VX_VMERGE } enum vlewidth = { VLE8, VLE16, VLE32, VLE64 } -enum fvvfunct6 = { FVV_VADD, FVV_VSUB, FVV_VMIN, FVV_VMAX, FVV_VSGNJ, FVV_VSGNJN, FVV_VSGNJX, +enum fvvfunct6 = { FVV_VADD, FVV_VSUB, FVV_VMIN, FVV_VMAX, FVV_VSGNJ, FVV_VSGNJN, FVV_VSGNJX, FVV_VDIV, FVV_VMUL } enum fvvmafunct6 = { FVV_VMADD, FVV_VNMADD, FVV_VMSUB, FVV_VNMSUB, FVV_VMACC, FVV_VNMACC, FVV_VMSAC, FVV_VNMSAC } @@ -155,15 +155,15 @@ enum fvvmfunct6 = { FVVM_VMFEQ, FVVM_VMFLE, FVVM_VMFLT, FVVM_VMFNE } enum vfunary0 = { FV_CVT_XU_F, FV_CVT_X_F, FV_CVT_F_XU, FV_CVT_F_X, FV_CVT_RTZ_XU_F, FV_CVT_RTZ_X_F } -enum vfwunary0 = { FWV_CVT_XU_F, FWV_CVT_X_F, FWV_CVT_F_XU, FWV_CVT_F_X, FWV_CVT_F_F, +enum vfwunary0 = { FWV_CVT_XU_F, FWV_CVT_X_F, FWV_CVT_F_XU, FWV_CVT_F_X, FWV_CVT_F_F, FWV_CVT_RTZ_XU_F, FWV_CVT_RTZ_X_F } -enum vfnunary0 = { FNV_CVT_XU_F, FNV_CVT_X_F, FNV_CVT_F_XU, FNV_CVT_F_X, FNV_CVT_F_F, +enum vfnunary0 = { FNV_CVT_XU_F, FNV_CVT_X_F, FNV_CVT_F_XU, FNV_CVT_F_X, FNV_CVT_F_F, FNV_CVT_ROD_F_F, FNV_CVT_RTZ_XU_F, FNV_CVT_RTZ_X_F} enum vfunary1 = { FVV_VSQRT, FVV_VRSQRT7, FVV_VREC7, FVV_VCLASS } -enum fvffunct6 = { VF_VADD, VF_VSUB, VF_VMIN, VF_VMAX, VF_VSGNJ, VF_VSGNJN, VF_VSGNJX, +enum fvffunct6 = { VF_VADD, VF_VSUB, VF_VMIN, VF_VMAX, VF_VSGNJ, VF_VSGNJN, VF_VSGNJX, VF_VDIV, VF_VRDIV, VF_VMUL, VF_VRSUB, VF_VSLIDE1UP, VF_VSLIDE1DOWN } enum fvfmafunct6 = { VF_VMADD, VF_VNMADD, VF_VMSUB, VF_VNMSUB, VF_VMACC, VF_VNMACC, VF_VMSAC, VF_VNMSAC } diff --git a/ocaml_emulator/softfloat.ml b/ocaml_emulator/softfloat.ml index 314e0dc18..f85056d3b 100644 --- a/ocaml_emulator/softfloat.ml +++ b/ocaml_emulator/softfloat.ml @@ -53,45 +53,6 @@ let f32_sqrt rm v = let f64_sqrt rm v = () -let f16_rsqrte7 rm v = - () - -let f32_rsqrte7 rm v = - () - -let f64_rsqrte7 rm v = - () - -let f16_recip7 rm v = - () - -let f32_recip7 rm v = - () - -let f64_recip7 rm v = - () - -let f16_class v = - () - -let f32_class v = - () - -let f64_class v = - () - -let f16_to_i8 rm v = - () - -let f16_to_ui8 rm v = - () - -let f16_to_i16 rm v = - () - -let f16_to_ui16 rm v = - () - let f16_to_i32 rm v = () @@ -116,12 +77,6 @@ let i64_to_f16 rm v = let ui64_to_f16 rm v = () -let f32_to_i16 rm v = - () - -let f32_to_ui16 rm v = - () - let f32_to_i32 rm v = ()