diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
index 8d3eaaf98..d47ce8d12 100644
--- a/model/riscv_csr_map.sail
+++ b/model/riscv_csr_map.sail
@@ -133,6 +133,7 @@ mapping clause csr_name_map = 0x343  <-> "mtval"
 mapping clause csr_name_map = 0x344  <-> "mip"
 /* machine protection and translation */
 mapping clause csr_name_map = 0x747  <-> "mseccfg"
+mapping clause csr_name_map = 0x757  <-> "mseccfgh"
 mapping clause csr_name_map = 0x3A0  <-> "pmpcfg0"
 mapping clause csr_name_map = 0x3A1  <-> "pmpcfg1"
 mapping clause csr_name_map = 0x3A2  <-> "pmpcfg2"
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 564091ace..cec2e2c0b 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -106,6 +106,7 @@ function readCSR csr : csreg -> xlenbits = {
     (0x344,  _) => mip.bits(),
 
     (0x747,  _) => mseccfg.bits(),             // mseccfg
+    (0x757, 32) => mseccfgh,                   // mseccfgh
 
     (0x3A0,  _) => pmpReadCfgReg(0),           // pmpcfg0
     (0x3A1, 32) => pmpReadCfgReg(1),           // pmpcfg1
@@ -196,6 +197,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
 
     // Note: Some(value) returned below is not the legalized value due to locked entries
     (0x747,  _) => { mseccfg->bits() = mseccfgWrite(mseccfg.bits(), value); Some(mseccfg.bits()) },
+    (0x757, 32) => { Some(mseccfgh) }, // ignore writes for now
     (0x3A0,  _) => { pmpWriteCfgReg(0, value); Some(pmpReadCfgReg(0)) },  // pmpcfg0
     (0x3A1, 32) => { pmpWriteCfgReg(1, value); Some(pmpReadCfgReg(1)) },  // pmpcfg1
     (0x3A2,  _) => { pmpWriteCfgReg(2, value); Some(pmpReadCfgReg(2)) },  // pmpcfg2
diff --git a/model/riscv_pmp_control.sail b/model/riscv_pmp_control.sail
index 76ecf4371..6aa05f2df 100644
--- a/model/riscv_pmp_control.sail
+++ b/model/riscv_pmp_control.sail
@@ -275,6 +275,7 @@ function init_pmp() -> unit = {
   mseccfg->RLB() = 0b0;
   mseccfg->MML() = 0b0;
   mseccfg->MMWP() = 0b0;
+  mseccfgh = EXTZ(0b0);
   pmp0cfg  = update_A(pmp0cfg,  pmpAddrMatchType_to_bits(OFF));
   pmp1cfg  = update_A(pmp1cfg,  pmpAddrMatchType_to_bits(OFF));
   pmp2cfg  = update_A(pmp2cfg,  pmpAddrMatchType_to_bits(OFF));
diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail
index 10e9b62ef..83cbac0ab 100644
--- a/model/riscv_pmp_regs.sail
+++ b/model/riscv_pmp_regs.sail
@@ -107,6 +107,7 @@ bitfield Mseccfg_ent : xlenbits = {
 }
 
 register mseccfg  : Mseccfg_ent
+register mseccfgh  : bits(32)
 
 register pmp0cfg  : Pmpcfg_ent
 register pmp1cfg  : Pmpcfg_ent
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index f9924baec..5e118ef4b 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -99,7 +99,8 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     0x344 => p == Machine, // mip
 
     0x747 => p == Machine, // mseccfg
-    
+    0x757 => p == Machine & (sizeof(xlen) == 32), // mseccfgh
+
     0x3A0 => p == Machine,                        // pmpcfg0
     0x3A1 => p == Machine & (sizeof(xlen) == 32), // pmpcfg1
     0x3A2 => p == Machine,                        // pmpcfg2