Update Zc* extension file names

riscv · Jul 28, 2024 · 9a9e8c7 · 9a9e8c7
1 parent 1f2b8b8
commit 9a9e8c7
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Showing 4 changed files with 6 additions and 16 deletions.
diff --git a/Makefile b/Makefile
@@ -23,9 +23,9 @@ SAIL_VLEN := riscv_vlen.sail
 
 # Instruction sources, depending on target
 SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
-SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
-SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail
-SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail
+SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
+SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
+SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail
 
 SAIL_DEFAULT_INST += riscv_insts_svinval.sail
 

diff --git a/model/riscv_insts_cext.sail → model/riscv_insts_zca.sail b/model/riscv_insts_cext.sail → model/riscv_insts_zca.sail
@@ -7,11 +7,10 @@
 /*=======================================================================================*/
 
 /* ********************************************************************* */
-/* This file specifies the compressed instructions in the 'C' extension. */
+/* This file specifies the compressed instructions in the 'Zca' extension. */
 
-/* These instructions are only legal if misa[C] is true. Instead of
- * checking this in every execute clause, we currently do the check in one place
- * in the fetch-execute logic.
+/* Instead of checking for Zca in every execute clause, we currently do
+ * the check in one place in the fetch-execute logic.
  */
 
 /* ****************************************************************** */

diff --git a/model/riscv_insts_cdext.sail → model/riscv_insts_zcd.sail b/model/riscv_insts_cdext.sail → model/riscv_insts_zcd.sail
@@ -6,15 +6,6 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 /*=======================================================================================*/
 
-/* ********************************************************************* */
-/* This file specifies the compressed floating-point instructions.
- *
- * These instructions are only legal if misa[C] and misa[D]
- * are set.
- */
-
-/* ****************************************************************** */
-
 enum clause extension = Ext_Zcd
 function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (sizeof(xlen) == 32 | sizeof(xlen) == 64)
 

diff --git a/model/riscv_insts_cfext.sail → model/riscv_insts_zcf.sail b/model/riscv_insts_cfext.sail → model/riscv_insts_zcf.sail