diff --git a/model/riscv_vmem_sv32.sail b/model/riscv_vmem_sv32.sail
index e0f5bc985..e8365c323 100644
--- a/model/riscv_vmem_sv32.sail
+++ b/model/riscv_vmem_sv32.sail
@@ -237,7 +237,7 @@ function translate32(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) =
                 /* pte needs dirty/accessed update but that is not enabled */
                 TR_Failure(PTW_PTE_Update(), ext_ptw)
               } else {
-                w_pte : SV32_PTE = update_BITS(pte, pbits.bits());
+                var w_pte : SV32_PTE = update_BITS(pte, pbits.bits());
                 /* ext is unused since there are no reserved bits for extensions */
                 match mem_write_value_priv(to_phys_addr(pteAddr), 4, w_pte.bits(), Supervisor, false, false, false) {
                   MemValue(_) => {
diff --git a/model/riscv_vmem_sv39.sail b/model/riscv_vmem_sv39.sail
index 5bc5a187e..384b6ece3 100644
--- a/model/riscv_vmem_sv39.sail
+++ b/model/riscv_vmem_sv39.sail
@@ -231,8 +231,8 @@ function translate39(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) =
                 /* pte needs dirty/accessed update but that is not enabled */
                 TR_Failure(PTW_PTE_Update(), ext_ptw)
               } else {
-                w_pte : SV39_PTE = update_BITS(pte, pbits.bits());
-                w_pte : SV39_PTE = update_Ext(w_pte, ext);
+                var w_pte : SV39_PTE = update_BITS(pte, pbits.bits());
+                w_pte = update_Ext(w_pte, ext);
                 match mem_write_value_priv(zero_extend(pteAddr), 8, w_pte.bits(), Supervisor, false, false, false) {
                   MemValue(_) => {
                     add_to_TLB39(asid, vAddr, pAddr, w_pte, pteAddr, level, global);
diff --git a/model/riscv_vmem_sv48.sail b/model/riscv_vmem_sv48.sail
index 26a8a3b6a..729a70177 100644
--- a/model/riscv_vmem_sv48.sail
+++ b/model/riscv_vmem_sv48.sail
@@ -195,8 +195,8 @@ function translate48(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) =
             /* pte needs dirty/accessed update but that is not enabled */
             TR_Failure(PTW_PTE_Update(), ext_ptw)
           } else {
-            w_pte : SV48_PTE = update_BITS(pte, pbits.bits());
-            w_pte : SV48_PTE = update_Ext(w_pte, ext);
+            var w_pte : SV48_PTE = update_BITS(pte, pbits.bits());
+            w_pte = update_Ext(w_pte, ext);
             match mem_write_value_priv(zero_extend(pteAddr), 8, w_pte.bits(), Supervisor, false, false, false) {
               MemValue(_) => {
                 add_to_TLB48(asid, vAddr, pAddr, w_pte, pteAddr, level, global);