From b4a6db0a02611bea3b9c905111ff319643a90576 Mon Sep 17 00:00:00 2001
From: Jordan Carlin <jordanmcarlin@gmail.com>
Date: Sun, 28 Jul 2024 16:50:12 -0700
Subject: [PATCH] Update Zc* extension file names

---
 Makefile                                               | 6 +++---
 model/{riscv_insts_cext.sail => riscv_insts_zca.sail}  | 7 +++----
 model/{riscv_insts_cdext.sail => riscv_insts_zcd.sail} | 9 ---------
 model/{riscv_insts_cfext.sail => riscv_insts_zcf.sail} | 0
 4 files changed, 6 insertions(+), 16 deletions(-)
 rename model/{riscv_insts_cext.sail => riscv_insts_zca.sail} (98%)
 rename model/{riscv_insts_cdext.sail => riscv_insts_zcd.sail} (92%)
 rename model/{riscv_insts_cfext.sail => riscv_insts_zcf.sail} (100%)

diff --git a/Makefile b/Makefile
index 268e36b9b..e26ee2901 100644
--- a/Makefile
+++ b/Makefile
@@ -23,9 +23,9 @@ SAIL_VLEN := riscv_vlen.sail
 
 # Instruction sources, depending on target
 SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_misa_ext.sail
-SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_cext.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
-SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_cfext.sail
-SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_cdext.sail
+SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_next.sail riscv_insts_hints.sail
+SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
+SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail
 
 SAIL_DEFAULT_INST += riscv_insts_svinval.sail
 
diff --git a/model/riscv_insts_cext.sail b/model/riscv_insts_zca.sail
similarity index 98%
rename from model/riscv_insts_cext.sail
rename to model/riscv_insts_zca.sail
index 14b783aee..5cc4f26df 100644
--- a/model/riscv_insts_cext.sail
+++ b/model/riscv_insts_zca.sail
@@ -7,11 +7,10 @@
 /*=======================================================================================*/
 
 /* ********************************************************************* */
-/* This file specifies the compressed instructions in the 'C' extension. */
+/* This file specifies the compressed instructions in the 'Zca' extension. */
 
-/* These instructions are only legal if misa[C] is true.  Instead of
- * checking this in every execute clause, we currently do the check in one place
- * in the fetch-execute logic.
+/* Instead of checking for Zca in every execute clause, we currently do
+ * the check in one place in the fetch-execute logic.
  */
 
 /* ****************************************************************** */
diff --git a/model/riscv_insts_cdext.sail b/model/riscv_insts_zcd.sail
similarity index 92%
rename from model/riscv_insts_cdext.sail
rename to model/riscv_insts_zcd.sail
index 52017ac3b..fc608a41e 100644
--- a/model/riscv_insts_cdext.sail
+++ b/model/riscv_insts_zcd.sail
@@ -6,15 +6,6 @@
 /*  SPDX-License-Identifier: BSD-2-Clause                                                */
 /*=======================================================================================*/
 
-/* ********************************************************************* */
-/* This file specifies the compressed floating-point instructions.
- *
- * These instructions are only legal if misa[C] and misa[D]
- * are set.
- */
-
-/* ****************************************************************** */
-
 enum clause extension = Ext_Zcd
 function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (sizeof(xlen) == 32 | sizeof(xlen) == 64)
 
diff --git a/model/riscv_insts_cfext.sail b/model/riscv_insts_zcf.sail
similarity index 100%
rename from model/riscv_insts_cfext.sail
rename to model/riscv_insts_zcf.sail