From bbac05724a01ac366a5ef0ff76b2e6828bca01aa Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Sun, 26 Nov 2023 16:00:44 -0600
Subject: [PATCH] add blanks

---
 model/riscv_sys_regs.sail | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 0fc1bfad1..4eadfc37a 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -634,6 +634,7 @@ bitfield Sstatus : xlenbits = {
   SIE  : 1,
   UIE  : 0
 }
+
 /* sstatus is a view of mstatus, so there is no register defined. */
 function get_sstatus_UXL(s : Sstatus) -> arch_xlen = {
   let m = Mk_Mstatus(s.bits());
@@ -645,6 +646,7 @@ function set_sstatus_UXL(s : Sstatus, a : arch_xlen) -> Sstatus = {
   let m = set_mstatus_UXL(m, a);
   Mk_Sstatus(m.bits())
 }
+
 function lower_mstatus(m : Mstatus) -> Sstatus = {
   let s = Mk_Sstatus(zero_extend(0b0));
   let s = update_SD(s, m.SD());