Add unratified B extension

riscv · Feb 7, 2024 · bc35e3a · bc35e3a
1 parent 4de2bff
commit bc35e3a
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 0 deletions.
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
@@ -543,6 +543,7 @@ function init_sys() -> unit = {
  misa[MXL] = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
  misa[A] = 0b1; /* atomics */
  misa[C] = bool_to_bits(sys_enable_rvc()); /* RVC */
+ misa[B] = 0b1; /* Bit-manipulation */
  misa[I] = 0b1; /* base integer ISA */
  misa[M] = 0b1; /* integer multiply/divide */
  misa[U] = 0b1; /* user-mode */

diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
@@ -187,6 +187,7 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = {
 /* we currently don't model 'E', so always assume 'I'. */
 function haveAtomics() -> bool = misa[A] == 0b1
 function haveRVC() -> bool = misa[C] == 0b1
+function haveBExt() -> bool = misa[B] == 0b1
 function haveMulDiv() -> bool = misa[M] == 0b1
 function haveSupMode() -> bool = misa[S] == 0b1
 function haveUsrMode() -> bool = misa[U] == 0b1