From ed3497b122ffd416722b05e2179840c54b7ddc63 Mon Sep 17 00:00:00 2001
From: William McSpaddden <bill@riscv.org>
Date: Wed, 1 May 2024 20:41:36 -0500
Subject: [PATCH] intermediate checkin

---
 .github/workflows/compile.yml | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml
index 11eb1aee7..084072a2b 100644
--- a/.github/workflows/compile.yml
+++ b/.github/workflows/compile.yml
@@ -29,25 +29,31 @@ jobs:
     - name: Build RISC-V testsuite
       run: |
         cd TEST_DIR_ROOT/riscv_tests.git ; \
+        git checkout riscv-tests-sail ; \
         echo ${PWD} ; ls ; \
         autoconf ;  \
         ./configure --prefix=${PWD}/target ; \
-        make -v ; \
-        which gmake ; \
         export PATH=/opt/riscv/bin:${PATH} ; \
-        echo "PATH: ${PATH}" ; \
-        ls -l /opt/riscv/bin ; \
-        riscv32-unknown-elf-gcc -march=rv32g_zbb -c -x c /dev/null ; \
-        echo "return code: $?" ; \
         make isa ;
     - name: Build and test simulators
       run: eval $(opam env) && test/run_tests.sh
+    - name: Build and test simulators (new method)
+      run: |
+        eval $(opam env) ; \
+        cd TEST_DIR_ROOT/riscv_tests.git ; \
+        ../../bin/run_tests.py --outfile=tests_new.xml --32bit=yes --64bit=yes --c_sim=yes --ocaml_sim=no --sailcov=no --clean_build=yes --test_switch_pyfile=test_command_line_switch.py --test_ignore_pyfile=test_ignore_list.py
     - name: Upload test results
       if: always()
       uses: actions/upload-artifact@v4
       with:
         name: tests.xml
         path: test/tests.xml
+    - name: Upload test results (new)
+      if: always()
+      uses: actions/upload-artifact@v4
+      with:
+        name: tests_new.xml
+        path: TEST_DIR_ROOT/riscv_test.git/tests_new.xml
     - name: Upload event payload
       if: always()
       uses: actions/upload-artifact@v4