From f00d548529b7f1893f1c6b998fae03ec952c8a98 Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Fri, 29 Dec 2023 11:33:37 -0600
Subject: [PATCH] add srmcfg CSR introduced by Ssqosid

---
 model/riscv_csr_map.sail     |  2 ++
 model/riscv_insts_zicsr.sail |  2 ++
 model/riscv_sys_control.sail |  7 +++++++
 model/riscv_sys_regs.sail    | 15 +++++++++++++++
 4 files changed, 26 insertions(+)

diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
index 5850ef48b..1d6f1042d 100644
--- a/model/riscv_csr_map.sail
+++ b/model/riscv_csr_map.sail
@@ -173,6 +173,8 @@ mapping clause csr_name_map = 0x00F  <-> "vcsr"
 mapping clause csr_name_map = 0xC20  <-> "vl"
 mapping clause csr_name_map = 0xC21  <-> "vtype"
 mapping clause csr_name_map = 0xC22  <-> "vlenb"
+/* Sqosid csrs */
+mapping clause csr_name_map = 0x181  <-> "srmcfg"
 /* Smstateen csrs */
 mapping clause csr_name_map = 0x30C  <-> "mstateen0"
 mapping clause csr_name_map = 0x31C  <-> "mstateen0h"
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index b3716a149..b25f54831 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -165,6 +165,7 @@ function readCSR csr : csreg -> xlenbits = {
     (0x143,  _) => stval,
     (0x144,  _) => lower_mip(mip, mideleg).bits(),
     (0x180,  _) => satp,
+    (0x181,  _) => srmcfg.bits(),
 
     /* user mode counters */
     (0xC00,  _) => mcycle[(sizeof(xlen) - 1) .. 0],
@@ -261,6 +262,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = {
     (0x143,  _) => { stval = value; Some(stval) },
     (0x144,  _) => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits()) },
     (0x180,  _) => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },
+    (0x181,  _) => { srmcfg = legalize_srmcfg(srmcfg, value); Some(srmcfg.bits()) },
 
     /* user mode: seed (entropy source). writes are ignored */
     (0x015,  _) => write_seed_csr(),
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 523961e64..604f6c427 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -155,6 +155,11 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     /* supervisor mode: address translation */
     0x180 => haveSupMode() & (p == Machine | p == Supervisor), // satp
 
+    /* supervisor mode: resource management configurations */
+    0x181 => haveSsqosid() & ((p == Machine) |
+                              ((p == Supervisor) & haveSmstateen() & (mstateen0.PRIV114() == 0b1)) |
+                              ((p == Supervisor) & not(haveSmstateen()))), // srmcfg
+
     /* user mode: counters */
     0xC00 => haveUsrMode(),    // cycle
     0xC01 => haveUsrMode(),    // time
@@ -627,6 +632,8 @@ function init_sys() -> unit = {
 
   init_pmp();
 
+  srmcfg->RCID()     = 0b000000000000;
+
   // log compatibility with spike
   if   get_config_print_reg()
   then print_reg("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(zero_extend(0b0) : xlenbits) ^ ")")
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 0b1299801..c5f90ee4b 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -891,6 +891,7 @@ function is_fiom_active() -> bool = {
 
 bitfield Mstateen0 : bits(64) = {
   // controls to new state introduced by the following small extensions of Priv-1.14-era:
+  // - CSR srmcfg introduced by Ssqosid extension
   PRIV114  : 55
 }
 register mstateen0 : Mstateen0
@@ -988,3 +989,17 @@ function get_vtype_vma() = decode_agtype(vtype.vma())
 
 val get_vtype_vta : unit -> agtype
 function get_vtype_vta() = decode_agtype(vtype.vta())
+
+/* srmcfg CSR introduced by Ssqosid */
+bitfield Srmcfg : xlenbits = {
+  MCID : 27 .. 16,
+  RCID : 11 .. 0
+}
+
+register srmcfg : Srmcfg
+
+function legalize_srmcfg(s : Srmcfg, v : xlenbits) -> Srmcfg = {
+  let s = update_MCID(s, v[27 .. 16]);
+  let s = update_RCID(s, v[11 .. 0]);
+  s
+}