From fbb7edcab3277a746182971b15be1731fb83f797 Mon Sep 17 00:00:00 2001
From: Dan Smathers <dan.smathers@seagate.com>
Date: Wed, 16 Aug 2023 17:30:48 -0600
Subject: [PATCH] adding read-only csr mconfigptr

mconfigptr is used by the unified discovery task group  https://github.com/riscv/configuration-structure
---
 model/riscv_csr_map.sail     | 1 +
 model/riscv_insts_zicsr.sail | 1 +
 model/riscv_sys_control.sail | 2 ++
 model/riscv_sys_regs.sail    | 1 +
 4 files changed, 5 insertions(+)

diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail
index e3f8f5bb8..d2bf86005 100644
--- a/model/riscv_csr_map.sail
+++ b/model/riscv_csr_map.sail
@@ -118,6 +118,7 @@ mapping clause csr_name_map = 0xF11  <-> "mvendorid"
 mapping clause csr_name_map = 0xF12  <-> "marchid"
 mapping clause csr_name_map = 0xF13  <-> "mimpid"
 mapping clause csr_name_map = 0xF14  <-> "mhartid"
+mapping clause csr_name_map = 0xF15  <-> "mconfigptr"
 /* machine trap setup */
 mapping clause csr_name_map = 0x300  <-> "mstatus"
 mapping clause csr_name_map = 0x301  <-> "misa"
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index f6e767265..e66a0ae8e 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -91,6 +91,7 @@ function readCSR csr : csreg -> xlenbits = {
     (0xF12,  _) => marchid,
     (0xF13,  _) => mimpid,
     (0xF14,  _) => mhartid,
+    (0xF15,  _) => mconfigptr,
     (0x300,  _) => mstatus.bits(),
     (0x301,  _) => misa.bits(),
     (0x302,  _) => medeleg.bits(),
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index d057ad6c0..32ecd6191 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -83,6 +83,7 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool =
     0xf12 => p == Machine, // marchdid
     0xf13 => p == Machine, // mimpid
     0xf14 => p == Machine, // mhartid
+    0xf15 => p == Machine, // mconfigptr
     /* machine mode: trap setup */
     0x300 => p == Machine, // mstatus
     0x301 => p == Machine, // misa
@@ -552,6 +553,7 @@ function init_sys() -> unit = {
   cur_privilege = Machine;
 
   mhartid     = zero_extend(0b0);
+  mconfigptr  = zero_extend(0b0);
 
   misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
   misa->A()   = 0b1;                            /* atomics */
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index fedb02e9e..b2e2336a3 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -579,6 +579,7 @@ register mimpid : xlenbits
 register marchid : xlenbits
 /* TODO: this should be readonly, and always 0 for now */
 register mhartid : xlenbits
+register mconfigptr : xlenbits
 
 /* S-mode registers */