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Add support for the Zvkb extension #236

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Add support for the Zvkb extension #236

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Implements the Zvkb (Vector Bit-manipulation used in Cryptography) extension, as of version Draft: 20230303

The following instructions are included:

  • vclmul.[vv,vx]
  • vclmulh.[vv,vx]
  • vrol.[vv,vx]
  • vror.[vv,vx,vi]
  • vbrev8.v
  • vrev8.v
  • vandn.[vv,vx]

All instructions were tested with VLEN & ELEN being manually adjusted; results were compared with QEMU results of each instruction.

Current revision is rebased with the latest changes of vector-dev branch.

XinlaiWan and others added 3 commits March 22, 2023 09:01
@XinlaiWan @nibrunie
@jrtc27 @rpsene
V extension general framework and configuration setting instructions (r…
32b1b8f 
…iscv#191)

* V extension general framework and configuration setting instructions

* Update model/riscv_insts_vext_utils.sail

fix a typo

Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Signed-off-by: BrighterW <xinlai.w@rioslab.org>

* Update model/riscv_insts_vext_vset.sail

* Revisions after Nov 22 meeting

* Update effect matching for functions in riscv_vlen.sail

* Fix code formatting issues

* Update model/riscv_insts_vext_utils.sail

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>

* Fix coding style issues

* Update vset instructions

Signed-off-by: BrighterW <xinlai.w@rioslab.org>
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>
Co-authored-by: Nicolas Brunie <nibrunie@gmail.com>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
@XinlaiWan @rpsene
Vector load / store instructions (riscv#198)
c673d33 
* Add vector load / store instructions

* Modify the implementation of SEW, LMUL, VLEN and avoid real numbers in the code

* Update vstart setting in vector load / store instructions

* Remove unnecessary assert statements in vector instructions

* Fix bugs in vleff instructions and revise coding styles

* Add guards for vector encdec clauses, Avoid redundant memory access after vector load/store failure
@XinlaiWan @rpsene
Vector integer/fixed-point arithmetic & mask instructions (riscv#227)
5a0ae4f 
* Add vector arithmetic & mask instructions

* Update vector EEW and EMUL checking function

* Add vector instruction illegal check functions

* Adjust code formatting for vector instruction illegal check functions

Merge approved by team at tech-golden-model meeting on 2023-03-14.
@charmitro charmitro changed the base branch from master to vector-dev March 27, 2023 08:55
@charmitro charmitro mentioned this pull request Mar 27, 2023
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Updated the PR:

  • Correction on iterating based on the specification
  • Correctly Load & Store from/to vector registers

@XinlaiWan
Vector floating-point instructions (riscv#232)
c5ab726 
* Add vector floating-point instructions

* Update vector floating-point conversion instructions

* Update copyright headers for vector extension code

---------

Co-authored-by: xwan <xinlai.wan@rivai.ai>
@charmitro
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Rebased from vector-dev branch.

@charmitro
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Updated the patchset:

  • Make sure we are running in sizeof(xlen) == 64bit

@nibrunieAtSi5
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nibrunieAtSi5 commented May 25, 2023 •
edited
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Since this extension was later split into Zvbb + Zvbc and extended with new instructions, is the plan to review / merge it as it is and then update the SAIL with a new PR or to update that PR ?

XinlaiWan and others added 11 commits June 12, 2023 14:28
@XinlaiWan
Vector reduction and mask instructions (riscv#259)
3a3b1c0 
* Add vector mask and reduction instructions

* Fix register overlap check in vector mask instructions

---------

Co-authored-by: xwan <xinlai.wan@rivai.ai>
@XinlaiWan @billmcspadden-riscv
update vector CSR vtype.vill setting and judgement
15364c0
@XinlaiWan @billmcspadden-riscv
Summarize patterns of vector illegal instruction check
5872908
Zvkb: add infrastructure for Zvkb
a9f0141 
To support the implementation of Zvkb extensions in SAIL, this
creates the necessary infrastructure(i.e., a file to hold it, and the
extension macro), preparing the tree for the Zvkb implementation.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vrol.[vv,vx]" instruction
86d63d6 
Vector rotate left by vector(.vv) or scalar(.vx).

The elements in vs2 are rotated left by the rotate amount
specified by either the cotrresponding elements of vs1 (vector-vector),
or integer register rs1 (vector-scalar). Only the low log2(SEW) bits
of the rotate-amount value are used, all other bits are ignored

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vror.[vv,vx,vi]" instructions
15f0c1f 
Vector rotate right by vector/scalar/immediate.

The elements in vs2 are rotated right by the rotate amount
specified by either the corresponding elements of vs1 (vector-vector),
integer register rs1 (vector-scalar), or an immediate value
(vector-immediate). Only the low log2(SEW) bits of the rotate-amount
value are used, all other bits are ignored.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vbrev8.v" instruction
f4a5aec 
Vector Reverse Bits in Bytes, a bit reversal is
performed on the bits of each byte.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vrev8.v" instrcuction
d0ea7f0 
Vector Reverse Bytes

A byte reversal is performed on each element of vs2, effectively
performing an endian swap.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vandn.[vv,vx]" instructions
d40d62b 
Bitwise And-Not.

Each bit of Op1 is inverted and logically ANDed with the
corresponding bits in vs2. In the vector- scalar version,
"Op1" is the sign-extended or truncated value in scalar register
rs1. In the vector-vector version, Op1 is vs1.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vclmul.[vv,vx]" instructions
7bf0ebe 
Produces the low half of 128-bit carry-less product.

Each 64-bit element in the vs2 vector register is carry-less
multiplied by either each 64-bit element in vs1 (vector-vector), or
the 64-bit value from integer register rs1 (vector-scalar). The
result is the least significant 64 bits of the carry-less product.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
Zvkb: add "vclmulh.[vv,vx]" instructions
1b71422 
Vector Carry-less Multiply by vector or scalar - returning
high half of product.

Each 64-bit element in the vs2 vector register is carry-less
multiplied by either each 64-bit element in vs1 (vector-vector), or
the 64-bit value from integer register rs1 (vector-scalar). The
result is the most significant 64 bits of the carry-less product.

Signed-off-by: Charalampos Mitrodimas <charalampos.mitrodimas@vrull.eu>
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Unit Test Results

712 tests  ±0   712 ✔️ ±0   0s ⏱️ ±0s
    6 suites ±0       0 💤 ±0 
    1 files   ±0       0 ❌ ±0 

Results for commit 1b71422. ± Comparison against base commit 5872908.

@rez5427 rez5427 mentioned this pull request Sep 22, 2024
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3 participants
@charmitro @nibrunieAtSi5 @XinlaiWan