Vector extension code corrections

[XinlaiWan]

In this PR, there are some corrections of the V extension code after going through the spec once again and running ISA tests covering more configurations (rvv-atg). They are mostly about corner case illegal checks.

1. Use register index instead of register name string when reading mask register v0, as suggested in the last PR.
2. Update setting of CSR vtype.vill field in vset instructions and judgement of illegal vill when executing vector instructions.
3. Update the condition check of SEW <= ELEN * LMUL for vset instructions. Violations will set vill according to the spec.
4. Fix a bug in vnclip/vnclipu instructions when calculating shift width.

V extension has a huge number of instructions with subtle variations. It's prone to miss some corner cases or small details in both instruction semantic and coding style. Please comment if there are issues found in the code, and I'll fix them soon. After this PR is approved, I'll open the merging PR from vector-dev branch to the main branch.

[github-actions]

Unit Test Results

712 tests  ±0   712 ✔️ ±0   0s ⏱️ ±0s
    6 suites ±0       0 💤 ±0 
    1 files   ±0       0 ❌ ±0 

Results for commit 25d39ce. ± Comparison against base commit 3a3b1c0.

♻️ This comment has been updated with latest results.