From e9ee1983ffc03a074c459de2d6e6f8c74a01e7ca Mon Sep 17 00:00:00 2001 From: ahadali5000 Date: Tue, 26 Sep 2023 10:42:45 +0500 Subject: [PATCH] Per section 3.1.1 of the Privileged Spec (Machine ISA Register misa): F/D both should be disabled if F=0 --- model/riscv_sys_regs.sail | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 251df5a65..abdfc8300 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -164,10 +164,10 @@ function legalize_misa(m : Misa, v : xlenbits) -> Misa = { else { /* Suppress enabling C if C was disabled at boot (i.e. not supported) */ let m = if not(sys_enable_rvc()) then m else update_C(m, v.C()); - /* Handle updates for F/D. */ - if not(sys_enable_fdext()) | (v.D() == 0b1 & v.F() == 0b0) + /* Suppress updates to misa.{f,d} if disabled at boot */ + if not(sys_enable_fdext()) then m - else update_D(update_F(m, v.F()), v.D()) + else update_D(update_F(m, v.F()), v.D() & v.F()) } }