Add Svinval extension.

[martinberger]

These changes add the "Svinval" Standard Extension for Fine-Grained
Address-Translation Cache Invalidation, Version 1.0 to the sail-riscv model.

This extension defines five new instructions: SINVAL.VMA, SFENCE.W.INVAL,
SFENCE.INVAL.IR, HINVAL.VVMA, HINVAL.GVMA.

HINVAL.VVMA & HINVAL.GVMA are omitted since they build on the
Hypervisor Extension which is yet to be included in the model.

SFENCE.W.INVAL & SFENCE.INVAL.IR are treated as nops pending integration
of the coherency model (rmem) with sail.

The specification says that SINVAL.VMA behaves just as SFENCE.VMA,
except there are additional ordering constraints with respect to the new
SFENCE.W.INVAL & SFENCE.INVAL.IR instructions. Since these are nops, we
can treat SINVAL.VMA as if it were SFENCE.VMA.

[martinberger]

This is essentially the same PR as #297 from @kristinbarber but I've added the missing haveSvinval() gates in the encdec functions.

[martinberger]

One question is: should this be in a separate riscv_insts_svinval.sail file?

[github-actions]

Test Results

712 tests  ±0     0 ✅  - 712   0s ⏱️ ±0s
  6 suites ±0     0 💤 ±  0 
  1 files   ±0   712 ❌ +712 

For more details on these failures, see this check.

Results for commit ff98dcc. ± Comparison against base commit c5ee87d.