diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail
index 9c9e06a4f..6fd66917d 100644
--- a/model/riscv_fetch.sail
+++ b/model/riscv_fetch.sail
@@ -12,7 +12,6 @@
 
 function isRVC(h : half) -> bool = not(h[1 .. 0] == 0b11)
 
-val fetch : unit -> FetchResult
 function fetch() -> FetchResult =
   /* fetch PC check for extensions: extensions return a transformed PC to fetch,
    * but any exceptions use the untransformed PC.
diff --git a/model/riscv_step.sail b/model/riscv_step.sail
index 012f63b4d..649ddec4e 100644
--- a/model/riscv_step.sail
+++ b/model/riscv_step.sail
@@ -33,8 +33,7 @@ function step(step_no : int) -> bool = {
       },
       None() => {
         /* the extension hook interposes on the fetch result */
-        let f : FetchResult = ext_fetch_hook(fetch());
-        match f {
+        match ext_fetch_hook(fetch()) {
           /* extension error */
           F_Ext_Error(e)   => {
             ext_handle_fetch_check_error(e);
@@ -57,10 +56,10 @@ function step(step_no : int) -> bool = {
             if haveRVC() then {
               nextPC = PC + 2;
               (execute(ast), true)
-             } else {
+            } else {
               handle_illegal();
               (RETIRE_FAIL, true)
-             }
+            }
           },
           F_Base(w) => {
             instbits = zero_extend(w);