From c1cfdb2eb858344eede562964949a741fce33740 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Thu, 4 Jul 2024 19:13:08 +0800
Subject: [PATCH 1/3] Add svnapot extention support

---
 c_emulator/riscv_rvfi_RV64                 |    Bin 0 -> 13911144 bytes
 model/riscv_vmem.sail                      |     30 +
 test/riscv-tests/rv64ssvnapot-p-napot      |    Bin 0 -> 2098688 bytes
 test/riscv-tests/rv64ssvnapot-p-napot.dump | 524553 ++++++++++++++++++
 4 files changed, 524583 insertions(+)
 create mode 100755 c_emulator/riscv_rvfi_RV64
 create mode 100755 test/riscv-tests/rv64ssvnapot-p-napot
 create mode 100644 test/riscv-tests/rv64ssvnapot-p-napot.dump

diff --git a/c_emulator/riscv_rvfi_RV64 b/c_emulator/riscv_rvfi_RV64
new file mode 100755
index 0000000000000000000000000000000000000000..309f4e583c7176218377b2837729a250ee58d425
GIT binary patch
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A>Hq)$

literal 0
HcmV?d00001

diff --git a/model/riscv_vmem.sail b/model/riscv_vmem.sail
index 2bb96fe7a..4987d0b71 100644
--- a/model/riscv_vmem.sail
+++ b/model/riscv_vmem.sail
@@ -45,6 +45,15 @@ function vpn_j_of_va(sv_params : SV_Params,
   ((va >> lsb) & mask)
 }
 
+// PRIVATE: Count trailing zeros
+function LowestSetBit(x : bits(64)) -> bits(64) = {
+  var count : bits(64) = zeros();
+  let perfect_one : bits(64) = 0x0000_0000_0000_0001;
+  foreach (i from 0 to (sizeof(xlen) - 1) by 1 in inc)
+    if [x[i]] == 0b1 then return(count + perfect_one) else (count = count + perfect_one);
+  return count;
+}
+
 // PRIVATE: Extract offset within page from VA
 function offset_of_va(va : bits(64)) -> bits(PAGESIZE_BITS) = va[pagesize_bits - 1 .. 0]
 
@@ -164,7 +173,28 @@ function pt_walk(sv_params,
                 }
               }
               else {
+                let mask_bits = level * sv_params.pte_PPN_j_size_bits;
+                let mask : bits(64) = ~ (ones() << mask_bits);
+                let ppn : bits(64) = ppns | (vpns_of_va(sv_params, va) & mask);
+                let napot_bits  = LowestSetBit(ppn);
+                let perfect_one : bits(64) = 0x0000_0000_0000_0001;
+                let napot_mask : bits(64) = (perfect_one << napot_bits) - perfect_one;
+                let napot_mask_not : bits(64) = ~ (napot_mask);
+                let ptshift_level = sv_params.levels - 1;
+                let ptshift = ptshift_level * sv_params.vpn_size_bits;
+
+                let page_base = (ppn & napot_mask_not) | 
+                                (vpns_of_va(sv_params, va) & napot_mask) | 
+                                (vpns_of_va(sv_params, va) & ((perfect_one << ptshift) - perfect_one));
+
                 let pa = (ppns << pagesize_bits) | zero_extend(offset_of_va(va));
+                let pa_napot = page_base << 12 | zero_extend(offset_of_va(va));
+
+                // For svnapot ext purpose.
+                if (pte & (perfect_one << 63)) == (perfect_one << 63) then {
+                  return PTW_Success(pa_napot, pte, pte_addr, level, global', ext_ptw)
+                };
+
                 PTW_Success(pa, pte, pte_addr, level, global', ext_ptw)
               }
           }
diff --git a/test/riscv-tests/rv64ssvnapot-p-napot b/test/riscv-tests/rv64ssvnapot-p-napot
new file mode 100755
index 0000000000000000000000000000000000000000..71427e7289beb2d23199f9067793e22065eeff6f
GIT binary patch
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z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF
z5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk
z1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs
z0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZ
zfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&U
zAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C7
z2oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N
z0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+
z009C72oNAZfB*pk1PBlyK!5-N0t5&UAV7cs0RjXF5FkK+009C72oNAZfB*pk1PBly
zK!5-N0t5&UAV7cs0RsOg0$=`mJV>{lHLrxisaP#{uROchKEC$M^2+hG`f?-H&L3Yp
zzI-m-UTHV8Zpy#XKHpkxw&K88Us<_)>6x{9m@Dji?86?b6bh-kKRu=tiXl|?%9rBM
z${yoqrkBW9o(b;_r#l|c6A$nE{5b#O)Oo%&&c_}4d3Ag{JI*gn<vZj27pL<556EB7
z^Xa*2qak@agdcC`cR%k>^L!!vthoC;KOg5`D(%kS9p?{C<=-0T-=A9NmoZ-nrC4^K
z=Qrd0wEx?A{$bB|V!jqXh0jjyyY&I<-_P^Kur&VM=VCiu7h|dHcpoPD&}=^c?CH~;
z?=E!0XRdyPm$ci;TD|2ft!A&&4ZUt-ZBqYUx7}+k_c|9lSub2{te(5nT5er!w$^&>
z&T8oNF1ETm+AA+FpKJ6QVXbi?PHLRJ)C#MOwN7t2i|e++xppgdWm!1iXkQAg)pN^P
z`@(9YcRBW*ZCz-u?r6s;jczZj^x~nGM;mv;a-0*+cRMTjal%6O@=Dw##$I<6FHUN`
z*45rZd$rvQ3**Bt<R@FmztszkUa#9ed%4%ja^H`7dnzuFKK<DT3-$AAWt8ZrS9`~`
zw4<J?PsftxZx5S%?`ts`uhXNjeP7zHjVcQ<?3%y*_hEE^N_=~EU%T6ju`}+ywtGx^
z=W2QC%v49(Yv+~P@vqfG*LTMAUmABNpZ&2+-rqyx8IQ)e{p{mh3U3u_dF#LV{lRT|
X|0iSDUi059)$&QtJ(!x;rsw|;%7~!-

literal 0
HcmV?d00001

diff --git a/test/riscv-tests/rv64ssvnapot-p-napot.dump b/test/riscv-tests/rv64ssvnapot-p-napot.dump
new file mode 100644
index 000000000..7136b6755
--- /dev/null
+++ b/test/riscv-tests/rv64ssvnapot-p-napot.dump
@@ -0,0 +1,524553 @@
+
+rv64ssvnapot-p-napot:     file format elf64-littleriscv
+
+
+Disassembly of section .text.init:
+
+0000000080000000 <_start>:
+    80000000:	0540006f          	j	80000054 <reset_vector>
+
+0000000080000004 <trap_vector>:
+    80000004:	34202f73          	csrr	t5,mcause
+    80000008:	00800f93          	li	t6,8
+    8000000c:	03ff0a63          	beq	t5,t6,80000040 <write_tohost>
+    80000010:	00900f93          	li	t6,9
+    80000014:	03ff0663          	beq	t5,t6,80000040 <write_tohost>
+    80000018:	00b00f93          	li	t6,11
+    8000001c:	03ff0263          	beq	t5,t6,80000040 <write_tohost>
+    80000020:	00000f17          	auipc	t5,0x0
+    80000024:	30cf0f13          	addi	t5,t5,780 # 8000032c <mtvec_handler>
+    80000028:	000f0463          	beqz	t5,80000030 <trap_vector+0x2c>
+    8000002c:	000f0067          	jr	t5
+    80000030:	34202f73          	csrr	t5,mcause
+    80000034:	000f5463          	bgez	t5,8000003c <handle_exception>
+    80000038:	0040006f          	j	8000003c <handle_exception>
+
+000000008000003c <handle_exception>:
+    8000003c:	5391e193          	ori	gp,gp,1337
+
+0000000080000040 <write_tohost>:
+    80000040:	00001f17          	auipc	t5,0x1
+    80000044:	fc3f2023          	sw	gp,-64(t5) # 80001000 <tohost>
+    80000048:	00001f17          	auipc	t5,0x1
+    8000004c:	fa0f2e23          	sw	zero,-68(t5) # 80001004 <tohost+0x4>
+    80000050:	ff1ff06f          	j	80000040 <write_tohost>
+
+0000000080000054 <reset_vector>:
+    80000054:	00000093          	li	ra,0
+    80000058:	00000113          	li	sp,0
+    8000005c:	00000193          	li	gp,0
+    80000060:	00000213          	li	tp,0
+    80000064:	00000293          	li	t0,0
+    80000068:	00000313          	li	t1,0
+    8000006c:	00000393          	li	t2,0
+    80000070:	00000413          	li	s0,0
+    80000074:	00000493          	li	s1,0
+    80000078:	00000513          	li	a0,0
+    8000007c:	00000593          	li	a1,0
+    80000080:	00000613          	li	a2,0
+    80000084:	00000693          	li	a3,0
+    80000088:	00000713          	li	a4,0
+    8000008c:	00000793          	li	a5,0
+    80000090:	00000813          	li	a6,0
+    80000094:	00000893          	li	a7,0
+    80000098:	00000913          	li	s2,0
+    8000009c:	00000993          	li	s3,0
+    800000a0:	00000a13          	li	s4,0
+    800000a4:	00000a93          	li	s5,0
+    800000a8:	00000b13          	li	s6,0
+    800000ac:	00000b93          	li	s7,0
+    800000b0:	00000c13          	li	s8,0
+    800000b4:	00000c93          	li	s9,0
+    800000b8:	00000d13          	li	s10,0
+    800000bc:	00000d93          	li	s11,0
+    800000c0:	00000e13          	li	t3,0
+    800000c4:	00000e93          	li	t4,0
+    800000c8:	00000f13          	li	t5,0
+    800000cc:	00000f93          	li	t6,0
+    800000d0:	f1402573          	csrr	a0,mhartid
+    800000d4:	00051063          	bnez	a0,800000d4 <reset_vector+0x80>
+    800000d8:	00000297          	auipc	t0,0x0
+    800000dc:	01028293          	addi	t0,t0,16 # 800000e8 <reset_vector+0x94>
+    800000e0:	30529073          	csrw	mtvec,t0
+    800000e4:	74445073          	csrwi	0x744,8
+    800000e8:	00000297          	auipc	t0,0x0
+    800000ec:	01028293          	addi	t0,t0,16 # 800000f8 <reset_vector+0xa4>
+    800000f0:	30529073          	csrw	mtvec,t0
+    800000f4:	18005073          	csrwi	satp,0
+    800000f8:	00000297          	auipc	t0,0x0
+    800000fc:	02428293          	addi	t0,t0,36 # 8000011c <reset_vector+0xc8>
+    80000100:	30529073          	csrw	mtvec,t0
+    80000104:	0010029b          	addiw	t0,zero,1
+    80000108:	03529293          	slli	t0,t0,0x35
+    8000010c:	fff28293          	addi	t0,t0,-1
+    80000110:	3b029073          	csrw	pmpaddr0,t0
+    80000114:	01f00293          	li	t0,31
+    80000118:	3a029073          	csrw	pmpcfg0,t0
+    8000011c:	30405073          	csrwi	mie,0
+    80000120:	00000297          	auipc	t0,0x0
+    80000124:	01428293          	addi	t0,t0,20 # 80000134 <reset_vector+0xe0>
+    80000128:	30529073          	csrw	mtvec,t0
+    8000012c:	30205073          	csrwi	medeleg,0
+    80000130:	30305073          	csrwi	mideleg,0
+    80000134:	00000193          	li	gp,0
+    80000138:	00000297          	auipc	t0,0x0
+    8000013c:	ecc28293          	addi	t0,t0,-308 # 80000004 <trap_vector>
+    80000140:	30529073          	csrw	mtvec,t0
+    80000144:	00100513          	li	a0,1
+    80000148:	01f51513          	slli	a0,a0,0x1f
+    8000014c:	00055c63          	bgez	a0,80000164 <reset_vector+0x110>
+    80000150:	0ff0000f          	fence
+    80000154:	00100193          	li	gp,1
+    80000158:	05d00893          	li	a7,93
+    8000015c:	00000513          	li	a0,0
+    80000160:	00000073          	ecall
+    80000164:	00000293          	li	t0,0
+    80000168:	00028a63          	beqz	t0,8000017c <reset_vector+0x128>
+    8000016c:	10529073          	csrw	stvec,t0
+    80000170:	0000b2b7          	lui	t0,0xb
+    80000174:	1092829b          	addiw	t0,t0,265 # b109 <_start-0x7fff4ef7>
+    80000178:	30229073          	csrw	medeleg,t0
+    8000017c:	30005073          	csrwi	mstatus,0
+    80000180:	00002537          	lui	a0,0x2
+    80000184:	8005051b          	addiw	a0,a0,-2048 # 1800 <_start-0x7fffe800>
+    80000188:	30052073          	csrs	mstatus,a0
+    8000018c:	00000297          	auipc	t0,0x0
+    80000190:	01428293          	addi	t0,t0,20 # 800001a0 <reset_vector+0x14c>
+    80000194:	34129073          	csrw	mepc,t0
+    80000198:	f1402573          	csrr	a0,mhartid
+    8000019c:	30200073          	mret
+    800001a0:	00200517          	auipc	a0,0x200
+    800001a4:	e6050513          	addi	a0,a0,-416 # 80200000 <my_data>
+    800001a8:	00c55513          	srli	a0,a0,0xc
+    800001ac:	ff000593          	li	a1,-16
+    800001b0:	00b57533          	and	a0,a0,a1
+    800001b4:	00856513          	ori	a0,a0,8
+    800001b8:	00a51513          	slli	a0,a0,0xa
+    800001bc:	fff0059b          	addiw	a1,zero,-1
+    800001c0:	03f59593          	slli	a1,a1,0x3f
+    800001c4:	0df58593          	addi	a1,a1,223
+    800001c8:	00b56533          	or	a0,a0,a1
+    800001cc:	00100597          	auipc	a1,0x100
+    800001d0:	e3458593          	addi	a1,a1,-460 # 80100000 <begin_signature>
+    800001d4:	00858593          	addi	a1,a1,8
+    800001d8:	00a5b023          	sd	a0,0(a1)
+    800001dc:	00100517          	auipc	a0,0x100
+    800001e0:	e2450513          	addi	a0,a0,-476 # 80100000 <begin_signature>
+    800001e4:	00c55513          	srli	a0,a0,0xc
+    800001e8:	00a51513          	slli	a0,a0,0xa
+    800001ec:	00100593          	li	a1,1
+    800001f0:	00b56533          	or	a0,a0,a1
+    800001f4:	00100597          	auipc	a1,0x100
+    800001f8:	e0c58593          	addi	a1,a1,-500 # 80100000 <begin_signature>
+    800001fc:	00858593          	addi	a1,a1,8
+    80000200:	00001637          	lui	a2,0x1
+    80000204:	00c585b3          	add	a1,a1,a2
+    80000208:	00a5b023          	sd	a0,0(a1)
+    8000020c:	00100517          	auipc	a0,0x100
+    80000210:	df450513          	addi	a0,a0,-524 # 80100000 <begin_signature>
+    80000214:	000015b7          	lui	a1,0x1
+    80000218:	00b50533          	add	a0,a0,a1
+    8000021c:	00c55513          	srli	a0,a0,0xc
+    80000220:	00a51513          	slli	a0,a0,0xa
+    80000224:	00100593          	li	a1,1
+    80000228:	00b56533          	or	a0,a0,a1
+    8000022c:	00100597          	auipc	a1,0x100
+    80000230:	dd458593          	addi	a1,a1,-556 # 80100000 <begin_signature>
+    80000234:	00858593          	addi	a1,a1,8
+    80000238:	00002637          	lui	a2,0x2
+    8000023c:	00c585b3          	add	a1,a1,a2
+    80000240:	00a5b023          	sd	a0,0(a1)
+    80000244:	00200517          	auipc	a0,0x200
+    80000248:	dbc50513          	addi	a0,a0,-580 # 80200000 <my_data>
+    8000024c:	ffff05b7          	lui	a1,0xffff0
+    80000250:	00b57533          	and	a0,a0,a1
+    80000254:	000085b7          	lui	a1,0x8
+    80000258:	0105859b          	addiw	a1,a1,16 # 8010 <_start-0x7fff7ff0>
+    8000025c:	00b566b3          	or	a3,a0,a1
+    80000260:	00000593          	li	a1,0
+    80000264:	00b6a023          	sw	a1,0(a3)
+    80000268:	00100193          	li	gp,1
+    8000026c:	00100597          	auipc	a1,0x100
+    80000270:	d9458593          	addi	a1,a1,-620 # 80100000 <begin_signature>
+    80000274:	00002637          	lui	a2,0x2
+    80000278:	00c585b3          	add	a1,a1,a2
+    8000027c:	00c5d593          	srli	a1,a1,0xc
+    80000280:	fff0051b          	addiw	a0,zero,-1
+    80000284:	03f51513          	slli	a0,a0,0x3f
+    80000288:	00b56533          	or	a0,a0,a1
+    8000028c:	18051073          	csrw	satp,a0
+    80000290:	12000073          	sfence.vma
+    80000294:	000615b7          	lui	a1,0x61
+    80000298:	8005859b          	addiw	a1,a1,-2048 # 60800 <_start-0x7ff9f800>
+    8000029c:	3005a073          	csrs	mstatus,a1
+    800002a0:	40201537          	lui	a0,0x40201
+    800002a4:	0105051b          	addiw	a0,a0,16 # 40201010 <_start-0x3fdfeff0>
+    800002a8:	02a00593          	li	a1,42
+
+00000000800002ac <napot_store>:
+    800002ac:	00b52023          	sw	a1,0(a0)
+    800002b0:	000205b7          	lui	a1,0x20
+    800002b4:	3005b073          	csrc	mstatus,a1
+    800002b8:	0006a583          	lw	a1,0(a3)
+    800002bc:	02a00513          	li	a0,42
+    800002c0:	08a58c63          	beq	a1,a0,80000358 <die>
+    800002c4:	00200517          	auipc	a0,0x200
+    800002c8:	d3c50513          	addi	a0,a0,-708 # 80200000 <my_data>
+    800002cc:	000015b7          	lui	a1,0x1
+    800002d0:	0105859b          	addiw	a1,a1,16 # 1010 <_start-0x7fffeff0>
+    800002d4:	00b50533          	add	a0,a0,a1
+    800002d8:	00052583          	lw	a1,0(a0)
+    800002dc:	02a00613          	li	a2,42
+    800002e0:	06c59c63          	bne	a1,a2,80000358 <die>
+    800002e4:	0ff0000f          	fence
+    800002e8:	00100193          	li	gp,1
+    800002ec:	05d00893          	li	a7,93
+    800002f0:	00000513          	li	a0,0
+    800002f4:	00000073          	ecall
+    800002f8:	02301063          	bne	zero,gp,80000318 <pass>
+
+00000000800002fc <fail>:
+    800002fc:	0ff0000f          	fence
+    80000300:	00018063          	beqz	gp,80000300 <fail+0x4>
+    80000304:	00119193          	slli	gp,gp,0x1
+    80000308:	0011e193          	ori	gp,gp,1
+    8000030c:	05d00893          	li	a7,93
+    80000310:	00018513          	mv	a0,gp
+    80000314:	00000073          	ecall
+
+0000000080000318 <pass>:
+    80000318:	0ff0000f          	fence
+    8000031c:	00100193          	li	gp,1
+    80000320:	05d00893          	li	a7,93
+    80000324:	00000513          	li	a0,0
+    80000328:	00000073          	ecall
+
+000000008000032c <mtvec_handler>:
+    8000032c:	34202f73          	csrr	t5,mcause
+    80000330:	00f00f93          	li	t6,15
+    80000334:	03ff1263          	bne	t5,t6,80000358 <die>
+    80000338:	34102f73          	csrr	t5,mepc
+    8000033c:	00000f97          	auipc	t6,0x0
+    80000340:	f70f8f93          	addi	t6,t6,-144 # 800002ac <napot_store>
+    80000344:	01ff1a63          	bne	t5,t6,80000358 <die>
+    80000348:	34302f73          	csrr	t5,mtval
+    8000034c:	40201fb7          	lui	t6,0x40201
+    80000350:	010f8f9b          	addiw	t6,t6,16 # 40201010 <_start-0x3fdfeff0>
+    80000354:	fdff02e3          	beq	t5,t6,80000318 <pass>
+
+0000000080000358 <die>:
+    80000358:	0ff0000f          	fence
+    8000035c:	00018063          	beqz	gp,8000035c <die+0x4>
+    80000360:	00119193          	slli	gp,gp,0x1
+    80000364:	0011e193          	ori	gp,gp,1
+    80000368:	05d00893          	li	a7,93
+    8000036c:	00018513          	mv	a0,gp
+    80000370:	00000073          	ecall
+    80000374:	c0001073          	unimp
+    80000378:	0000                	.insn	2, 0x
+    8000037a:	0000                	.insn	2, 0x
+    8000037c:	0000                	.insn	2, 0x
+    8000037e:	0000                	.insn	2, 0x
+
+Disassembly of section .data:
+
+0000000080100000 <begin_signature>:
+    80100000:	0000                	.insn	2, 0x
+    80100002:	0000                	.insn	2, 0x
+    80100004:	0000                	.insn	2, 0x
+    80100006:	0000                	.insn	2, 0x
+    80100008:	0000                	.insn	2, 0x
+    8010000a:	0000                	.insn	2, 0x
+    8010000c:	0000                	.insn	2, 0x
+    8010000e:	0000                	.insn	2, 0x
+    80100010:	0000                	.insn	2, 0x
+    80100012:	0000                	.insn	2, 0x
+    80100014:	0000                	.insn	2, 0x
+    80100016:	0000                	.insn	2, 0x
+    80100018:	0000                	.insn	2, 0x
+    8010001a:	0000                	.insn	2, 0x
+    8010001c:	0000                	.insn	2, 0x
+    8010001e:	0000                	.insn	2, 0x
+    80100020:	0000                	.insn	2, 0x
+    80100022:	0000                	.insn	2, 0x
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From 613d39f39fc10b7214be75a2fce89281271f0b09 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Thu, 4 Jul 2024 19:13:41 +0800
Subject: [PATCH 2/3] Add svnapot extention support

---
 c_emulator/riscv_rvfi_RV64 | Bin 13911144 -> 0 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 delete mode 100755 c_emulator/riscv_rvfi_RV64

diff --git a/c_emulator/riscv_rvfi_RV64 b/c_emulator/riscv_rvfi_RV64
deleted file mode 100755
index 309f4e583c7176218377b2837729a250ee58d425..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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From e9b8d5ba2dcf5b79acede2f246111f6966f746d6 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Thu, 4 Jul 2024 22:38:18 +0800
Subject: [PATCH 3/3] Add svnapot extention support

---
 c_emulator/riscv_rvfi_RV64 | Bin 0 -> 13894720 bytes
 model/riscv_vmem.sail      |  23 ++++++++---------------
 model/riscv_vmem_ptw.sail  |  18 ++++++++++--------
 3 files changed, 18 insertions(+), 23 deletions(-)
 create mode 100755 c_emulator/riscv_rvfi_RV64

diff --git a/c_emulator/riscv_rvfi_RV64 b/c_emulator/riscv_rvfi_RV64
new file mode 100755
index 0000000000000000000000000000000000000000..a034aebb1bdc4d4171e741c7daf597cfe4123fec
GIT binary patch
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literal 0
HcmV?d00001

diff --git a/model/riscv_vmem.sail b/model/riscv_vmem.sail
index 4987d0b71..f980e5636 100644
--- a/model/riscv_vmem.sail
+++ b/model/riscv_vmem.sail
@@ -45,15 +45,6 @@ function vpn_j_of_va(sv_params : SV_Params,
   ((va >> lsb) & mask)
 }
 
-// PRIVATE: Count trailing zeros
-function LowestSetBit(x : bits(64)) -> bits(64) = {
-  var count : bits(64) = zeros();
-  let perfect_one : bits(64) = 0x0000_0000_0000_0001;
-  foreach (i from 0 to (sizeof(xlen) - 1) by 1 in inc)
-    if [x[i]] == 0b1 then return(count + perfect_one) else (count = count + perfect_one);
-  return count;
-}
-
 // PRIVATE: Extract offset within page from VA
 function offset_of_va(va : bits(64)) -> bits(PAGESIZE_BITS) = va[pagesize_bits - 1 .. 0]
 
@@ -176,23 +167,25 @@ function pt_walk(sv_params,
                 let mask_bits = level * sv_params.pte_PPN_j_size_bits;
                 let mask : bits(64) = ~ (ones() << mask_bits);
                 let ppn : bits(64) = ppns | (vpns_of_va(sv_params, va) & mask);
-                let napot_bits  = LowestSetBit(ppn);
-                let perfect_one : bits(64) = 0x0000_0000_0000_0001;
-                let napot_mask : bits(64) = (perfect_one << napot_bits) - perfect_one;
+                let napot_mask : bits(64) = ppn ^ (ppn - 1);
                 let napot_mask_not : bits(64) = ~ (napot_mask);
                 let ptshift_level = sv_params.levels - 1;
                 let ptshift = ptshift_level * sv_params.vpn_size_bits;
 
                 let page_base = (ppn & napot_mask_not) | 
                                 (vpns_of_va(sv_params, va) & napot_mask) | 
-                                (vpns_of_va(sv_params, va) & ((perfect_one << ptshift) - perfect_one));
+                                (vpns_of_va(sv_params, va) & ((zero_extend(0b1) << ptshift) - zero_extend(0b1)));
 
                 let pa = (ppns << pagesize_bits) | zero_extend(offset_of_va(va));
                 let pa_napot = page_base << 12 | zero_extend(offset_of_va(va));
 
                 // For svnapot ext purpose.
-                if (pte & (perfect_one << 63)) == (perfect_one << 63) then {
-                  return PTW_Success(pa_napot, pte, pte_addr, level, global', ext_ptw)
+                if (pte & (zero_extend(0b1) << 63)) == (zero_extend(0b1) << 63) then {
+                  if (napot_mask != zero_extend(0xf)) then {
+                    return PTW_Failure(PTW_Invalid_PTE(), ext_ptw)
+                  } else {
+                    return PTW_Success(pa_napot, pte, pte_addr, level, global', ext_ptw)
+                  }
                 };
 
                 PTW_Success(pa, pte, pte_addr, level, global', ext_ptw)
diff --git a/model/riscv_vmem_ptw.sail b/model/riscv_vmem_ptw.sail
index ab73b1909..9b33be010 100644
--- a/model/riscv_vmem_ptw.sail
+++ b/model/riscv_vmem_ptw.sail
@@ -15,13 +15,14 @@
 // Failure modes for address-translation/page-table-walks
 // PRIVATE
 union PTW_Error = {
-  PTW_Invalid_Addr  : unit,          // invalid source address
-  PTW_Access        : unit,          // physical memory access error for a PTE
-  PTW_Invalid_PTE   : unit,
-  PTW_No_Permission : unit,
-  PTW_Misaligned    : unit,          // misaligned superpage
-  PTW_PTE_Update    : unit,          // PTE update needed but not enabled
-  PTW_Ext_Error     : ext_ptw_error  // parameterized for errors from extensions
+  PTW_Invalid_Addr    : unit,          // invalid source address
+  PTW_Access          : unit,          // physical memory access error for a PTE
+  PTW_Invalid_PTE     : unit,
+  PTW_No_Permission   : unit,
+  PTW_Misaligned      : unit,          // misaligned superpage
+  PTW_PTE_Update      : unit,          // PTE update needed but not enabled
+  PTW_Ext_Error       : ext_ptw_error, // parameterized for errors from extensions
+  PTW_Unsupport_Napot : unit           // Unsupport Napot bits
 }
 
 // PRIVATE: only 'to_str' overload is public
@@ -33,7 +34,8 @@ function ptw_error_to_str(e : PTW_Error) -> string = {
     PTW_No_Permission()  => "no-permission",
     PTW_Misaligned()     => "misaligned-superpage",
     PTW_PTE_Update()     => "pte-update-needed",
-    PTW_Ext_Error(e)     => "extension-error"
+    PTW_Ext_Error(e)     => "extension-error",
+    PTW_Unsupport_Napot()=> "unsupport napot bits"
   }
 }