From 28bd3bee8b473f249cbc53717f817aed9aa2abc5 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sat, 28 Sep 2024 19:12:13 +0800
Subject: [PATCH 1/8] replace vxrm with vcsr[vxrm]

---
 model/riscv_insts_vext_utils.sail |  2 +-
 model/riscv_insts_zicsr.sail      |  2 +-
 model/riscv_sys_control.sail      |  3 +-
 model/riscv_sys_regs.sail         |  1 -
 vtest.py                          | 47 +++++++++++++++++++++++++++++++
 5 files changed, 50 insertions(+), 5 deletions(-)
 create mode 100644 vtest.py

diff --git a/model/riscv_insts_vext_utils.sail b/model/riscv_insts_vext_utils.sail
index 5aa5bdff1..879b17170 100755
--- a/model/riscv_insts_vext_utils.sail
+++ b/model/riscv_insts_vext_utils.sail
@@ -399,7 +399,7 @@ val get_fixed_rounding_incr : forall ('m 'n : Int), ('m > 0 & 'n >= 0). (bits('m
 function get_fixed_rounding_incr(vec_elem, shift_amount) = {
   if shift_amount == 0 then 0b0
   else {
-    let rounding_mode = vxrm[1 .. 0];
+    let rounding_mode = vcsr[vxrm];
     match rounding_mode {
       0b00 => slice(vec_elem, shift_amount - 1, 1),
       0b01 => bool_to_bits(
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index c96d31a5b..544b41289 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -72,7 +72,7 @@ function clause read_CSR(0b1011100 /* 0xB80 */ @ index : bits(5) if sizeof(xlen)
 /* vector */
 function clause read_CSR(0x008) = zero_extend(vstart)
 function clause read_CSR(0x009) = zero_extend(vxsat)
-function clause read_CSR(0x00A) = zero_extend(vxrm)
+function clause read_CSR(0x00A) = zero_extend(vcsr[vxrm])
 function clause read_CSR(0x00F) = zero_extend(vcsr.bits)
 function clause read_CSR(0xC20) = vl
 function clause read_CSR(0xC21) = vtype.bits
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 8a8c9daa7..28f5c0301 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -558,8 +558,7 @@ function init_sys() -> unit = {
    */
   vstart             = zero_extend(0b0);
   vxsat              = 0b0;
-  vxrm               = 0b00;
-  vcsr[vxrm]       = vxrm;
+  vcsr[]       = vxrm;
   vcsr[vxsat]      = vxsat;
   vl                 = zero_extend(0b0);
   vtype[vill]      = 0b1;
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 65336f2e1..600ce26e3 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -857,7 +857,6 @@ function is_fiom_active() -> bool = {
 /* vector csrs */
 register vstart : bits(16) /* use the largest possible length of vstart */
 register vxsat  : bits(1)
-register vxrm   : bits(2)
 register vl     : xlenbits
 register vlenb  : xlenbits
 
diff --git a/vtest.py b/vtest.py
new file mode 100644
index 000000000..38ca44c6f
--- /dev/null
+++ b/vtest.py
@@ -0,0 +1,47 @@
+import os
+import subprocess
+import pandas as pd
+
+# 测试目录和模拟器路径
+TEST_DIR = "/home/rez/workbench/riscv-vector-tests/out/v512x64machine/bin/stage2/"
+EMULATOR = "/home/rez/workbench/prtest/sail-riscv/c_emulator/riscv_sim_RV64"
+
+# 结果列表
+results = []
+
+# 遍历 TEST_DIR 下的所有文件
+for root, dirs, files in os.walk(TEST_DIR):
+    for file in files:
+        test_path = os.path.join(root, file)
+        print(f"Running {test_path}...")
+
+        # 运行测试并捕获输出
+        try:
+            result = subprocess.run([EMULATOR, test_path], capture_output=True, text=True, timeout=60)
+            last_line = result.stdout.splitlines()[-1] if result.stdout else ""
+        except subprocess.TimeoutExpired:
+            last_line = "TIMEOUT"
+
+        # 判断测试结果
+        if "FAILURE" in last_line:
+            status = "FAILED"
+        elif "TIMEOUT" in last_line:
+            status = "TIMEOUT"
+        else:
+            status = "SUCCEEDED"
+
+        # 将测试结果保存到列表
+        results.append({
+            "Test File": test_path,
+            "Last Line": last_line,
+            "Status": status
+        })
+
+# 生成结果表格
+df = pd.DataFrame(results)
+
+# 将结果保存为 CSV 文件
+df.to_csv("test_results.csv", index=False)
+
+# 打印表格
+print(df)

From ad450e9bfab25ecd94453df40ac262d61c0a5ff5 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sat, 28 Sep 2024 19:19:47 +0800
Subject: [PATCH 2/8] replace vxrm with vcsr[vxrm]

---
 model/riscv_insts_zicsr.sail | 2 +-
 model/riscv_sys_control.sail | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 544b41289..9f32701ab 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -190,7 +190,7 @@ function clause write_CSR(0x015, value) = write_seed_csr()
 /* vector */
 function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
 function clause write_CSR(0x009, value) = { vxsat = value[0 .. 0]; zero_extend(vxsat) }
-function clause write_CSR(0x00A, value) = { vxrm = value[1 .. 0]; zero_extend(vxrm) }
+function clause write_CSR(0x00A, value) = { vcsr[vxrm] = value[1 .. 0]; zero_extend(vcsr[vxrm]) }
 function clause write_CSR(0x00F, value) = { vcsr.bits = value[2 ..0]; zero_extend(vcsr.bits) }
 function clause write_CSR(0xC20, value) = { vl = value; vl }
 function clause write_CSR(0xC21, value) = { vtype.bits = value; vtype.bits }
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 28f5c0301..3a2772f4e 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -558,7 +558,6 @@ function init_sys() -> unit = {
    */
   vstart             = zero_extend(0b0);
   vxsat              = 0b0;
-  vcsr[]       = vxrm;
   vcsr[vxsat]      = vxsat;
   vl                 = zero_extend(0b0);
   vtype[vill]      = 0b1;

From 46bd47e3979752edebe4dc7a54e0ffec360e7047 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sat, 28 Sep 2024 19:36:59 +0800
Subject: [PATCH 3/8] replace vxrm with vcsr[vxrm]

---
 vtest.py | 47 -----------------------------------------------
 1 file changed, 47 deletions(-)
 delete mode 100644 vtest.py

diff --git a/vtest.py b/vtest.py
deleted file mode 100644
index 38ca44c6f..000000000
--- a/vtest.py
+++ /dev/null
@@ -1,47 +0,0 @@
-import os
-import subprocess
-import pandas as pd
-
-# 测试目录和模拟器路径
-TEST_DIR = "/home/rez/workbench/riscv-vector-tests/out/v512x64machine/bin/stage2/"
-EMULATOR = "/home/rez/workbench/prtest/sail-riscv/c_emulator/riscv_sim_RV64"
-
-# 结果列表
-results = []
-
-# 遍历 TEST_DIR 下的所有文件
-for root, dirs, files in os.walk(TEST_DIR):
-    for file in files:
-        test_path = os.path.join(root, file)
-        print(f"Running {test_path}...")
-
-        # 运行测试并捕获输出
-        try:
-            result = subprocess.run([EMULATOR, test_path], capture_output=True, text=True, timeout=60)
-            last_line = result.stdout.splitlines()[-1] if result.stdout else ""
-        except subprocess.TimeoutExpired:
-            last_line = "TIMEOUT"
-
-        # 判断测试结果
-        if "FAILURE" in last_line:
-            status = "FAILED"
-        elif "TIMEOUT" in last_line:
-            status = "TIMEOUT"
-        else:
-            status = "SUCCEEDED"
-
-        # 将测试结果保存到列表
-        results.append({
-            "Test File": test_path,
-            "Last Line": last_line,
-            "Status": status
-        })
-
-# 生成结果表格
-df = pd.DataFrame(results)
-
-# 将结果保存为 CSV 文件
-df.to_csv("test_results.csv", index=False)
-
-# 打印表格
-print(df)

From 5295652dcc478d69dc64e44b826563d0a5a36386 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sat, 28 Sep 2024 20:02:26 +0800
Subject: [PATCH 4/8] replace vxrm with vcsr[vxrm]

---
 model/riscv_insts_vext_utils.sail | 10 +++++-----
 model/riscv_insts_zicsr.sail      |  4 ++--
 model/riscv_sys_control.sail      |  2 --
 model/riscv_sys_regs.sail         |  1 -
 4 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/model/riscv_insts_vext_utils.sail b/model/riscv_insts_vext_utils.sail
index 879b17170..c1f6a9231 100755
--- a/model/riscv_insts_vext_utils.sail
+++ b/model/riscv_insts_vext_utils.sail
@@ -415,10 +415,10 @@ function get_fixed_rounding_incr(vec_elem, shift_amount) = {
 val unsigned_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)
 function unsigned_saturation(len, elem) = {
   if unsigned(elem) > unsigned(ones('m)) then {
-    vxsat = 0b1;
+    vcsr[vxsat] = 0b1;
     ones('m)
   } else {
-    vxsat = 0b0;
+    vcsr[vxsat] = 0b0;
     elem['m - 1 .. 0]
   }
 }
@@ -427,13 +427,13 @@ function unsigned_saturation(len, elem) = {
 val signed_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)
 function signed_saturation(len, elem) = {
   if signed(elem) > signed(0b0 @ ones('m - 1)) then {
-    vxsat = 0b1;
+    vcsr[vxsat] = 0b1;
     0b0 @ ones('m - 1)
   } else if signed(elem) < signed(0b1 @ zeros('m - 1)) then {
-    vxsat = 0b1;
+    vcsr[vxsat] = 0b1;
     0b1 @ zeros('m - 1)
   } else {
-    vxsat = 0b0;
+    vcsr[vxsat] = 0b0;
     elem['m - 1 .. 0]
   };
 }
diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 9f32701ab..1ac8fa5a8 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -71,7 +71,7 @@ function clause read_CSR(0b1011100 /* 0xB80 */ @ index : bits(5) if sizeof(xlen)
 
 /* vector */
 function clause read_CSR(0x008) = zero_extend(vstart)
-function clause read_CSR(0x009) = zero_extend(vxsat)
+function clause read_CSR(0x009) = zero_extend(vcsr[vxsat])
 function clause read_CSR(0x00A) = zero_extend(vcsr[vxrm])
 function clause read_CSR(0x00F) = zero_extend(vcsr.bits)
 function clause read_CSR(0xC20) = vl
@@ -189,7 +189,7 @@ function clause write_CSR(0x015, value) = write_seed_csr()
 
 /* vector */
 function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
-function clause write_CSR(0x009, value) = { vxsat = value[0 .. 0]; zero_extend(vxsat) }
+function clause write_CSR(0x009, value) = { vcsr[vxsat] = value[0 .. 0]; zero_extend(vcsr[vxsat]) }
 function clause write_CSR(0x00A, value) = { vcsr[vxrm] = value[1 .. 0]; zero_extend(vcsr[vxrm]) }
 function clause write_CSR(0x00F, value) = { vcsr.bits = value[2 ..0]; zero_extend(vcsr.bits) }
 function clause write_CSR(0xC20, value) = { vl = value; vl }
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 3a2772f4e..29a1eb444 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -557,8 +557,6 @@ function init_sys() -> unit = {
    * See riscv_vlen.sail for details.
    */
   vstart             = zero_extend(0b0);
-  vxsat              = 0b0;
-  vcsr[vxsat]      = vxsat;
   vl                 = zero_extend(0b0);
   vtype[vill]      = 0b1;
   vtype[reserved]  = zero_extend(0b0);
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 600ce26e3..eb377ec18 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -856,7 +856,6 @@ function is_fiom_active() -> bool = {
 }
 /* vector csrs */
 register vstart : bits(16) /* use the largest possible length of vstart */
-register vxsat  : bits(1)
 register vl     : xlenbits
 register vlenb  : xlenbits
 

From 54e016c5d8180ca843a0009d9aab40e316ce8319 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sun, 29 Sep 2024 11:07:21 +0800
Subject: [PATCH 5/8] replace vxrm with vcsr[vxrm]

---
 model/riscv_sys_control.sail | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index 29a1eb444..a3ee54996 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -558,6 +558,8 @@ function init_sys() -> unit = {
    */
   vstart             = zero_extend(0b0);
   vl                 = zero_extend(0b0);
+  vcsr[vxrm]       = vxrm;
+  vcsr[vxsat]      = vxsat;
   vtype[vill]      = 0b1;
   vtype[reserved]  = zero_extend(0b0);
   vtype[vma]       = 0b0;

From 207bfcce5783a373a8edae30e457e15cb7762dbf Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Sun, 29 Sep 2024 11:26:50 +0800
Subject: [PATCH 6/8] replace vxrm with vcsr[vxrm]

---
 model/riscv_sys_control.sail | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index a3ee54996..82b458740 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -558,8 +558,8 @@ function init_sys() -> unit = {
    */
   vstart             = zero_extend(0b0);
   vl                 = zero_extend(0b0);
-  vcsr[vxrm]       = vxrm;
-  vcsr[vxsat]      = vxsat;
+  vcsr[vxrm]       = 0b00;
+  vcsr[vxsat]      = 0b0;
   vtype[vill]      = 0b1;
   vtype[reserved]  = zero_extend(0b0);
   vtype[vma]       = 0b0;

From 8cb480b3d16f1f47ebb6abbecc95f3b28c64d7c4 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Wed, 2 Oct 2024 12:42:48 +0800
Subject: [PATCH 7/8] replace vxrm with vcsr[vxrm]

replace vxrm with vcsr[vxrm]
---
 model/riscv_vext_control.sail | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/model/riscv_vext_control.sail b/model/riscv_vext_control.sail
index 38d0e0caa..82f15af9b 100755
--- a/model/riscv_vext_control.sail
+++ b/model/riscv_vext_control.sail
@@ -19,10 +19,6 @@ function clause read_CSR (0x009) = zero_extend(vcsr[vxsat])
 function clause read_CSR (0x00A) = zero_extend(vcsr[vxrm])
 function clause read_CSR (0x00F) = zero_extend(vcsr.bits)
 
-function clause read_CSR (0x009) = zero_extend(vcsr[vxsat])
-function clause read_CSR (0x00A) = zero_extend(vcsr[vxrm])
-function clause read_CSR (0x00F) = zero_extend(vcsr.bits)
-
 function clause write_CSR (0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); zero_extend(vcsr[vxsat]) }
 function clause write_CSR (0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); zero_extend(vcsr[vxrm]) }
 function clause write_CSR (0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); zero_extend(vcsr.bits) }

From dae4fc00b0f06720c253667dcaa83b45dcce2d48 Mon Sep 17 00:00:00 2001
From: Yui5427 <785369607@qq.com>
Date: Wed, 2 Oct 2024 13:07:50 +0800
Subject: [PATCH 8/8] replace vxrm with vcsr[vxrm]

---
 model/riscv_insts_zicsr.sail  | 18 ------------------
 model/riscv_vext_control.sail | 27 +++++++++++++++++----------
 2 files changed, 17 insertions(+), 28 deletions(-)

diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail
index 1ac8fa5a8..adb7f9f9f 100644
--- a/model/riscv_insts_zicsr.sail
+++ b/model/riscv_insts_zicsr.sail
@@ -69,15 +69,6 @@ function clause read_CSR(0xB82 if sizeof(xlen) == 32) = minstret[63 .. 32]
 function clause read_CSR(0b1011000 /* 0xB00 */ @ index : bits(5) if unsigned(index) >= 3) = read_mhpmcounter(hpmidx_from_bits(index))
 function clause read_CSR(0b1011100 /* 0xB80 */ @ index : bits(5) if sizeof(xlen) == 32 & unsigned(index) >= 3) = read_mhpmcounterh(hpmidx_from_bits(index))
 
-/* vector */
-function clause read_CSR(0x008) = zero_extend(vstart)
-function clause read_CSR(0x009) = zero_extend(vcsr[vxsat])
-function clause read_CSR(0x00A) = zero_extend(vcsr[vxrm])
-function clause read_CSR(0x00F) = zero_extend(vcsr.bits)
-function clause read_CSR(0xC20) = vl
-function clause read_CSR(0xC21) = vtype.bits
-function clause read_CSR(0xC22) = vlenb
-
 /* trigger/debug */
 function clause read_CSR(0x7a0) = ~(tselect)  /* this indicates we don't have any trigger support */
 
@@ -187,15 +178,6 @@ function clause write_CSR(0x180, value) = { satp = legalize_satp(cur_Architectur
 /* user mode: seed (entropy source). writes are ignored */
 function clause write_CSR(0x015, value) = write_seed_csr()
 
-/* vector */
-function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
-function clause write_CSR(0x009, value) = { vcsr[vxsat] = value[0 .. 0]; zero_extend(vcsr[vxsat]) }
-function clause write_CSR(0x00A, value) = { vcsr[vxrm] = value[1 .. 0]; zero_extend(vcsr[vxrm]) }
-function clause write_CSR(0x00F, value) = { vcsr.bits = value[2 ..0]; zero_extend(vcsr.bits) }
-function clause write_CSR(0xC20, value) = { vl = value; vl }
-function clause write_CSR(0xC21, value) = { vtype.bits = value; vtype.bits }
-function clause write_CSR(0xC22, value) = { vlenb = value; vlenb }
-
 function clause execute CSR(csr, rs1, rd, is_imm, op) = {
   let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1);
   let isWrite : bool = match op {
diff --git a/model/riscv_vext_control.sail b/model/riscv_vext_control.sail
index 82f15af9b..3dabc1fc0 100755
--- a/model/riscv_vext_control.sail
+++ b/model/riscv_vext_control.sail
@@ -7,18 +7,25 @@
 /*=======================================================================================*/
 
 function clause is_CSR_defined (0x008) = true
-function clause is_CSR_defined (0xC20) = true
-function clause is_CSR_defined (0xC21) = true
-function clause is_CSR_defined (0xC22) = true
-
 function clause is_CSR_defined (0x009) = true
 function clause is_CSR_defined (0x00A) = true
 function clause is_CSR_defined (0x00F) = true
+function clause is_CSR_defined (0xC20) = true
+function clause is_CSR_defined (0xC21) = true
+function clause is_CSR_defined (0xC22) = true
 
-function clause read_CSR (0x009) = zero_extend(vcsr[vxsat])
-function clause read_CSR (0x00A) = zero_extend(vcsr[vxrm])
-function clause read_CSR (0x00F) = zero_extend(vcsr.bits)
+function clause read_CSR(0x008) = zero_extend(vstart)
+function clause read_CSR(0x009) = zero_extend(vcsr[vxsat])
+function clause read_CSR(0x00A) = zero_extend(vcsr[vxrm])
+function clause read_CSR(0x00F) = zero_extend(vcsr.bits)
+function clause read_CSR(0xC20) = vl
+function clause read_CSR(0xC21) = vtype.bits
+function clause read_CSR(0xC22) = vlenb
 
-function clause write_CSR (0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); zero_extend(vcsr[vxsat]) }
-function clause write_CSR (0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); zero_extend(vcsr[vxrm]) }
-function clause write_CSR (0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); zero_extend(vcsr.bits) }
+function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
+function clause write_CSR(0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); zero_extend(vcsr[vxsat]) }
+function clause write_CSR(0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); zero_extend(vcsr[vxrm]) }
+function clause write_CSR(0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); zero_extend(vcsr.bits) }
+function clause write_CSR(0xC20, value) = { vl = value; vl }
+function clause write_CSR(0xC21, value) = { vtype.bits = value; vtype.bits }
+function clause write_CSR(0xC22, value) = { vlenb = value; vlenb }