Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

replace vxrm with vcsr[vxrm] #564

Open
wants to merge 6 commits into
base: master
Choose a base branch
from
Open

replace vxrm with vcsr[vxrm] #564

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
28bd3be
replace vxrm with vcsr[vxrm]
Yui5427 Sep 28, 2024
ad450e9
replace vxrm with vcsr[vxrm]
Yui5427 Sep 28, 2024
46bd47e
replace vxrm with vcsr[vxrm]
Yui5427 Sep 28, 2024
5295652
replace vxrm with vcsr[vxrm]
Yui5427 Sep 28, 2024
54e016c
replace vxrm with vcsr[vxrm]
Yui5427 Sep 29, 2024
207bfcc
replace vxrm with vcsr[vxrm]
Yui5427 Sep 29, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 6 additions & 6 deletions model/riscv_insts_vext_utils.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -399,7 +399,7 @@ val get_fixed_rounding_incr : forall ('m 'n : Int), ('m > 0 & 'n >= 0). (bits('m
function get_fixed_rounding_incr(vec_elem, shift_amount) = {
if shift_amount == 0 then 0b0
else {
let rounding_mode = vxrm[1 .. 0];
let rounding_mode = vcsr[vxrm];
match rounding_mode {
0b00 => slice(vec_elem, shift_amount - 1, 1),
0b01 => bool_to_bits(
Expand All @@ -415,10 +415,10 @@ function get_fixed_rounding_incr(vec_elem, shift_amount) = {
val unsigned_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)
function unsigned_saturation(len, elem) = {
if unsigned(elem) > unsigned(ones('m)) then {
vxsat = 0b1;
vcsr[vxsat] = 0b1;
ones('m)
} else {
vxsat = 0b0;
vcsr[vxsat] = 0b0;
elem['m - 1 .. 0]
}
}
Expand All @@ -427,13 +427,13 @@ function unsigned_saturation(len, elem) = {
val signed_saturation : forall ('m 'n: Int), ('n >= 'm > 1). (int('m), bits('n)) -> bits('m)
function signed_saturation(len, elem) = {
if signed(elem) > signed(0b0 @ ones('m - 1)) then {
vxsat = 0b1;
vcsr[vxsat] = 0b1;
0b0 @ ones('m - 1)
} else if signed(elem) < signed(0b1 @ zeros('m - 1)) then {
vxsat = 0b1;
vcsr[vxsat] = 0b1;
0b1 @ zeros('m - 1)
} else {
vxsat = 0b0;
vcsr[vxsat] = 0b0;
elem['m - 1 .. 0]
};
}
Expand Down
8 changes: 4 additions & 4 deletions model/riscv_insts_zicsr.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -71,8 +71,8 @@ function clause read_CSR(0b1011100 /* 0xB80 */ @ index : bits(5) if sizeof(xlen)

/* vector */
function clause read_CSR(0x008) = zero_extend(vstart)
function clause read_CSR(0x009) = zero_extend(vxsat)
function clause read_CSR(0x00A) = zero_extend(vxrm)
function clause read_CSR(0x009) = zero_extend(vcsr[vxsat])
function clause read_CSR(0x00A) = zero_extend(vcsr[vxrm])
function clause read_CSR(0x00F) = zero_extend(vcsr.bits)
function clause read_CSR(0xC20) = vl
function clause read_CSR(0xC21) = vtype.bits
Expand Down Expand Up @@ -189,8 +189,8 @@ function clause write_CSR(0x015, value) = write_seed_csr()

/* vector */
function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
function clause write_CSR(0x009, value) = { vxsat = value[0 .. 0]; zero_extend(vxsat) }
function clause write_CSR(0x00A, value) = { vxrm = value[1 .. 0]; zero_extend(vxrm) }
function clause write_CSR(0x009, value) = { vcsr[vxsat] = value[0 .. 0]; zero_extend(vcsr[vxsat]) }
function clause write_CSR(0x00A, value) = { vcsr[vxrm] = value[1 .. 0]; zero_extend(vcsr[vxrm]) }
function clause write_CSR(0x00F, value) = { vcsr.bits = value[2 ..0]; zero_extend(vcsr.bits) }
function clause write_CSR(0xC20, value) = { vl = value; vl }
function clause write_CSR(0xC21, value) = { vtype.bits = value; vtype.bits }
Expand Down
6 changes: 2 additions & 4 deletions model/riscv_sys_control.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -557,11 +557,9 @@ function init_sys() -> unit = {
* See riscv_vlen.sail for details.
*/
vstart = zero_extend(0b0);
vxsat = 0b0;
vxrm = 0b00;
vcsr[vxrm] = vxrm;
vcsr[vxsat] = vxsat;
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This might want to be vcsr[vxrm] = 0b00 and vcsr[vxsat] = 0b0 rather than removing both.

vl = zero_extend(0b0);
vcsr[vxrm] = 0b00;
vcsr[vxsat] = 0b0;
vtype[vill] = 0b1;
vtype[reserved] = zero_extend(0b0);
vtype[vma] = 0b0;
Expand Down
2 changes: 0 additions & 2 deletions model/riscv_sys_regs.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -856,8 +856,6 @@ function is_fiom_active() -> bool = {
}
/* vector csrs */
register vstart : bits(16) /* use the largest possible length of vstart */
register vxsat : bits(1)
register vxrm : bits(2)
register vl : xlenbits
register vlenb : xlenbits

Expand Down
Loading