From f82993a30d0c7d9ed54e0c6276636e56b9fbecbf Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Thu, 24 Oct 2024 16:07:07 +0000 Subject: [PATCH] librz/arch: capstone v6 update (without MIPS) (#4662) * Bumps Capstone version to newest Capstone next (beyond first v6-Alpha1). * Fixes leaks * Fixes build and change to AArch64 and SystemZ compatibility headers. * Marks M68k test as broken (see commit message). * Fix AArch64 and SystemZ tests * Handle op.size == 0 for x86 IL ops --- .github/workflows/ci.yml | 10 + doc/PACKAGERS.md | 2 +- librz/arch/isa/arm/aarch64_meta_macros.h | 69 - librz/arch/isa/arm/arm_accessors32.h | 23 +- librz/arch/isa/arm/arm_accessors64.h | 29 +- librz/arch/isa/arm/arm_cs.h | 6 +- librz/arch/isa/arm/arm_esil32.c | 5 + librz/arch/isa/arm/arm_esil64.c | 483 ++-- librz/arch/isa/arm/arm_il32.c | 8 + librz/arch/isa/arm/arm_il64.c | 1965 +++++++++-------- librz/arch/isa/arm/asm-arm.h | 1 - librz/arch/isa/x86/common.c | 4 +- librz/arch/p/analysis/analysis_arm_cs.c | 742 ++++--- librz/arch/p/analysis/analysis_mips_cs.c | 66 +- librz/arch/p/analysis/analysis_sysz.c | 33 +- librz/arch/p/asm/asm_arm_cs.c | 5 +- librz/arch/p/asm/asm_sysz.c | 2 + librz/arch/p/asm/cs_helper.h | 3 + meson_options.txt | 2 +- subprojects/capstone-next.wrap | 2 +- subprojects/capstone-v6.wrap | 6 + .../meson.build | 23 +- .../packagefiles/capstone-next/meson.build | 3 +- test/db/analysis/arm64 | 4 +- test/db/analysis/mips | 14 +- test/db/analysis/sparc | 111 +- test/db/analysis/sysz | 4 +- test/db/analysis/tricore | 3 + test/db/asm/arm_64 | 4 +- test/db/asm/mips_64 | 64 +- test/db/asm/mips_v2_64 | 4 +- test/db/asm/tricore | 50 +- test/db/cmd/cmd_pd | 1 + test/db/cmd/cmd_pde | 1 + test/db/esil/mips_32 | 15 + test/db/formats/elf/m68k | 9 + test/db/formats/elf/mips | 3 + 37 files changed, 1909 insertions(+), 1870 deletions(-) delete mode 100644 librz/arch/isa/arm/aarch64_meta_macros.h create mode 100644 subprojects/capstone-v6.wrap rename subprojects/packagefiles/{capstone-auto-sync-aarch64 => capstone-6.0.0-alpha1}/meson.build (83%) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index f3337e7efbc..fa41cddc5a1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -160,6 +160,16 @@ jobs: timeout: 45 cflags: "-Wno-cpp" allow_failure: true + - name: capstone-v6 + os: ubuntu-22.04 + build_system: meson + compiler: gcc + meson_options: -Dbuildtype=release -Duse_capstone_version=v6 --werror + run_tests: false + enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }} + timeout: 45 + cflags: "-Wno-cpp" + allow_failure: false - name: no-gpl-code os: ubuntu-22.04 build_system: meson diff --git a/doc/PACKAGERS.md b/doc/PACKAGERS.md index fa3dca038ff..b3948f84953 100644 --- a/doc/PACKAGERS.md +++ b/doc/PACKAGERS.md @@ -66,7 +66,7 @@ version of Capstone be dynamically linked at runtime. To do this, use the `-Duse_sys_capstone=enabled` command line option when running `meson`. You can override the version of Capstone Rizin will use by setting -`use_capstone_version` to one of `v4`, `v5` or `next`. +`use_capstone_version` to one of `v4`, `v5`, `v6` or `next`. There are more bundled dependencies that can be swapped out for system versions. At the time of writing, these are: diff --git a/librz/arch/isa/arm/aarch64_meta_macros.h b/librz/arch/isa/arm/aarch64_meta_macros.h deleted file mode 100644 index 540f07a42b7..00000000000 --- a/librz/arch/isa/arm/aarch64_meta_macros.h +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-FileCopyrightText: 2023 Rot127 -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef AARCH64_META_MACROS_H -#define AARCH64_META_MACROS_H - -#ifdef USE_SYS_CAPSTONE - -/// Macro for meta programming. -/// Meant for projects using Capstone and need to support multiple -/// versions of it. -/// These macros replace several instances of the old "ARM64" with -/// the new "AArch64" name depending on the CS version. -#if CS_NEXT_VERSION < 6 -#define CS_AARCH64(x) ARM64##x -#else -#define CS_AARCH64(x) AArch64##x -#endif - -#if CS_NEXT_VERSION < 6 -#define CS_AARCH64pre(x) x##ARM64 -#else -#define CS_AARCH64pre(x) x##AARCH64 -#endif - -#if CS_NEXT_VERSION < 6 -#define CS_AARCH64CC(x) ARM64_CC##x -#else -#define CS_AARCH64CC(x) AArch64CC##x -#endif - -#if CS_NEXT_VERSION < 6 -#define CS_AARCH64_VL_(x) ARM64_VAS_##x -#else -#define CS_AARCH64_VL_(x) AArch64Layout_VL_##x -#endif - -#if CS_NEXT_VERSION < 6 -#define CS_aarch64_ arm64 -#else -#define CS_aarch64_ aarch64 -#endif - -#if CS_NEXT_VERSION < 6 -#define CS_aarch64(x) arm64##x -#else -#define CS_aarch64(x) aarch64##x -#endif - -#if CS_NEXT_VERSION < 6 -#define CS_aarch64_op() cs_arm64_op -#define CS_aarch64_reg() arm64_reg -#define CS_aarch64_cc() arm64_cc -#define CS_cs_aarch64() cs_arm64 -#define CS_aarch64_extender() arm64_extender -#define CS_aarch64_shifter() arm64_shifter -#define CS_aarch64_vas() arm64_vas -#else -#define CS_aarch64_op() cs_aarch64_op -#define CS_aarch64_reg() aarch64_reg -#define CS_aarch64_cc() AArch64CC_CondCode -#define CS_cs_aarch64() cs_aarch64 -#define CS_aarch64_extender() aarch64_extender -#define CS_aarch64_shifter() aarch64_shifter -#define CS_aarch64_vas() AArch64Layout_VectorLayout -#endif - -#endif // USE_SYS_CAPSTONE -#endif // AARCH64_META_MACROS_H diff --git a/librz/arch/isa/arm/arm_accessors32.h b/librz/arch/isa/arm/arm_accessors32.h index 5ded7f07e28..8aaed8616fd 100644 --- a/librz/arch/isa/arm/arm_accessors32.h +++ b/librz/arch/isa/arm/arm_accessors32.h @@ -7,6 +7,9 @@ * cs_insn *insn */ +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #define REGID(x) insn->detail->arm.operands[x].reg @@ -27,14 +30,24 @@ #define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM) #define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP) -#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift -#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL -#define OPCOUNT() insn->detail->arm.op_count -#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0) -#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type +#if CS_NEXT_VERSION < 6 +#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift +#else +#define LSHIFT(x) insn->detail->arm.operands[x].shift.value +#endif +#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL +#define OPCOUNT() insn->detail->arm.op_count +#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0) +#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type + +#if CS_NEXT_VERSION < 6 #define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \ SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG || \ SHIFTTYPE(x) == ARM_SFT_RRX_REG) +#else +#define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \ + SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG) +#endif #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value #if CS_NEXT_VERSION >= 6 diff --git a/librz/arch/isa/arm/arm_accessors64.h b/librz/arch/isa/arm/arm_accessors64.h index 4d8b765679d..1b063f9d402 100644 --- a/librz/arch/isa/arm/arm_accessors64.h +++ b/librz/arch/isa/arm/arm_accessors64.h @@ -7,22 +7,23 @@ * cs_insn *insn */ +#define CAPSTONE_AARCH64_COMPAT_HEADER #include -#define IMM64(x) (ut64)(insn->detail->CS_aarch64_.operands[x].imm) -#define INSOP64(x) insn->detail->CS_aarch64_.operands[x] +#define IMM64(x) (ut64)(insn->detail->arm64.operands[x].imm) +#define INSOP64(x) insn->detail->arm64.operands[x] -#define REGID64(x) insn->detail->CS_aarch64_.operands[x].reg -#define REGBASE64(x) insn->detail->CS_aarch64_.operands[x].mem.base +#define REGID64(x) insn->detail->arm64.operands[x].reg +#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base // s/index/base|reg/ -#define HASMEMINDEX64(x) (insn->detail->CS_aarch64_.operands[x].mem.index != CS_AARCH64(_REG_INVALID)) -#define MEMDISP64(x) (ut64) insn->detail->CS_aarch64_.operands[x].mem.disp -#define ISIMM64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_IMM)) -#define ISREG64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_REG)) -#define ISMEM64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_MEM)) +#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID) +#define MEMDISP64(x) (ut64) insn->detail->arm64.operands[x].mem.disp +#define ISIMM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_IMM) +#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG) +#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM) -#define LSHIFT2_64(x) insn->detail->CS_aarch64_.operands[x].shift.value -#define OPCOUNT64() insn->detail->CS_aarch64_.op_count +#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value +#define OPCOUNT64() insn->detail->arm64.op_count #if CS_NEXT_VERSION < 6 #define ISWRITEBACK64() (insn->detail->arm64.writeback == true) @@ -33,6 +34,6 @@ #define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64()))) #define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64()))) #else -#define ISPREINDEX64() (!insn->detail->CS_aarch64_.post_index && ISWRITEBACK64()) -#define ISPOSTINDEX64() (insn->detail->CS_aarch64_.post_index && ISWRITEBACK64()) -#endif \ No newline at end of file +#define ISPREINDEX64() (!insn->detail->arm64.post_index && ISWRITEBACK64()) +#define ISPOSTINDEX64() (insn->detail->arm64.post_index && ISWRITEBACK64()) +#endif diff --git a/librz/arch/isa/arm/arm_cs.h b/librz/arch/isa/arm/arm_cs.h index a2c55eb8f86..5b1f8549169 100644 --- a/librz/arch/isa/arm/arm_cs.h +++ b/librz/arch/isa/arm/arm_cs.h @@ -5,8 +5,10 @@ #define RZ_ARM_CS_H #include +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include -#include "aarch64_meta_macros.h" RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb); RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn); @@ -19,7 +21,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode #else RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type); #endif -RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type); +RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type); RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb); RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian); diff --git a/librz/arch/isa/arm/arm_esil32.c b/librz/arch/isa/arm/arm_esil32.c index f7f931d311a..87f08cb0632 100644 --- a/librz/arch/isa/arm/arm_esil32.c +++ b/librz/arch/isa/arm/arm_esil32.c @@ -2,6 +2,9 @@ // SPDX-License-Identifier: LGPL-3.0-only #include +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #include "arm_cs.h" @@ -34,7 +37,9 @@ static const char *decode_shift(arm_shifter shift) { case ARM_SFT_ROR: case ARM_SFT_RRX: case ARM_SFT_ROR_REG: +#if CS_NEXT_VERSION < 6 case ARM_SFT_RRX_REG: +#endif return E_OP_RR; default: diff --git a/librz/arch/isa/arm/arm_esil64.c b/librz/arch/isa/arm/arm_esil64.c index b76c1273a6e..4c620ea2343 100644 --- a/librz/arch/isa/arm/arm_esil64.c +++ b/librz/arch/isa/arm/arm_esil64.c @@ -2,80 +2,84 @@ // SPDX-License-Identifier: LGPL-3.0-only #include + +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #include "arm_cs.h" #include "arm_accessors64.h" -#define REG64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->CS_aarch64_.operands[x].reg)) -#define MEMBASE64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->CS_aarch64_.operands[x].mem.base)) -#define MEMINDEX64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->CS_aarch64_.operands[x].mem.index)) +#define REG64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].reg)) +#define MEMBASE64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.base)) +#define MEMINDEX64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.index)) -RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type) { +RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type) { const char *close_cond[2]; close_cond[0] = ""; close_cond[1] = ",}"; int close_type = 0; switch (cond_type) { - case CS_AARCH64CC(_EQ): + case ARM64CC_EQ: close_type = 1; rz_strbuf_setf(&op->esil, "zf,?{,"); break; - case CS_AARCH64CC(_NE): + case ARM64CC_NE: close_type = 1; rz_strbuf_setf(&op->esil, "zf,!,?{,"); break; - case CS_AARCH64CC(_HS): + case ARM64CC_HS: close_type = 1; rz_strbuf_setf(&op->esil, "cf,?{,"); break; - case CS_AARCH64CC(_LO): + case ARM64CC_LO: close_type = 1; rz_strbuf_setf(&op->esil, "cf,!,?{,"); break; - case CS_AARCH64CC(_MI): + case ARM64CC_MI: close_type = 1; rz_strbuf_setf(&op->esil, "nf,?{,"); break; - case CS_AARCH64CC(_PL): + case ARM64CC_PL: close_type = 1; rz_strbuf_setf(&op->esil, "nf,!,?{,"); break; - case CS_AARCH64CC(_VS): + case ARM64CC_VS: close_type = 1; rz_strbuf_setf(&op->esil, "vf,?{,"); break; - case CS_AARCH64CC(_VC): + case ARM64CC_VC: close_type = 1; rz_strbuf_setf(&op->esil, "vf,!,?{,"); break; - case CS_AARCH64CC(_HI): + case ARM64CC_HI: close_type = 1; rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,"); break; - case CS_AARCH64CC(_LS): + case ARM64CC_LS: close_type = 1; rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,"); break; - case CS_AARCH64CC(_GE): + case ARM64CC_GE: close_type = 1; rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,"); break; - case CS_AARCH64CC(_LT): + case ARM64CC_LT: close_type = 1; rz_strbuf_setf(&op->esil, "nf,vf,^,?{,"); break; - case CS_AARCH64CC(_GT): + case ARM64CC_GT: // zf == 0 && nf == vf close_type = 1; rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,"); break; - case CS_AARCH64CC(_LE): + case ARM64CC_LE: // zf == 1 || nf != vf close_type = 1; rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,"); break; - case CS_AARCH64CC(_AL): + case ARM64CC_AL: // always executed break; default: @@ -86,37 +90,37 @@ RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc( static int arm64_reg_width(int reg) { switch (reg) { - case CS_AARCH64(_REG_W0): - case CS_AARCH64(_REG_W1): - case CS_AARCH64(_REG_W2): - case CS_AARCH64(_REG_W3): - case CS_AARCH64(_REG_W4): - case CS_AARCH64(_REG_W5): - case CS_AARCH64(_REG_W6): - case CS_AARCH64(_REG_W7): - case CS_AARCH64(_REG_W8): - case CS_AARCH64(_REG_W9): - case CS_AARCH64(_REG_W10): - case CS_AARCH64(_REG_W11): - case CS_AARCH64(_REG_W12): - case CS_AARCH64(_REG_W13): - case CS_AARCH64(_REG_W14): - case CS_AARCH64(_REG_W15): - case CS_AARCH64(_REG_W16): - case CS_AARCH64(_REG_W17): - case CS_AARCH64(_REG_W18): - case CS_AARCH64(_REG_W19): - case CS_AARCH64(_REG_W20): - case CS_AARCH64(_REG_W21): - case CS_AARCH64(_REG_W22): - case CS_AARCH64(_REG_W23): - case CS_AARCH64(_REG_W24): - case CS_AARCH64(_REG_W25): - case CS_AARCH64(_REG_W26): - case CS_AARCH64(_REG_W27): - case CS_AARCH64(_REG_W28): - case CS_AARCH64(_REG_W29): - case CS_AARCH64(_REG_W30): + case ARM64_REG_W0: + case ARM64_REG_W1: + case ARM64_REG_W2: + case ARM64_REG_W3: + case ARM64_REG_W4: + case ARM64_REG_W5: + case ARM64_REG_W6: + case ARM64_REG_W7: + case ARM64_REG_W8: + case ARM64_REG_W9: + case ARM64_REG_W10: + case ARM64_REG_W11: + case ARM64_REG_W12: + case ARM64_REG_W13: + case ARM64_REG_W14: + case ARM64_REG_W15: + case ARM64_REG_W16: + case ARM64_REG_W17: + case ARM64_REG_W18: + case ARM64_REG_W19: + case ARM64_REG_W20: + case ARM64_REG_W21: + case ARM64_REG_W22: + case ARM64_REG_W23: + case ARM64_REG_W24: + case ARM64_REG_W25: + case ARM64_REG_W26: + case ARM64_REG_W27: + case ARM64_REG_W28: + case ARM64_REG_W29: + case ARM64_REG_W30: return 32; break; default: @@ -125,20 +129,20 @@ static int arm64_reg_width(int reg) { return 64; } -static int decode_sign_ext(CS_aarch64_extender() extender) { +static int decode_sign_ext(aarch64_extender extender) { switch (extender) { - case CS_AARCH64(_EXT_UXTB): - case CS_AARCH64(_EXT_UXTH): - case CS_AARCH64(_EXT_UXTW): - case CS_AARCH64(_EXT_UXTX): + case ARM64_EXT_UXTB: + case ARM64_EXT_UXTH: + case ARM64_EXT_UXTW: + case ARM64_EXT_UXTX: return 0; // nothing needs to be done for unsigned - case CS_AARCH64(_EXT_SXTB): + case ARM64_EXT_SXTB: return 8; - case CS_AARCH64(_EXT_SXTH): + case ARM64_EXT_SXTH: return 16; - case CS_AARCH64(_EXT_SXTW): + case ARM64_EXT_SXTW: return 32; - case CS_AARCH64(_EXT_SXTX): + case ARM64_EXT_SXTX: return 64; default: break; @@ -147,24 +151,24 @@ static int decode_sign_ext(CS_aarch64_extender() extender) { return 0; } -#define EXT64(x) decode_sign_ext(insn->detail->CS_aarch64_.operands[x].ext) +#define EXT64(x) decode_sign_ext(insn->detail->arm64.operands[x].ext) -static const char *decode_shift_64(CS_aarch64_shifter() shift) { +static const char *decode_shift_64(aarch64_shifter shift) { const char *E_OP_SR = ">>"; const char *E_OP_SL = "<<"; const char *E_OP_RR = ">>>"; const char *E_OP_VOID = ""; switch (shift) { - case CS_AARCH64(_SFT_ASR): - case CS_AARCH64(_SFT_LSR): + case ARM64_SFT_ASR: + case ARM64_SFT_LSR: return E_OP_SR; - case CS_AARCH64(_SFT_LSL): - case CS_AARCH64(_SFT_MSL): + case ARM64_SFT_LSL: + case ARM64_SFT_MSL: return E_OP_SL; - case CS_AARCH64(_SFT_ROR): + case ARM64_SFT_ROR: return E_OP_RR; default: @@ -173,22 +177,22 @@ static const char *decode_shift_64(CS_aarch64_shifter() shift) { return E_OP_VOID; } -#define DECODE_SHIFT64(x) decode_shift_64(insn->detail->CS_aarch64_.operands[x].shift.type) +#define DECODE_SHIFT64(x) decode_shift_64(insn->detail->arm64.operands[x].shift.type) static int regsize64(cs_insn *insn, int n) { - unsigned int reg = insn->detail->CS_aarch64_.operands[n].reg; - if ((reg >= CS_AARCH64(_REG_S0) && reg <= CS_AARCH64(_REG_S31)) || - (reg >= CS_AARCH64(_REG_W0) && reg <= CS_AARCH64(_REG_W30)) || - reg == CS_AARCH64(_REG_WZR)) { + unsigned int reg = insn->detail->arm64.operands[n].reg; + if ((reg >= ARM64_REG_S0 && reg <= ARM64_REG_S31) || + (reg >= ARM64_REG_W0 && reg <= ARM64_REG_W30) || + reg == ARM64_REG_WZR) { return 4; } - if (reg >= CS_AARCH64(_REG_B0) && reg <= CS_AARCH64(_REG_B31)) { + if (reg >= ARM64_REG_B0 && reg <= ARM64_REG_B31) { return 1; } - if (reg >= CS_AARCH64(_REG_H0) && reg <= CS_AARCH64(_REG_H31)) { + if (reg >= ARM64_REG_H0 && reg <= ARM64_REG_H31) { return 2; } - if (reg >= CS_AARCH64(_REG_Q0) && reg <= CS_AARCH64(_REG_Q31)) { + if (reg >= ARM64_REG_Q0 && reg <= ARM64_REG_Q31) { return 16; } return 8; @@ -210,7 +214,7 @@ static void shifted_reg64_append(RzStrBuf *sb, csh *handle, cs_insn *insn, int n } if (LSHIFT2_64(n)) { - if (insn->detail->CS_aarch64_.operands[n].shift.type != CS_AARCH64(_SFT_ASR)) { + if (insn->detail->arm64.operands[n].shift.type != ARM64_SFT_ASR) { if (signext) { rz_strbuf_appendf(sb, "%d,%d,%s,~,%s", LSHIFT2_64(n), signext, rn, DECODE_SHIFT64(n)); } else { @@ -294,12 +298,12 @@ static void bfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) { switch (insn->alias_id) { default: return; - case AArch64_INS_ALIAS_BFI: // bfi w8, w8, 2, 1 + case AARCH64_INS_ALIAS_BFI: // bfi w8, w8, 2, 1 width += 1; // TODO Mod depends on (sf && N) bits lsb = -lsb % 32; break; - case AArch64_INS_ALIAS_BFXIL: + case AARCH64_INS_ALIAS_BFXIL: width = width - lsb + 1; break; } @@ -314,25 +318,25 @@ static void bfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) { static void subfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) { ut64 lsb = IMM64(2); ut64 width = IMM64(3); - if (insn->alias_id == AArch64_INS_ALIAS_SBFIZ) { + if (insn->alias_id == AARCH64_INS_ALIAS_SBFIZ) { width += 1; lsb = -lsb % 64; rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=", lsb, IMM64(3), REG64(1), rz_num_bitmask((ut8)width), REG64(0)); - } else if (insn->alias_id == AArch64_INS_ALIAS_UBFIZ) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_UBFIZ) { width += 1; lsb = -lsb % 64; rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=", lsb, REG64(1), rz_num_bitmask((ut8)width), REG64(0)); - } else if (insn->alias_id == AArch64_INS_ALIAS_SBFX) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_SBFX) { width = width - lsb + 1; rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=", IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); - } else if (insn->alias_id == AArch64_INS_ALIAS_UBFX) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_UBFX) { width = width - lsb + 1; rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=", lsb, REG64(1), lsb, rz_num_bitmask((ut8)width), REG64(0)); - } else if (insn->alias_id == AArch64_INS_ALIAS_LSL) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_LSL) { // imms != 0x1f => mod 32 // imms != 0x3f => mod 64 ut32 m = IMM64(3) != 0x1f ? 32 : 64; @@ -352,7 +356,7 @@ static void subfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) { ut64 i2 = IMM64(2) % m; rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,<<,%s,=", i2 % (ut64)size, r1, r0); } - } else if (insn->alias_id == AArch64_INS_ALIAS_LSR) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_LSR) { const char *r0 = REG64(0); const char *r1 = REG64(1); const int size = REGSIZE64(0) * 8; @@ -369,7 +373,7 @@ static void subfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) { ut64 i2 = IMM64(2); rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,>>,%s,=", i2 % (ut64)size, r1, r0); } - } else if (insn->alias_id == AArch64_INS_ALIAS_ASR) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_ASR) { const char *r0 = REG64(0); const char *r1 = REG64(1); const int size = REGSIZE64(0) * 8; @@ -397,10 +401,10 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_init(&op->esil); rz_strbuf_set(&op->esil, ""); - postfix = rz_arm64_cs_esil_prefix_cond(op, insn->detail->CS_aarch64_.cc); + postfix = rz_arm64_cs_esil_prefix_cond(op, insn->detail->arm64.cc); switch (insn->id) { - case CS_AARCH64(_INS_REV): + case ARM64_INS_REV: // these REV* instructions were almost right, except in the cases like rev x0, x0 // where the use of |= caused copies of the value to be erroneously present { @@ -441,7 +445,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_REV32): { + case ARM64_INS_REV32: { const char *r0 = REG64(0); const char *r1 = REG64(1); rz_strbuf_setf(&op->esil, @@ -452,7 +456,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a r1, r1, r1, r1, r0); break; } - case CS_AARCH64(_INS_REV16): { + case ARM64_INS_REV16: { const char *r0 = REG64(0); const char *r1 = REG64(1); rz_strbuf_setf(&op->esil, @@ -461,71 +465,71 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a r1, r1, r0); break; } - case CS_AARCH64(_INS_ADR): + case ARM64_INS_ADR: // TODO: must be 21bit signed rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,=", IMM64(1), REG64(0)); break; - case CS_AARCH64(_INS_SMADDL): { + case ARM64_INS_SMADDL: { int size = REGSIZE64(1) * 8; rz_strbuf_setf(&op->esil, "%d,%s,~,%d,%s,~,*,%s,+,%s,=", size, REG64(2), size, REG64(1), REG64(3), REG64(0)); break; } - case CS_AARCH64(_INS_UMADDL): - case CS_AARCH64(_INS_FMADD): - case CS_AARCH64(_INS_MADD): + case ARM64_INS_UMADDL: + case ARM64_INS_FMADD: + case ARM64_INS_MADD: rz_strbuf_setf(&op->esil, "%s,%s,*,%s,+,%s,=", REG64(2), REG64(1), REG64(3), REG64(0)); break; - case CS_AARCH64(_INS_MSUB): + case ARM64_INS_MSUB: rz_strbuf_setf(&op->esil, "%s,%s,*,%s,-,%s,=", REG64(2), REG64(1), REG64(3), REG64(0)); break; #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_MNEG): + case ARM64_INS_MNEG: rz_strbuf_setf(&op->esil, "%s,%s,*,0,-,%s,=", REG64(2), REG64(1), REG64(0)); break; #endif - case CS_AARCH64(_INS_ADD): - case CS_AARCH64(_INS_ADC): // Add with carry. - // case CS_AARCH64(_INS_ADCS): // Add with carry. + case ARM64_INS_ADD: + case ARM64_INS_ADC: // Add with carry. + // case ARM64_INS_ADCS: // Add with carry. OPCALL("+"); break; - case CS_AARCH64(_INS_SUB): + case ARM64_INS_SUB: OPCALL("-"); break; - case CS_AARCH64(_INS_SBC): + case ARM64_INS_SBC: // TODO have to check this more, VEX does not work rz_strbuf_setf(&op->esil, "%s,cf,+,%s,-,%s,=", REG64(2), REG64(1), REG64(0)); break; - case CS_AARCH64(_INS_SMULL): { + case ARM64_INS_SMULL: { int size = REGSIZE64(1) * 8; rz_strbuf_setf(&op->esil, "%d,%s,~,%d,%s,~,*,%s,=", size, REG64(2), size, REG64(1), REG64(0)); break; } - case CS_AARCH64(_INS_MUL): + case ARM64_INS_MUL: OPCALL("*"); break; - case CS_AARCH64(_INS_AND): + case ARM64_INS_AND: OPCALL("&"); break; - case CS_AARCH64(_INS_ORR): + case ARM64_INS_ORR: OPCALL("|"); break; - case CS_AARCH64(_INS_EOR): + case ARM64_INS_EOR: OPCALL("^"); break; - case CS_AARCH64(_INS_ORN): + case ARM64_INS_ORN: OPCALL_NEG("|"); break; - case CS_AARCH64(_INS_EON): + case ARM64_INS_EON: OPCALL_NEG("^"); break; - case CS_AARCH64(_INS_LSR): { + case ARM64_INS_LSR: { const char *r0 = REG64(0); const char *r1 = REG64(1); const int size = REGSIZE64(0) * 8; @@ -544,7 +548,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_LSL): { + case ARM64_INS_LSL: { const char *r0 = REG64(0); const char *r1 = REG64(1); const int size = REGSIZE64(0) * 8; @@ -563,18 +567,18 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_ROR): + case ARM64_INS_ROR: OPCALL(">>>"); break; - case CS_AARCH64(_INS_HINT): + case ARM64_INS_HINT: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_NOP): + case ARM64_INS_NOP: rz_strbuf_setf(&op->esil, ","); break; #endif - case CS_AARCH64(_INS_FDIV): + case ARM64_INS_FDIV: break; - case CS_AARCH64(_INS_SDIV): { + case ARM64_INS_SDIV: { /* TODO: support WZR XZR to specify 32, 64bit op */ int size = REGSIZE64(1) * 8; if (ISREG64(2)) { @@ -584,7 +588,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_UDIV): + case ARM64_INS_UDIV: /* TODO: support WZR XZR to specify 32, 64bit op */ if ISREG64 (2) { rz_strbuf_setf(&op->esil, "%s,%s,/,%s,=", REG64(2), REG64(1), REG64(0)); @@ -592,20 +596,20 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_setf(&op->esil, "%s,%s,/=", REG64(1), REG64(0)); } break; - case CS_AARCH64(_INS_BR): + case ARM64_INS_BR: rz_strbuf_setf(&op->esil, "%s,pc,=", REG64(0)); break; - case CS_AARCH64(_INS_B): + case ARM64_INS_B: /* capstone precompute resulting address, using PC + IMM */ rz_strbuf_appendf(&op->esil, "%" PFMT64d ",pc,=", IMM64(0)); break; - case CS_AARCH64(_INS_BL): + case ARM64_INS_BL: rz_strbuf_setf(&op->esil, "pc,lr,=,%" PFMT64d ",pc,=", IMM64(0)); break; - case CS_AARCH64(_INS_BLR): + case ARM64_INS_BLR: rz_strbuf_setf(&op->esil, "pc,lr,=,%s,pc,=", REG64(0)); break; - case CS_AARCH64(_INS_CLZ):; + case ARM64_INS_CLZ:; int size = 8 * REGSIZE64(0); // expression is much more concise with GOTO, but GOTOs should be minimized @@ -652,43 +656,43 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; - case CS_AARCH64(_INS_LDRH): - case CS_AARCH64(_INS_LDUR): - case CS_AARCH64(_INS_LDURB): - case CS_AARCH64(_INS_LDURH): - case CS_AARCH64(_INS_LDR): - // case CS_AARCH64(_INS_LDRSB): - // case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDRB): - // case CS_AARCH64(_INS_LDRSW): - // case CS_AARCH64(_INS_LDURSW): - case CS_AARCH64(_INS_LDXR): - case CS_AARCH64(_INS_LDXRB): - case CS_AARCH64(_INS_LDXRH): - case CS_AARCH64(_INS_LDAXR): - case CS_AARCH64(_INS_LDAXRB): - case CS_AARCH64(_INS_LDAXRH): - case CS_AARCH64(_INS_LDAR): - case CS_AARCH64(_INS_LDARB): - case CS_AARCH64(_INS_LDARH): { + case ARM64_INS_LDRH: + case ARM64_INS_LDUR: + case ARM64_INS_LDURB: + case ARM64_INS_LDURH: + case ARM64_INS_LDR: + // case ARM64_INS_LDRSB: + // case ARM64_INS_LDRSH: + case ARM64_INS_LDRB: + // case ARM64_INS_LDRSW: + // case ARM64_INS_LDURSW: + case ARM64_INS_LDXR: + case ARM64_INS_LDXRB: + case ARM64_INS_LDXRH: + case ARM64_INS_LDAXR: + case ARM64_INS_LDAXRB: + case ARM64_INS_LDAXRH: + case ARM64_INS_LDAR: + case ARM64_INS_LDARB: + case ARM64_INS_LDARH: { int size = REGSIZE64(0); switch (insn->id) { - case CS_AARCH64(_INS_LDRB): - case CS_AARCH64(_INS_LDARB): - case CS_AARCH64(_INS_LDAXRB): - case CS_AARCH64(_INS_LDXRB): - case CS_AARCH64(_INS_LDURB): + case ARM64_INS_LDRB: + case ARM64_INS_LDARB: + case ARM64_INS_LDAXRB: + case ARM64_INS_LDXRB: + case ARM64_INS_LDURB: size = 1; break; - case CS_AARCH64(_INS_LDRH): - case CS_AARCH64(_INS_LDARH): - case CS_AARCH64(_INS_LDXRH): - case CS_AARCH64(_INS_LDAXRH): - case CS_AARCH64(_INS_LDURH): + case ARM64_INS_LDRH: + case ARM64_INS_LDARH: + case ARM64_INS_LDXRH: + case ARM64_INS_LDAXRH: + case ARM64_INS_LDURH: size = 2; break; - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDURSW): + case ARM64_INS_LDRSW: + case ARM64_INS_LDURSW: size = 4; break; default: @@ -713,8 +717,13 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,-", -(st64)MEMDISP64(1), MEMBASE64(1)); } else { - rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,+", - MEMDISP64(1), MEMBASE64(1)); + if (insn->detail->arm64.operands[1].mem.base == 0) { + rz_strbuf_appendf(&op->esil, "%" PFMT64d, + MEMDISP64(1)); + } else { + rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,+", + MEMDISP64(1), MEMBASE64(1)); + } } rz_strbuf_append(&op->esil, ",DUP,tmp,="); @@ -751,7 +760,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a instructions like ldr x16, [x13, x9] ldrb w2, [x19, x23] - are not detected as CS_AARCH64(_OP_MEM) type and + are not detected as ARM64_OP_MEM type and fall in this case instead. */ if (ISREG64(2)) { @@ -766,25 +775,25 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_LDRSB): - case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDURSB): - case CS_AARCH64(_INS_LDURSH): - case CS_AARCH64(_INS_LDURSW): { + case ARM64_INS_LDRSB: + case ARM64_INS_LDRSH: + case ARM64_INS_LDRSW: + case ARM64_INS_LDURSB: + case ARM64_INS_LDURSH: + case ARM64_INS_LDURSW: { // handle the sign extended instrs here int size = REGSIZE64(0); switch (insn->id) { - case CS_AARCH64(_INS_LDRSB): - case CS_AARCH64(_INS_LDURSB): + case ARM64_INS_LDRSB: + case ARM64_INS_LDURSB: size = 1; break; - case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDURSH): + case ARM64_INS_LDRSH: + case ARM64_INS_LDURSH: size = 2; break; - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDURSW): + case ARM64_INS_LDRSW: + case ARM64_INS_LDURSW: size = 4; break; default: @@ -847,7 +856,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a instructions like ldr x16, [x13, x9] ldrb w2, [x19, x23] - are not detected as CS_AARCH64(_OP_MEM) type and + are not detected as ARM64_OP_MEM type and fall in this case instead. */ if (ISREG64(2)) { @@ -862,13 +871,13 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_FCMP): - case CS_AARCH64(_INS_CCMP): - case CS_AARCH64(_INS_CCMN): + case ARM64_INS_FCMP: + case ARM64_INS_CCMP: + case ARM64_INS_CCMN: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_TST): // cmp w8, 0xd - case CS_AARCH64(_INS_CMP): // cmp w8, 0xd - case CS_AARCH64(_INS_CMN): // cmp w8, 0xd + case ARM64_INS_TST: // cmp w8, 0xd + case ARM64_INS_CMP: // cmp w8, 0xd + case ARM64_INS_CMN: // cmp w8, 0xd #endif { // update esil, cpu flags @@ -883,9 +892,9 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a break; } #if CS_NEXT_VERSION >= 6 - case AArch64_INS_SUBS: - if (insn->alias_id != AArch64_INS_ALIAS_CMP && - insn->alias_id != AArch64_INS_ALIAS_CMN) { + case AARCH64_INS_SUBS: + if (insn->alias_id != AARCH64_INS_ALIAS_CMP && + insn->alias_id != AARCH64_INS_ALIAS_CMN) { cmp(op, handle, insn); break; } @@ -900,71 +909,71 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; #endif - case CS_AARCH64(_INS_FCSEL): - case CS_AARCH64(_INS_CSEL): // csel Wd, Wn, Wm --> Wd := (cond) ? Wn : Wm + case ARM64_INS_FCSEL: + case ARM64_INS_CSEL: // csel Wd, Wn, Wm --> Wd := (cond) ? Wn : Wm rz_strbuf_appendf(&op->esil, "%s,}{,%s,},%s,=", REG64(1), REG64(2), REG64(0)); postfix = ""; break; #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CSET): // cset Wd --> Wd := (cond) ? 1 : 0 + case ARM64_INS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0 rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0)); postfix = ""; break; - case CS_AARCH64(_INS_CINC): // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn + case ARM64_INS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0)); postfix = ""; break; - case CS_AARCH64(_INS_CSINC): // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1) + case ARM64_INS_CSINC: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1) rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0)); postfix = ""; break; #else - case CS_AARCH64(_INS_CSINC): + case ARM64_INS_CSINC: switch (insn->alias_id) { default: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1) rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0)); postfix = ""; break; - case AArch64_INS_ALIAS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0 + case AARCH64_INS_ALIAS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0 rz_strbuf_drain_nofree(&op->esil); - rz_arm64_cs_esil_prefix_cond(op, AArch64CC_getInvertedCondCode(insn->detail->CS_aarch64_.cc)); + rz_arm64_cs_esil_prefix_cond(op, AArch64CC_getInvertedCondCode(insn->detail->arm64.cc)); rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0)); postfix = ""; break; - case AArch64_INS_ALIAS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn + case AARCH64_INS_ALIAS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn rz_strbuf_drain_nofree(&op->esil); - rz_arm64_cs_esil_prefix_cond(op, AArch64CC_getInvertedCondCode(insn->detail->CS_aarch64_.cc)); + rz_arm64_cs_esil_prefix_cond(op, AArch64CC_getInvertedCondCode(insn->detail->arm64.cc)); rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0)); postfix = ""; break; } break; #endif - case CS_AARCH64(_INS_STXRB): - case CS_AARCH64(_INS_STXRH): - case CS_AARCH64(_INS_STXR): { + case ARM64_INS_STXRB: + case ARM64_INS_STXRH: + case ARM64_INS_STXR: { int size = REGSIZE64(1); - if (insn->id == CS_AARCH64(_INS_STXRB)) { + if (insn->id == ARM64_INS_STXRB) { size = 1; - } else if (insn->id == CS_AARCH64(_INS_STXRH)) { + } else if (insn->id == ARM64_INS_STXRH) { size = 2; } rz_strbuf_setf(&op->esil, "0,%s,=,%s,%s,%" PFMT64d ",+,=[%d]", REG64(0), REG64(1), MEMBASE64(1), MEMDISP64(1), size); break; } - case CS_AARCH64(_INS_STRB): - case CS_AARCH64(_INS_STRH): - case CS_AARCH64(_INS_STUR): - case CS_AARCH64(_INS_STURB): - case CS_AARCH64(_INS_STURH): - case CS_AARCH64(_INS_STR): // str x6, [x6,0xf90] + case ARM64_INS_STRB: + case ARM64_INS_STRH: + case ARM64_INS_STUR: + case ARM64_INS_STURB: + case ARM64_INS_STURH: + case ARM64_INS_STR: // str x6, [x6,0xf90] { int size = REGSIZE64(0); - if (insn->id == CS_AARCH64(_INS_STRB) || insn->id == CS_AARCH64(_INS_STURB)) { + if (insn->id == ARM64_INS_STRB || insn->id == ARM64_INS_STURB) { size = 1; - } else if (insn->id == CS_AARCH64(_INS_STRH) || insn->id == CS_AARCH64(_INS_STURH)) { + } else if (insn->id == ARM64_INS_STRH || insn->id == ARM64_INS_STURH) { size = 2; } if (ISMEM64(1)) { @@ -1023,7 +1032,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a instructions like ldr x16, [x13, x9] ldrb w2, [x19, x23] - are not detected as CS_AARCH64(_OP_MEM) type and + are not detected as ARM64_OP_MEM type and fall in this case instead. */ if (ISREG64(2)) { @@ -1038,7 +1047,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_BIC): + case ARM64_INS_BIC: if (OPCOUNT64() == 2) { if (REGSIZE64(0) == 4) { rz_strbuf_appendf(&op->esil, "%s,0xffffffff,^,%s,&=", REG64(1), REG64(0)); @@ -1057,28 +1066,28 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } } break; - case CS_AARCH64(_INS_CBZ): + case ARM64_INS_CBZ: rz_strbuf_setf(&op->esil, "%s,!,?{,%" PFMT64d ",pc,=,}", REG64(0), IMM64(1)); break; - case CS_AARCH64(_INS_CBNZ): + case ARM64_INS_CBNZ: rz_strbuf_setf(&op->esil, "%s,?{,%" PFMT64d ",pc,=,}", REG64(0), IMM64(1)); break; - case CS_AARCH64(_INS_TBZ): + case ARM64_INS_TBZ: // tbnz x0, 4, label // if ((1<<4) & x0) goto label; rz_strbuf_setf(&op->esil, "%" PFMT64d ",1,<<,%s,&,!,?{,%" PFMT64d ",pc,=,}", IMM64(1), REG64(0), IMM64(2)); break; - case CS_AARCH64(_INS_TBNZ): + case ARM64_INS_TBNZ: // tbnz x0, 4, label // if ((1<<4) & x0) goto label; rz_strbuf_setf(&op->esil, "%" PFMT64d ",1,<<,%s,&,?{,%" PFMT64d ",pc,=,}", IMM64(1), REG64(0), IMM64(2)); break; - case CS_AARCH64(_INS_STNP): - case CS_AARCH64(_INS_STP): // stp x6, x7, [x6,0xf90] + case ARM64_INS_STNP: + case ARM64_INS_STP: // stp x6, x7, [x6,0xf90] { int disp = (int)MEMDISP64(2); char sign = disp >= 0 ? '+' : '-'; @@ -1118,7 +1127,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a REG64(1), MEMBASE64(2), abs, sign, size, size); } } break; - case CS_AARCH64(_INS_LDP): // ldp x29, x30, [sp], 0x10 + case ARM64_INS_LDP: // ldp x29, x30, [sp], 0x10 { int disp = (int)MEMDISP64(2); char sign = disp >= 0 ? '+' : '-'; @@ -1162,18 +1171,18 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a size, abs, MEMBASE64(2), sign, size, REG64(1)); } } break; - case CS_AARCH64(_INS_ADRP): + case ARM64_INS_ADRP: rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,=", IMM64(1), REG64(0)); break; - case CS_AARCH64(_INS_MOV): + case ARM64_INS_MOV: if (ISREG64(1)) { rz_strbuf_setf(&op->esil, "%s,%s,=", REG64(1), REG64(0)); } else { rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,=", IMM64(1), REG64(0)); } break; - case CS_AARCH64(_INS_EXTR): + case ARM64_INS_EXTR: // from VEX /* 01 | t0 = GET:I64(x4) @@ -1186,23 +1195,23 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,>>,%" PFMT64d ",%s,<<,|,%s,=", IMM64(3), REG64(2), IMM64(3), REG64(1), REG64(0)); break; - case CS_AARCH64(_INS_RBIT): + case ARM64_INS_RBIT: // this expression reverses the bits. it does. do not scroll right. // Derived from VEX rz_strbuf_setf(&op->esil, "0xffffffff00000000,0x20,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x20,0xffffffff00000000,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,%2$s,=", REG64(1), REG64(0)); break; #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_MVN): + case ARM64_INS_MVN: #endif - case CS_AARCH64(_INS_MOVN): + case ARM64_INS_MOVN: if (ISREG64(1)) { rz_strbuf_setf(&op->esil, "%d,%s,-1,^,<<,%s,=", LSHIFT2_64(1), REG64(1), REG64(0)); } else { rz_strbuf_setf(&op->esil, "%d,%" PFMT64d ",<<,-1,^,%s,=", LSHIFT2_64(1), IMM64(1), REG64(0)); } break; - case CS_AARCH64(_INS_MOVK): // movk w8, 0x1290 + case ARM64_INS_MOVK: // movk w8, 0x1290 { ut64 shift = LSHIFT2_64(1); if (shift < 0) { @@ -1221,13 +1230,13 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a break; } - case CS_AARCH64(_INS_MOVZ): + case ARM64_INS_MOVZ: rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,=", IMM64(1) << LSHIFT2_64(1), REG64(0)); break; /* ASR, SXTB, SXTH and SXTW are alias for SBFM */ - case CS_AARCH64(_INS_ASR): { + case ARM64_INS_ASR: { // OPCALL(">>>>"); const char *r0 = REG64(0); const char *r1 = REG64(1); @@ -1247,7 +1256,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_SXTB): + case ARM64_INS_SXTB: if (arm64_reg_width(REGID64(0)) == 32) { rz_strbuf_setf(&op->esil, "0xffffffff,8,0xff,%s,&,~,&,%s,=", REG64(1), REG64(0)); @@ -1256,7 +1265,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a REG64(1), REG64(0)); } break; - case CS_AARCH64(_INS_SXTH): /* halfword */ + case ARM64_INS_SXTH: /* halfword */ if (arm64_reg_width(REGID64(0)) == 32) { rz_strbuf_setf(&op->esil, "0xffffffff,16,0xffff,%s,&,~,&,%s,=", REG64(1), REG64(0)); @@ -1265,28 +1274,28 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a REG64(1), REG64(0)); } break; - case CS_AARCH64(_INS_SXTW): /* word */ + case ARM64_INS_SXTW: /* word */ rz_strbuf_setf(&op->esil, "32,0xffffffff,%s,&,~,%s,=", REG64(1), REG64(0)); break; - case CS_AARCH64(_INS_UXTB): + case ARM64_INS_UXTB: rz_strbuf_setf(&op->esil, "%s,0xff,&,%s,=", REG64(1), REG64(0)); break; - case CS_AARCH64(_INS_UMULL): + case ARM64_INS_UMULL: rz_strbuf_setf(&op->esil, "%s,%s,*,%s,=", REG64(1), REG64(2), REG64(0)); break; - case CS_AARCH64(_INS_UXTH): + case ARM64_INS_UXTH: rz_strbuf_setf(&op->esil, "%s,0xffff,&,%s,=", REG64(1), REG64(0)); break; - case CS_AARCH64(_INS_RET): + case ARM64_INS_RET: rz_strbuf_setf(&op->esil, "lr,pc,="); break; - case CS_AARCH64(_INS_ERET): + case ARM64_INS_ERET: rz_strbuf_setf(&op->esil, "lr,pc,="); break; #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_BFI): // bfi w8, w8, 2, 1 - case CS_AARCH64(_INS_BFXIL): { + case ARM64_INS_BFI: // bfi w8, w8, 2, 1 + case ARM64_INS_BFXIL: { if (OPCOUNT64() >= 3 && ISIMM64(3) && IMM64(3) > 0) { ut64 mask = rz_num_bitmask((ut8)IMM64(3)); ut64 shift = IMM64(2); @@ -1297,42 +1306,42 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } break; } - case CS_AARCH64(_INS_SBFIZ): + case ARM64_INS_SBFIZ: if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=", IMM64(2), IMM64(3), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); } break; - case CS_AARCH64(_INS_UBFIZ): + case ARM64_INS_UBFIZ: if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=", IMM64(2), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); } break; - case CS_AARCH64(_INS_SBFX): + case ARM64_INS_SBFX: if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=", IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); } break; - case CS_AARCH64(_INS_UBFX): + case ARM64_INS_UBFX: if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) { rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=", IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0)); } break; #else - case AArch64_INS_BFM: + case AARCH64_INS_BFM: bfm(op, handle, insn); break; - case AArch64_INS_UBFM: - case AArch64_INS_SBFM: + case AARCH64_INS_UBFM: + case AARCH64_INS_SBFM: subfm(op, handle, insn); break; #endif - case CS_AARCH64(_INS_NEG): + case ARM64_INS_NEG: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_NEGS): + case ARM64_INS_NEGS: #endif if (LSHIFT2_64(1)) { SHIFTED_REG64_APPEND(&op->esil, 1); @@ -1341,7 +1350,7 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a } rz_strbuf_appendf(&op->esil, ",0,-,%s,=", REG64(0)); break; - case CS_AARCH64(_INS_SVC): + case ARM64_INS_SVC: rz_strbuf_setf(&op->esil, "%" PFMT64u ",$", IMM64(0)); break; } diff --git a/librz/arch/isa/arm/arm_il32.c b/librz/arch/isa/arm/arm_il32.c index d9626787be4..58c50a438ee 100644 --- a/librz/arch/isa/arm/arm_il32.c +++ b/librz/arch/isa/arm/arm_il32.c @@ -3,6 +3,10 @@ #include #include + +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #include "arm_cs.h" @@ -348,7 +352,9 @@ static bool is_reg_shift(arm_shifter type) { case ARM_SFT_LSL_REG: case ARM_SFT_LSR_REG: case ARM_SFT_ROR_REG: +#if CS_NEXT_VERSION < 6 case ARM_SFT_RRX_REG: +#endif return true; default: return false; @@ -401,7 +407,9 @@ shift(RzILOpBitVector *val, RZ_NULLABLE RzILOpBool **carry_out, arm_shifter type SHIFTR0(val, dist), SHIFTL0(DUP(val), NEG(DUP(dist)))); case ARM_SFT_RRX: +#if CS_NEXT_VERSION < 6 case ARM_SFT_RRX_REG: +#endif if (carry_out) { *carry_out = LSB(DUP(val)); } diff --git a/librz/arch/isa/arm/arm_il64.c b/librz/arch/isa/arm/arm_il64.c index 9ebc3c87ed3..b2f62e148fb 100644 --- a/librz/arch/isa/arm/arm_il64.c +++ b/librz/arch/isa/arm/arm_il64.c @@ -2,6 +2,10 @@ // SPDX-License-Identifier: LGPL-3.0-only #include + +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #include "arm_cs.h" @@ -15,7 +19,7 @@ #define ISMEM ISMEM64 #define OPCOUNT OPCOUNT64 #undef MEMDISP64 // the original one casts to ut64 which we don't want here -#define MEMDISP(x) insn->detail->CS_aarch64_.operands[x].mem.disp +#define MEMDISP(x) insn->detail->arm64.operands[x].mem.disp #include @@ -35,144 +39,144 @@ static const char *regs_bound[] = { * IL for arm64 condition * unconditional is returned as NULL (rather than true), for simpler code */ -static RzILOpBool *cond(CS_aarch64_cc() c) { +static RzILOpBool *cond(ARM64CC_CondCode c) { switch (c) { - case CS_AARCH64CC(_EQ): + case ARM64CC_EQ: return VARG("zf"); - case CS_AARCH64CC(_NE): + case ARM64CC_NE: return INV(VARG("zf")); - case CS_AARCH64CC(_HS): + case ARM64CC_HS: return VARG("cf"); - case CS_AARCH64CC(_LO): + case ARM64CC_LO: return INV(VARG("cf")); - case CS_AARCH64CC(_MI): + case ARM64CC_MI: return VARG("nf"); - case CS_AARCH64CC(_PL): + case ARM64CC_PL: return INV(VARG("nf")); - case CS_AARCH64CC(_VS): + case ARM64CC_VS: return VARG("vf"); - case CS_AARCH64CC(_VC): + case ARM64CC_VC: return INV(VARG("vf")); - case CS_AARCH64CC(_HI): + case ARM64CC_HI: return AND(VARG("cf"), INV(VARG("zf"))); - case CS_AARCH64CC(_LS): + case ARM64CC_LS: return OR(INV(VARG("cf")), VARG("zf")); - case CS_AARCH64CC(_GE): + case ARM64CC_GE: return INV(XOR(VARG("nf"), VARG("vf"))); - case CS_AARCH64CC(_LT): + case ARM64CC_LT: return XOR(VARG("nf"), VARG("vf")); - case CS_AARCH64CC(_GT): + case ARM64CC_GT: return INV(OR(XOR(VARG("nf"), VARG("vf")), VARG("zf"))); - case CS_AARCH64CC(_LE): + case ARM64CC_LE: return OR(XOR(VARG("nf"), VARG("vf")), VARG("zf")); default: return NULL; } } -static CS_aarch64_reg() xreg(ut8 idx) { - // for some reason, the CS_AARCH64(_REG_X0)...CS_AARCH64(_REG_X30) enum values are not contiguous, +static arm64_reg xreg(ut8 idx) { + // for some reason, the ARM64_REG_X0...ARM64_REG_X30 enum values are not contiguous, // so use switch here and let the compiler optimize: switch (idx) { - case 0: return CS_AARCH64(_REG_X0); - case 1: return CS_AARCH64(_REG_X1); - case 2: return CS_AARCH64(_REG_X2); - case 3: return CS_AARCH64(_REG_X3); - case 4: return CS_AARCH64(_REG_X4); - case 5: return CS_AARCH64(_REG_X5); - case 6: return CS_AARCH64(_REG_X6); - case 7: return CS_AARCH64(_REG_X7); - case 8: return CS_AARCH64(_REG_X8); - case 9: return CS_AARCH64(_REG_X9); - case 10: return CS_AARCH64(_REG_X10); - case 11: return CS_AARCH64(_REG_X11); - case 12: return CS_AARCH64(_REG_X12); - case 13: return CS_AARCH64(_REG_X13); - case 14: return CS_AARCH64(_REG_X14); - case 15: return CS_AARCH64(_REG_X15); - case 16: return CS_AARCH64(_REG_X16); - case 17: return CS_AARCH64(_REG_X17); - case 18: return CS_AARCH64(_REG_X18); - case 19: return CS_AARCH64(_REG_X19); - case 20: return CS_AARCH64(_REG_X20); - case 21: return CS_AARCH64(_REG_X21); - case 22: return CS_AARCH64(_REG_X22); - case 23: return CS_AARCH64(_REG_X23); - case 24: return CS_AARCH64(_REG_X24); - case 25: return CS_AARCH64(_REG_X25); - case 26: return CS_AARCH64(_REG_X26); - case 27: return CS_AARCH64(_REG_X27); - case 28: return CS_AARCH64(_REG_X28); - case 29: return CS_AARCH64(_REG_X29); - case 30: return CS_AARCH64(_REG_X30); - case 31: return CS_AARCH64(_REG_SP); - case 32: return CS_AARCH64(_REG_XZR); + case 0: return ARM64_REG_X0; + case 1: return ARM64_REG_X1; + case 2: return ARM64_REG_X2; + case 3: return ARM64_REG_X3; + case 4: return ARM64_REG_X4; + case 5: return ARM64_REG_X5; + case 6: return ARM64_REG_X6; + case 7: return ARM64_REG_X7; + case 8: return ARM64_REG_X8; + case 9: return ARM64_REG_X9; + case 10: return ARM64_REG_X10; + case 11: return ARM64_REG_X11; + case 12: return ARM64_REG_X12; + case 13: return ARM64_REG_X13; + case 14: return ARM64_REG_X14; + case 15: return ARM64_REG_X15; + case 16: return ARM64_REG_X16; + case 17: return ARM64_REG_X17; + case 18: return ARM64_REG_X18; + case 19: return ARM64_REG_X19; + case 20: return ARM64_REG_X20; + case 21: return ARM64_REG_X21; + case 22: return ARM64_REG_X22; + case 23: return ARM64_REG_X23; + case 24: return ARM64_REG_X24; + case 25: return ARM64_REG_X25; + case 26: return ARM64_REG_X26; + case 27: return ARM64_REG_X27; + case 28: return ARM64_REG_X28; + case 29: return ARM64_REG_X29; + case 30: return ARM64_REG_X30; + case 31: return ARM64_REG_SP; + case 32: return ARM64_REG_XZR; default: rz_warn_if_reached(); - return CS_AARCH64(_REG_INVALID); + return ARM64_REG_INVALID; } } -static bool is_xreg(CS_aarch64_reg() reg) { +static bool is_xreg(arm64_reg reg) { switch (reg) { - case CS_AARCH64(_REG_X0): - case CS_AARCH64(_REG_X1): - case CS_AARCH64(_REG_X2): - case CS_AARCH64(_REG_X3): - case CS_AARCH64(_REG_X4): - case CS_AARCH64(_REG_X5): - case CS_AARCH64(_REG_X6): - case CS_AARCH64(_REG_X7): - case CS_AARCH64(_REG_X8): - case CS_AARCH64(_REG_X9): - case CS_AARCH64(_REG_X10): - case CS_AARCH64(_REG_X11): - case CS_AARCH64(_REG_X12): - case CS_AARCH64(_REG_X13): - case CS_AARCH64(_REG_X14): - case CS_AARCH64(_REG_X15): - case CS_AARCH64(_REG_X16): - case CS_AARCH64(_REG_X17): - case CS_AARCH64(_REG_X18): - case CS_AARCH64(_REG_X19): - case CS_AARCH64(_REG_X20): - case CS_AARCH64(_REG_X21): - case CS_AARCH64(_REG_X22): - case CS_AARCH64(_REG_X23): - case CS_AARCH64(_REG_X24): - case CS_AARCH64(_REG_X25): - case CS_AARCH64(_REG_X26): - case CS_AARCH64(_REG_X27): - case CS_AARCH64(_REG_X28): - case CS_AARCH64(_REG_X29): - case CS_AARCH64(_REG_X30): - case CS_AARCH64(_REG_SP): - case CS_AARCH64(_REG_XZR): + case ARM64_REG_X0: + case ARM64_REG_X1: + case ARM64_REG_X2: + case ARM64_REG_X3: + case ARM64_REG_X4: + case ARM64_REG_X5: + case ARM64_REG_X6: + case ARM64_REG_X7: + case ARM64_REG_X8: + case ARM64_REG_X9: + case ARM64_REG_X10: + case ARM64_REG_X11: + case ARM64_REG_X12: + case ARM64_REG_X13: + case ARM64_REG_X14: + case ARM64_REG_X15: + case ARM64_REG_X16: + case ARM64_REG_X17: + case ARM64_REG_X18: + case ARM64_REG_X19: + case ARM64_REG_X20: + case ARM64_REG_X21: + case ARM64_REG_X22: + case ARM64_REG_X23: + case ARM64_REG_X24: + case ARM64_REG_X25: + case ARM64_REG_X26: + case ARM64_REG_X27: + case ARM64_REG_X28: + case ARM64_REG_X29: + case ARM64_REG_X30: + case ARM64_REG_SP: + case ARM64_REG_XZR: return true; default: return false; } } -static ut8 wreg_idx(CS_aarch64_reg() reg) { - if (reg >= CS_AARCH64(_REG_W0) && reg <= CS_AARCH64(_REG_W30)) { - return reg - CS_AARCH64(_REG_W0); +static ut8 wreg_idx(arm64_reg reg) { + if (reg >= ARM64_REG_W0 && reg <= ARM64_REG_W30) { + return reg - ARM64_REG_W0; } - if (reg == CS_AARCH64(_REG_WSP)) { + if (reg == ARM64_REG_WSP) { return 31; } - if (reg == CS_AARCH64(_REG_WZR)) { + if (reg == ARM64_REG_WZR) { return 32; } rz_warn_if_reached(); return 0; } -static bool is_wreg(CS_aarch64_reg() reg) { - return (reg >= CS_AARCH64(_REG_W0) && reg <= CS_AARCH64(_REG_W30)) || reg == CS_AARCH64(_REG_WSP) || reg == CS_AARCH64(_REG_WZR); +static bool is_wreg(arm64_reg reg) { + return (reg >= ARM64_REG_W0 && reg <= ARM64_REG_W30) || reg == ARM64_REG_WSP || reg == ARM64_REG_WZR; } -static CS_aarch64_reg() xreg_of_reg(CS_aarch64_reg() reg) { +static arm64_reg xreg_of_reg(arm64_reg reg) { if (is_wreg(reg)) { return xreg(wreg_idx(reg)); } @@ -182,41 +186,41 @@ static CS_aarch64_reg() xreg_of_reg(CS_aarch64_reg() reg) { /** * Variable name for a register given by cs */ -static const char *reg_var_name(CS_aarch64_reg() reg) { +static const char *reg_var_name(arm64_reg reg) { reg = xreg_of_reg(reg); switch (reg) { - case CS_AARCH64(_REG_X0): return "x0"; - case CS_AARCH64(_REG_X1): return "x1"; - case CS_AARCH64(_REG_X2): return "x2"; - case CS_AARCH64(_REG_X3): return "x3"; - case CS_AARCH64(_REG_X4): return "x4"; - case CS_AARCH64(_REG_X5): return "x5"; - case CS_AARCH64(_REG_X6): return "x6"; - case CS_AARCH64(_REG_X7): return "x7"; - case CS_AARCH64(_REG_X8): return "x8"; - case CS_AARCH64(_REG_X9): return "x9"; - case CS_AARCH64(_REG_X10): return "x10"; - case CS_AARCH64(_REG_X11): return "x11"; - case CS_AARCH64(_REG_X12): return "x12"; - case CS_AARCH64(_REG_X13): return "x13"; - case CS_AARCH64(_REG_X14): return "x14"; - case CS_AARCH64(_REG_X15): return "x15"; - case CS_AARCH64(_REG_X16): return "x16"; - case CS_AARCH64(_REG_X17): return "x17"; - case CS_AARCH64(_REG_X18): return "x18"; - case CS_AARCH64(_REG_X19): return "x19"; - case CS_AARCH64(_REG_X20): return "x20"; - case CS_AARCH64(_REG_X21): return "x21"; - case CS_AARCH64(_REG_X22): return "x22"; - case CS_AARCH64(_REG_X23): return "x23"; - case CS_AARCH64(_REG_X24): return "x24"; - case CS_AARCH64(_REG_X25): return "x25"; - case CS_AARCH64(_REG_X26): return "x26"; - case CS_AARCH64(_REG_X27): return "x27"; - case CS_AARCH64(_REG_X28): return "x28"; - case CS_AARCH64(_REG_X29): return "x29"; - case CS_AARCH64(_REG_X30): return "x30"; - case CS_AARCH64(_REG_SP): return "sp"; + case ARM64_REG_X0: return "x0"; + case ARM64_REG_X1: return "x1"; + case ARM64_REG_X2: return "x2"; + case ARM64_REG_X3: return "x3"; + case ARM64_REG_X4: return "x4"; + case ARM64_REG_X5: return "x5"; + case ARM64_REG_X6: return "x6"; + case ARM64_REG_X7: return "x7"; + case ARM64_REG_X8: return "x8"; + case ARM64_REG_X9: return "x9"; + case ARM64_REG_X10: return "x10"; + case ARM64_REG_X11: return "x11"; + case ARM64_REG_X12: return "x12"; + case ARM64_REG_X13: return "x13"; + case ARM64_REG_X14: return "x14"; + case ARM64_REG_X15: return "x15"; + case ARM64_REG_X16: return "x16"; + case ARM64_REG_X17: return "x17"; + case ARM64_REG_X18: return "x18"; + case ARM64_REG_X19: return "x19"; + case ARM64_REG_X20: return "x20"; + case ARM64_REG_X21: return "x21"; + case ARM64_REG_X22: return "x22"; + case ARM64_REG_X23: return "x23"; + case ARM64_REG_X24: return "x24"; + case ARM64_REG_X25: return "x25"; + case ARM64_REG_X26: return "x26"; + case ARM64_REG_X27: return "x27"; + case ARM64_REG_X28: return "x28"; + case ARM64_REG_X29: return "x29"; + case ARM64_REG_X30: return "x30"; + case ARM64_REG_SP: return "sp"; default: return NULL; } } @@ -224,11 +228,11 @@ static const char *reg_var_name(CS_aarch64_reg() reg) { /** * Get the bits of the given register or 0, if it is not known (e.g. not implemented yet) */ -static ut32 reg_bits(CS_aarch64_reg() reg) { - if (is_xreg(reg) || reg == CS_AARCH64(_REG_XZR)) { +static ut32 reg_bits(arm64_reg reg) { + if (is_xreg(reg) || reg == ARM64_REG_XZR) { return 64; } - if (is_wreg(reg) || reg == CS_AARCH64(_REG_WZR)) { + if (is_wreg(reg) || reg == ARM64_REG_WZR) { return 32; } return 0; @@ -237,16 +241,16 @@ static ut32 reg_bits(CS_aarch64_reg() reg) { /** * IL to read the given capstone reg */ -static RzILOpBitVector *read_reg(CS_aarch64_reg() reg) { - if (reg == CS_AARCH64(_REG_XZR)) { +static RzILOpBitVector *read_reg(arm64_reg reg) { + if (reg == ARM64_REG_XZR) { return U64(0); } - if (reg == CS_AARCH64(_REG_WZR)) { + if (reg == ARM64_REG_WZR) { return U32(0); } const char *var = reg_var_name(reg); if (!var) { - return NULL; + return U64(0); } if (is_wreg(reg)) { return UNSIGNED(32, VARG(var)); @@ -267,35 +271,35 @@ static RzILOpBitVector *adjust_unsigned(ut32 bits, RZ_OWN RzILOpBitVector *v) { return v; } -static RzILOpBitVector *reg_extend(ut32 dst_bits, CS_aarch64_extender() ext, RZ_OWN RzILOpBitVector *reg, ut32 v_bits) { +static RzILOpBitVector *reg_extend(ut32 dst_bits, arm64_extender ext, RZ_OWN RzILOpBitVector *reg, ut32 v_bits) { bool is_signed = false; ut32 src_bits = v_bits; switch (ext) { - case CS_AARCH64(_EXT_SXTB): + case ARM64_EXT_SXTB: is_signed = true; // fallthrough - case CS_AARCH64(_EXT_UXTB): + case ARM64_EXT_UXTB: src_bits = 8; break; - case CS_AARCH64(_EXT_SXTH): + case ARM64_EXT_SXTH: is_signed = true; // fallthrough - case CS_AARCH64(_EXT_UXTH): + case ARM64_EXT_UXTH: src_bits = 16; break; - case CS_AARCH64(_EXT_SXTW): + case ARM64_EXT_SXTW: is_signed = true; // fallthrough - case CS_AARCH64(_EXT_UXTW): + case ARM64_EXT_UXTW: src_bits = 32; break; - case CS_AARCH64(_EXT_SXTX): + case ARM64_EXT_SXTX: is_signed = true; // fallthrough - case CS_AARCH64(_EXT_UXTX): + case ARM64_EXT_UXTX: src_bits = 64; break; @@ -320,16 +324,16 @@ static RzILOpBitVector *reg_extend(ut32 dst_bits, CS_aarch64_extender() ext, RZ_ return is_signed ? SIGNED(dst_bits, reg) : reg; } -static RzILOpBitVector *apply_shift(CS_aarch64_shifter() sft, ut32 dist, RZ_OWN RzILOpBitVector *v) { +static RzILOpBitVector *apply_shift(arm64_shifter sft, ut32 dist, RZ_OWN RzILOpBitVector *v) { if (!dist) { return v; } switch (sft) { - case CS_AARCH64(_SFT_LSL): + case ARM64_SFT_LSL: return SHIFTL0(v, UN(6, dist)); - case CS_AARCH64(_SFT_LSR): + case ARM64_SFT_LSR: return SHIFTR0(v, UN(6, dist)); - case CS_AARCH64(_SFT_ASR): + case ARM64_SFT_ASR: return SHIFTRA(v, UN(6, dist)); default: return v; @@ -338,13 +342,13 @@ static RzILOpBitVector *apply_shift(CS_aarch64_shifter() sft, ut32 dist, RZ_OWN #define REG(n) read_reg(REGID(n)) #define REGBITS(n) reg_bits(REGID(n)) -#define MEMBASEID(x) insn->detail->CS_aarch64_.operands[x].mem.base +#define MEMBASEID(x) insn->detail->arm64.operands[x].mem.base #define MEMBASE(x) read_reg(MEMBASEID(x)) /** * IL to write a value to the given capstone reg */ -static RzILOpEffect *write_reg(CS_aarch64_reg() reg, RZ_OWN RZ_NONNULL RzILOpBitVector *v) { +static RzILOpEffect *write_reg(arm64_reg reg, RZ_OWN RZ_NONNULL RzILOpBitVector *v) { rz_return_val_if_fail(v, NULL); const char *var = reg_var_name(reg); if (!var) { @@ -357,8 +361,8 @@ static RzILOpEffect *write_reg(CS_aarch64_reg() reg, RZ_OWN RZ_NONNULL RzILOpBit return SETG(var, v); } -static RzILOpBitVector *arg_mem(RzILOpBitVector *base_plus_disp, CS_aarch64_op() * op) { - if (op->mem.index == CS_AARCH64(_REG_INVALID)) { +static RzILOpBitVector *arg_mem(RzILOpBitVector *base_plus_disp, cs_arm64_op *op) { + if (op->mem.index == ARM64_REG_INVALID) { return base_plus_disp; } RzILOpBitVector *index = read_reg(op->mem.index); @@ -375,9 +379,9 @@ static RzILOpBitVector *arg_mem(RzILOpBitVector *base_plus_disp, CS_aarch64_op() */ static RzILOpBitVector *arg(RZ_BORROW cs_insn *insn, size_t n, RZ_OUT ut32 *bits_inout) { ut32 bits_requested = bits_inout ? *bits_inout : 0; - CS_aarch64_op() *op = &insn->detail->CS_aarch64_.operands[n]; + cs_arm64_op *op = &insn->detail->arm64.operands[n]; switch (op->type) { - case CS_AARCH64(_OP_REG): { + case ARM64_OP_REG: { if (!bits_requested) { bits_requested = REGBITS(n); if (!bits_requested) { @@ -393,17 +397,17 @@ static RzILOpBitVector *arg(RZ_BORROW cs_insn *insn, size_t n, RZ_OUT ut32 *bits } return apply_shift(op->shift.type, op->shift.value, reg_extend(bits_requested, op->ext, r, REGBITS(n))); } - case CS_AARCH64(_OP_IMM): { + case ARM64_OP_IMM: { if (!bits_requested) { return NULL; } ut64 val = IMM(n); - if (op->shift.type == CS_AARCH64(_SFT_LSL)) { + if (op->shift.type == ARM64_SFT_LSL) { val <<= op->shift.value; } return UN(bits_requested, val); } - case CS_AARCH64(_OP_MEM): { + case ARM64_OP_MEM: { RzILOpBitVector *addr = MEMBASE(n); #if CS_NEXT_VERSION >= 6 if (ISPOSTINDEX64()) { @@ -416,7 +420,7 @@ static RzILOpBitVector *arg(RZ_BORROW cs_insn *insn, size_t n, RZ_OUT ut32 *bits } else if (disp < 0) { addr = SUB(addr, U64(-disp)); } - return arg_mem(addr, &insn->detail->CS_aarch64_.operands[n]); + return arg_mem(addr, &insn->detail->arm64.operands[n]); } default: break; @@ -450,16 +454,16 @@ static RzILOpEffect *update_flags_zn00(RzILOpBitVector *v) { } /** - * Capstone: CS_AARCH64(_INS_ADD), CS_AARCH64(_INS_ADC), CS_AARCH64(_INS_SUB), CS_AARCH64(_INS_SBC) + * Capstone: ARM64_INS_ADD, ARM64_INS_ADC, ARM64_INS_SUB, ARM64_INS_SBC * ARM: add, adds, adc, adcs, sub, subs, sbc, sbcs */ static RzILOpEffect *add_sub(cs_insn *insn) { if (!ISREG(0)) { return NULL; } - bool is_sub = insn->id == CS_AARCH64(_INS_SUB) || insn->id == CS_AARCH64(_INS_SBC) + bool is_sub = insn->id == ARM64_INS_SUB || insn->id == ARM64_INS_SBC #if CS_API_MAJOR > 4 - || insn->id == CS_AARCH64(_INS_SUBS) || insn->id == CS_AARCH64(_INS_SBCS) + || insn->id == ARM64_INS_SUBS || insn->id == ARM64_INS_SBCS #endif ; ut32 bits = REGBITS(0); @@ -475,23 +479,23 @@ static RzILOpEffect *add_sub(cs_insn *insn) { } RzILOpBitVector *res = is_sub ? SUB(a, b) : ADD(a, b); bool with_carry = false; - if (insn->id == CS_AARCH64(_INS_ADC) + if (insn->id == ARM64_INS_ADC #if CS_API_MAJOR > 4 - || insn->id == CS_AARCH64(_INS_ADCS) + || insn->id == ARM64_INS_ADCS #endif ) { res = ADD(res, ITE(VARG("cf"), UN(bits, 1), UN(bits, 0))); with_carry = true; - } else if (insn->id == CS_AARCH64(_INS_SBC) + } else if (insn->id == ARM64_INS_SBC #if CS_API_MAJOR > 4 - || insn->id == CS_AARCH64(_INS_SBCS) + || insn->id == ARM64_INS_SBCS #endif ) { res = SUB(res, ITE(VARG("cf"), UN(bits, 0), UN(bits, 1))); with_carry = true; } RzILOpEffect *set = write_reg(REGID(0), res); - bool update_flags = insn->detail->CS_aarch64_.update_flags; + bool update_flags = insn->detail->arm64.update_flags; if (update_flags) { return SEQ6( SETL("a", DUP(a)), @@ -505,7 +509,7 @@ static RzILOpEffect *add_sub(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_ADR), CS_AARCH64(_INS_ADRP) + * Capstone: ARM64_INS_ADR, ARM64_INS_ADRP * ARM: adr, adrp */ static RzILOpEffect *adr(cs_insn *insn) { @@ -516,7 +520,7 @@ static RzILOpEffect *adr(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_AND), CS_AARCH64(_INS_EON), CS_AARCH64(_INS_EOR), CS_AARCH64(_INS_ORN), CS_AARCH64(_INS_AORR) + * Capstone: ARM64_INS_AND, ARM64_INS_EON, ARM64_INS_EOR, ARM64_INS_ORN, ARM64_INS_AORR * ARM: and, eon, eor, orn, orr */ static RzILOpEffect *bitwise(cs_insn *insn) { @@ -536,19 +540,19 @@ static RzILOpEffect *bitwise(cs_insn *insn) { } RzILOpBitVector *res; switch (insn->id) { - case CS_AARCH64(_INS_EOR): + case ARM64_INS_EOR: res = LOGXOR(a, b); break; - case CS_AARCH64(_INS_EON): + case ARM64_INS_EON: res = LOGXOR(a, LOGNOT(b)); break; - case CS_AARCH64(_INS_ORN): + case ARM64_INS_ORN: res = LOGOR(a, LOGNOT(b)); break; - case CS_AARCH64(_INS_ORR): + case ARM64_INS_ORR: res = LOGOR(a, b); break; - default: // CS_AARCH64(_INS_AND) + default: // ARM64_INS_AND res = LOGAND(a, b); break; } @@ -556,14 +560,14 @@ static RzILOpEffect *bitwise(cs_insn *insn) { if (!eff) { return NULL; } - if (insn->detail->CS_aarch64_.update_flags) { + if (insn->detail->arm64.update_flags) { return SEQ2(eff, update_flags_zn00(REG(0))); } return eff; } /** - * Capstone: CS_AARCH64(_INS_ASR), CS_AARCH64(_INS_LSL), CS_AARCH64(_INS_LSR), CS_AARCH64(_INS_ROR) + * Capstone: ARM64_INS_ASR, ARM64_INS_LSL, ARM64_INS_LSR, ARM64_INS_ROR * ARM: asr, asrv, lsl, lslv, lsr, lsrv, ror, rorv */ static RzILOpEffect *shift(cs_insn *insn) { @@ -586,25 +590,28 @@ static RzILOpEffect *shift(cs_insn *insn) { } RzILOpBitVector *res; switch (insn->id) { - case CS_AARCH64(_INS_ASR): + case ARM64_INS_ASR: res = SHIFTRA(a, b); break; - case CS_AARCH64(_INS_LSR): + case ARM64_INS_LSR: res = SHIFTR0(a, b); break; - case CS_AARCH64(_INS_ROR): + case ARM64_INS_ROR: res = LOGOR(SHIFTR0(a, b), SHIFTL0(DUP(a), NEG(DUP(b)))); break; #if CS_NEXT_VERSION >= 6 - case AArch64_INS_EXTR: - if (insn->alias_id != AArch64_INS_ALIAS_ROR) { + case AARCH64_INS_EXTR: + if (insn->alias_id != AARCH64_INS_ALIAS_ROR) { + rz_il_op_pure_free(a); + rz_il_op_pure_free(b); return NULL; } + rz_il_op_pure_free(b); b = ARG(3, &bits); res = LOGOR(SHIFTR0(a, b), SHIFTL0(DUP(a), NEG(DUP(b)))); break; #endif - default: // CS_AARCH64(_INS_LSL) + default: // ARM64_INS_LSL res = SHIFTL0(a, b); break; } @@ -612,14 +619,14 @@ static RzILOpEffect *shift(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_B), CS_AARCH64(_INS_RET), CS_AARCH64(_INS_RETAA), CS_AARCH64(_INS_RETAB) + * Capstone: ARM64_INS_B, ARM64_INS_RET, ARM64_INS_RETAA, ARM64_INS_RETAB * ARM: b, b.cond, ret, retaa, retab */ static RzILOpEffect *branch(cs_insn *insn) { RzILOpBitVector *a; if (OPCOUNT() == 0) { - // for CS_AARCH64(_INS_RET) and similar - a = read_reg(CS_AARCH64(_REG_LR)); + // for ARM64_INS_RET and similar + a = read_reg(ARM64_REG_LR); } else { ut32 bits = 64; a = ARG(0, &bits); @@ -627,7 +634,7 @@ static RzILOpEffect *branch(cs_insn *insn) { if (!a) { return NULL; } - RzILOpBool *c = cond(insn->detail->CS_aarch64_.cc); + RzILOpBool *c = cond(insn->detail->arm64.cc); if (c) { return BRANCH(c, JMP(a), NOP()); } @@ -635,7 +642,7 @@ static RzILOpEffect *branch(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_BL), CS_AARCH64(_INS_BLR), CS_AARCH64(_INS_BLRAA), CS_AARCH64(_INS_BLRAAZ), CS_AARCH64(_INS_BLRAB), CS_AARCH64(_INS_BLRABZ) + * Capstone: ARM64_INS_BL, ARM64_INS_BLR, ARM64_INS_BLRAA, ARM64_INS_BLRAAZ, ARM64_INS_BLRAB, ARM64_INS_BLRABZ * ARM: bl, blr, blraa, blraaz, blrab, blrabz */ static RzILOpEffect *bl(cs_insn *insn) { @@ -650,7 +657,7 @@ static RzILOpEffect *bl(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_BFM), CS_AARCH64(_INS_BFI), CS_AARCH64(_INS_BFXIL) + * Capstone: ARM64_INS_BFM, ARM64_INS_BFI, ARM64_INS_BFXIL * ARM: bfm, bfc, bfi, bfxil */ static RzILOpEffect *bfm(cs_insn *insn) { @@ -674,22 +681,22 @@ static RzILOpEffect *bfm(cs_insn *insn) { #if CS_NEXT_VERSION < 6 ut64 mask_base = rz_num_bitmask(IMM(3)); ut64 mask = mask_base << RZ_MIN(63, IMM(2)); - if (insn->id == CS_AARCH64(_INS_BFI)) { + if (insn->id == ARM64_INS_BFI) { return write_reg(REGID(0), LOGOR(LOGAND(a, UN(bits, ~mask)), SHIFTL0(LOGAND(b, UN(bits, mask_base)), UN(6, IMM(2))))); } - // insn->id == CS_AARCH64(_INS_BFXIL) + // insn->id == ARM64_INS_BFXIL return write_reg(REGID(0), LOGOR(LOGAND(a, UN(bits, ~mask_base)), SHIFTR0(LOGAND(b, UN(bits, mask)), UN(6, IMM(2))))); #else ut64 lsb = IMM(2); ut64 width = IMM(3); - if (insn->alias_id == AArch64_INS_ALIAS_BFI) { + if (insn->alias_id == AARCH64_INS_ALIAS_BFI) { width += 1; // TODO Mod depends on (sf && N) bits lsb = -lsb % 32; ut64 mask_base = rz_num_bitmask(width); ut64 mask = mask_base << RZ_MIN(63, lsb); return write_reg(REGID(0), LOGOR(LOGAND(a, UN(bits, ~mask)), SHIFTL0(LOGAND(b, UN(bits, mask_base)), UN(6, lsb)))); - } else if (insn->alias_id == AArch64_INS_ALIAS_BFXIL) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_BFXIL) { width = width - lsb + 1; ut64 mask_base = rz_num_bitmask(width); ut64 mask = mask_base << RZ_MIN(63, lsb); @@ -700,7 +707,7 @@ static RzILOpEffect *bfm(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_BIC), CS_AARCH64(_INS_BICS) + * Capstone: ARM64_INS_BIC, ARM64_INS_BICS * ARM: bic, bics */ static RzILOpEffect *bic(cs_insn *insn) { @@ -720,14 +727,14 @@ static RzILOpEffect *bic(cs_insn *insn) { } RzILOpBitVector *res = LOGAND(a, LOGNOT(b)); RzILOpEffect *eff = NULL; - if (REGID(0) != CS_AARCH64(_REG_XZR) && REGID(0) != CS_AARCH64(_REG_WZR)) { + if (REGID(0) != ARM64_REG_XZR && REGID(0) != ARM64_REG_WZR) { eff = write_reg(REGID(0), res); if (!eff) { return NULL; } res = NULL; } - if (insn->detail->CS_aarch64_.update_flags) { + if (insn->detail->arm64.update_flags) { RzILOpEffect *eff1 = update_flags_zn00(res ? res : REG(0)); return eff ? SEQ2(eff, eff1) : eff1; } @@ -739,9 +746,9 @@ static RzILOpEffect *bic(cs_insn *insn) { #if CS_API_MAJOR > 4 /** - * Capstone: CS_AARCH64(_INS_CAS), CS_AARCH64(_INS_CASA), CS_AARCH64(_INS_CASAL), CS_AARCH64(_INS_CASL), - * CS_AARCH64(_INS_CASB), CS_AARCH64(_INS_CASAB), CS_AARCH64(_INS_CASALB), CS_AARCH64(_INS_CASLB), - * CS_AARCH64(_INS_CASH), CS_AARCH64(_INS_CASAH), CS_AARCH64(_INS_CASALH), CS_AARCH64(_INS_CASLH): + * Capstone: ARM64_INS_CAS, ARM64_INS_CASA, ARM64_INS_CASAL, ARM64_INS_CASL, + * ARM64_INS_CASB, ARM64_INS_CASAB, ARM64_INS_CASALB, ARM64_INS_CASLB, + * ARM64_INS_CASH, ARM64_INS_CASAH, ARM64_INS_CASALH, ARM64_INS_CASLH: * ARM: cas, casa, casal, casl, casb, casab, casalb, caslb, cash, casah, casalh, caslh */ static RzILOpEffect *cas(cs_insn *insn) { @@ -753,16 +760,16 @@ static RzILOpEffect *cas(cs_insn *insn) { return NULL; } switch (insn->id) { - case CS_AARCH64(_INS_CASB): - case CS_AARCH64(_INS_CASAB): - case CS_AARCH64(_INS_CASALB): - case CS_AARCH64(_INS_CASLB): + case ARM64_INS_CASB: + case ARM64_INS_CASAB: + case ARM64_INS_CASALB: + case ARM64_INS_CASLB: bits = 8; break; - case CS_AARCH64(_INS_CASH): - case CS_AARCH64(_INS_CASAH): - case CS_AARCH64(_INS_CASALH): - case CS_AARCH64(_INS_CASLH): + case ARM64_INS_CASH: + case ARM64_INS_CASAH: + case ARM64_INS_CASALH: + case ARM64_INS_CASLH: bits = 16; break; default: @@ -786,7 +793,7 @@ static RzILOpEffect *cas(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_CASP), CS_AARCH64(_INS_CASPA), CS_AARCH64(_INS_CASPAL), CS_AARCH64(_INS_CASPL) + * Capstone: ARM64_INS_CASP, ARM64_INS_CASPA, ARM64_INS_CASPAL, ARM64_INS_CASPL * ARM: casp, caspa, caspal, caspl */ static RzILOpEffect *casp(cs_insn *insn) { @@ -825,7 +832,7 @@ static RzILOpEffect *casp(cs_insn *insn) { #endif /** - * Capstone: CS_AARCH64(_INS_CBZ), CS_AARCH64(_INS_CBNZ) + * Capstone: ARM64_INS_CBZ, ARM64_INS_CBNZ * ARM: cbz, cbnz */ static RzILOpEffect *cbz(cs_insn *insn) { @@ -837,11 +844,11 @@ static RzILOpEffect *cbz(cs_insn *insn) { rz_il_op_pure_free(tgt); return NULL; } - return BRANCH(insn->id == CS_AARCH64(_INS_CBNZ) ? INV(IS_ZERO(v)) : IS_ZERO(v), JMP(tgt), NULL); + return BRANCH(insn->id == ARM64_INS_CBNZ ? INV(IS_ZERO(v)) : IS_ZERO(v), JMP(tgt), NULL); } /** - * Capstone: CS_AARCH64(_INS_CMP), CS_AARCH64(_INS_CMN), CS_AARCH64(_INS_CCMP), CS_AARCH64(_INS_CCMN) + * Capstone: ARM64_INS_CMP, ARM64_INS_CMN, ARM64_INS_CCMP, ARM64_INS_CCMN * ARM: cmp, cmn, ccmp, ccmn */ static RzILOpEffect *cmp(cs_insn *insn) { @@ -853,8 +860,8 @@ static RzILOpEffect *cmp(cs_insn *insn) { #else RzILOpBitVector *a; RzILOpBitVector *b; - if (insn->alias_id == AArch64_INS_ALIAS_CMP || - insn->alias_id == AArch64_INS_ALIAS_CMN) { + if (insn->alias_id == AARCH64_INS_ALIAS_CMP || + insn->alias_id == AARCH64_INS_ALIAS_CMN) { // Reg at 0 is zero register a = ARG(1, &bits); b = ARG(2, &bits); @@ -869,9 +876,9 @@ static RzILOpEffect *cmp(cs_insn *insn) { return NULL; } #if CS_NEXT_VERSION < 6 - bool is_neg = insn->id == CS_AARCH64(_INS_CMN) || insn->id == CS_AARCH64(_INS_CCMN); + bool is_neg = insn->id == ARM64_INS_CMN || insn->id == ARM64_INS_CCMN; #else - bool is_neg = insn->alias_id == AArch64_INS_ALIAS_CMN || insn->id == CS_AARCH64(_INS_CCMN); + bool is_neg = insn->alias_id == ARM64_INS_ALIAS_CMN || insn->id == ARM64_INS_CCMN; #endif RzILOpEffect *eff = SEQ6( SETL("a", a), @@ -880,7 +887,7 @@ static RzILOpEffect *cmp(cs_insn *insn) { SETG("cf", (is_neg ? add_carry : sub_carry)(VARL("a"), VARL("b"), false, bits)), SETG("vf", (is_neg ? add_overflow : sub_overflow)(VARL("a"), VARL("b"), VARL("r"))), update_flags_zn(VARL("r"))); - RzILOpBool *c = cond(insn->detail->CS_aarch64_.cc); + RzILOpBool *c = cond(insn->detail->arm64.cc); if (c) { ut64 imm = IMM(2); return BRANCH(c, @@ -895,7 +902,7 @@ static RzILOpEffect *cmp(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_CINC), CS_AARCH64(_INS_CSINC), CS_AARCH64(_INS_CINV), CS_AARCH64(_INS_CSINV), CS_AARCH64(_INS_CNEG), CS_AARCH64(_INS_CSNEG), CS_AARCH64(_INS_CSEL) + * Capstone: ARM64_INS_CINC, ARM64_INS_CSINC, ARM64_INS_CINV, ARM64_INS_CSINV, ARM64_INS_CNEG, ARM64_INS_CSNEG, ARM64_INS_CSEL * ARM: cinc, csinc, cinv, csinv, cneg, csneg, csel */ static RzILOpEffect *csinc(cs_insn *insn) { @@ -914,15 +921,15 @@ static RzILOpEffect *csinc(cs_insn *insn) { return NULL; } #if CS_NEXT_VERSION < 6 - RzILOpBool *c = cond(insn->detail->CS_aarch64_.cc); + RzILOpBool *c = cond(insn->detail->arm64.cc); #else - AArch64CC_CondCode cc; - if (insn->alias_id == AArch64_INS_ALIAS_CINV || - insn->alias_id == AArch64_INS_ALIAS_CNEG || - insn->alias_id == AArch64_INS_ALIAS_CINC) { - cc = AArch64CC_getInvertedCondCode(insn->detail->CS_aarch64_.cc); + ARM64CC_CondCode cc; + if (insn->alias_id == AARCH64_INS_ALIAS_CINV || + insn->alias_id == AARCH64_INS_ALIAS_CNEG || + insn->alias_id == AARCH64_INS_ALIAS_CINC) { + cc = AArch64CC_getInvertedCondCode(insn->detail->arm64.cc); } else { - cc = insn->detail->CS_aarch64_.cc; + cc = insn->detail->arm64.cc; } RzILOpBool *c = cond(cc); #endif @@ -939,45 +946,45 @@ static RzILOpEffect *csinc(cs_insn *insn) { RzILOpBitVector *res; bool invert_cond = false; switch (insn->id) { - case CS_AARCH64(_INS_CSEL): + case ARM64_INS_CSEL: invert_cond = true; res = src1; break; #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CSINV): + case ARM64_INS_CSINV: invert_cond = true; // fallthrough - case CS_AARCH64(_INS_CINV): + case ARM64_INS_CINV: res = LOGNOT(src1); break; - case CS_AARCH64(_INS_CSNEG): + case ARM64_INS_CSNEG: invert_cond = true; // fallthrough - case CS_AARCH64(_INS_CNEG): + case ARM64_INS_CNEG: res = NEG(src1); break; - case CS_AARCH64(_INS_CSINC): + case ARM64_INS_CSINC: invert_cond = true; #else - case CS_AARCH64(_INS_CSINV): + case ARM64_INS_CSINV: if (!insn->is_alias) { invert_cond = true; } res = LOGNOT(src1); break; - case CS_AARCH64(_INS_CSNEG): + case ARM64_INS_CSNEG: if (!insn->is_alias) { invert_cond = true; } res = NEG(src1); break; - case CS_AARCH64(_INS_CSINC): + case ARM64_INS_CSINC: if (!insn->is_alias) { invert_cond = true; } #endif // fallthrough - default: // CS_AARCH64(_INS_CINC), CS_AARCH64(_INS_CSINC) + default: // ARM64_INS_CINC, ARM64_INS_CSINC res = ADD(src1, UN(bits, 1)); break; } @@ -985,7 +992,7 @@ static RzILOpEffect *csinc(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_CSET), CS_AARCH64(_INS_CSETM) + * Capstone: ARM64_INS_CSET, ARM64_INS_CSETM * ARM: cset, csetm */ static RzILOpEffect *cset(cs_insn *insn) { @@ -994,13 +1001,13 @@ static RzILOpEffect *cset(cs_insn *insn) { } RzILOpBool *c = NULL; #if CS_NEXT_VERSION < 6 - c = cond(insn->detail->CS_aarch64_.cc); + c = cond(insn->detail->arm64.cc); #else - if (insn->alias_id == AArch64_INS_ALIAS_CSET || - insn->alias_id == AArch64_INS_ALIAS_CSETM) { - c = cond(AArch64CC_getInvertedCondCode(insn->detail->CS_aarch64_.cc)); + if (insn->alias_id == AARCH64_INS_ALIAS_CSET || + insn->alias_id == AARCH64_INS_ALIAS_CSETM) { + c = cond(AArch64CC_getInvertedCondCode(insn->detail->arm64.cc)); } else { - c = cond(insn->detail->CS_aarch64_.cc); + c = cond(insn->detail->arm64.cc); } #endif if (!c) { @@ -1008,14 +1015,14 @@ static RzILOpEffect *cset(cs_insn *insn) { } ut32 bits = REGBITS(0); #if CS_NEXT_VERSION < 6 - return write_reg(REGID(0), ITE(c, SN(bits, insn->id == CS_AARCH64(_INS_CSETM) ? -1 : 1), SN(bits, 0))); + return write_reg(REGID(0), ITE(c, SN(bits, insn->id == ARM64_INS_CSETM ? -1 : 1), SN(bits, 0))); #else - return write_reg(REGID(0), ITE(c, SN(bits, insn->alias_id == AArch64_INS_ALIAS_CSETM ? -1 : 1), SN(bits, 0))); + return write_reg(REGID(0), ITE(c, SN(bits, insn->alias_id == AARCH64_INS_ALIAS_CSETM ? -1 : 1), SN(bits, 0))); #endif } /** - * Capstone: CS_AARCH64(_INS_CLS) + * Capstone: ARM64_INS_CLS * ARM: cls */ static RzILOpEffect *cls(cs_insn *insn) { @@ -1039,7 +1046,7 @@ static RzILOpEffect *cls(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_CLZ) + * Capstone: ARM64_INS_CLZ * ARM: clz */ static RzILOpEffect *clz(cs_insn *insn) { @@ -1062,7 +1069,7 @@ static RzILOpEffect *clz(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_EXTR) + * Capstone: ARM64_INS_EXTR * ARM: extr */ static RzILOpEffect *extr(cs_insn *insn) { @@ -1099,7 +1106,7 @@ static void label_svc(RzILVM *vm, RzILOpEffect *op) { } /** - * Capstone: CS_AARCH64(_INS_HVC) + * Capstone: ARM64_INS_HVC * ARM: hvc */ static RzILOpEffect *hvc(cs_insn *insn) { @@ -1110,7 +1117,7 @@ static void label_hvc(RzILVM *vm, RzILOpEffect *op) { // stub, nothing to do here } -static RzILOpEffect *load_effect(ut32 bits, bool is_signed, CS_aarch64_reg() dst_reg, RZ_OWN RzILOpBitVector *addr) { +static RzILOpEffect *load_effect(ut32 bits, bool is_signed, arm64_reg dst_reg, RZ_OWN RzILOpBitVector *addr) { RzILOpBitVector *val = bits == 8 ? LOAD(addr) : LOADW(bits, addr); if (bits != 64) { if (is_signed) { @@ -1129,7 +1136,7 @@ static RzILOpEffect *load_effect(ut32 bits, bool is_signed, CS_aarch64_reg() dst static RzILOpEffect *writeback(cs_insn *insn, size_t addr_op, RZ_BORROW RzILOpBitVector *addr) { #if CS_NEXT_VERSION < 6 - if (!insn->detail->CS_aarch64_.writeback || !is_xreg(MEMBASEID(addr_op))) { + if (!insn->detail->arm64.writeback || !is_xreg(MEMBASEID(addr_op))) { #else if (!insn->detail->writeback || !is_xreg(MEMBASEID(addr_op))) { #endif @@ -1149,16 +1156,16 @@ static RzILOpEffect *writeback(cs_insn *insn, size_t addr_op, RZ_BORROW RzILOpBi } /** - * Capstone: CS_AARCH64(_INS_LDR), CS_AARCH64(_INS_LDRB), CS_AARCH64(_INS_LDRH), CS_AARCH64(_INS_LDRU), CS_AARCH64(_INS_LDRUB), CS_AARCH64(_INS_LDRUH), - * CS_AARCH64(_INS_LDRSW), CS_AARCH64(_INS_LDRSB), CS_AARCH64(_INS_LDRSH), CS_AARCH64(_INS_LDURSW), CS_AARCH64(_INS_LDURSB), CS_AARCH64(_INS_LDURSH), - * CS_AARCH64(_INS_LDAPR), CS_AARCH64(_INS_LDAPRB), CS_AARCH64(_INS_LDAPRH), CS_AARCH64(_INS_LDAPUR), CS_AARCH64(_INS_LDAPURB), CS_AARCH64(_INS_LDAPURH), - * CS_AARCH64(_INS_LDAPURSB), CS_AARCH64(_INS_LDAPURSH), CS_AARCH64(_INS_LDAPURSW), CS_AARCH64(_INS_LDAR), CS_AARCH64(_INS_LDARB), CS_AARCH64(_INS_LDARH), - * CS_AARCH64(_INS_LDAXP), CS_AARCH64(_INS_LDXP), CS_AARCH64(_INS_LDAXR), CS_AARCH64(_INS_LDAXRB), CS_AARCH64(_INS_LDAXRH), - * CS_AARCH64(_INS_LDLAR), CS_AARCH64(_INS_LDLARB), CS_AARCH64(_INS_LDLARH), - * CS_AARCH64(_INS_LDP), CS_AARCH64(_INS_LDNP), CS_AARCH64(_INS_LDPSW), - * CS_AARCH64(_INS_LDRAA), CS_AARCH64(_INS_LDRAB), - * CS_AARCH64(_INS_LDTR), CS_AARCH64(_INS_LDTRB), CS_AARCH64(_INS_LDTRH), CS_AARCH64(_INS_LDTRSW), CS_AARCH64(_INS_LDTRSB), CS_AARCH64(_INS_LDTRSH), - * CS_AARCH64(_INS_LDXR), CS_AARCH64(_INS_LDXRB), CS_AARCH64(_INS_LDXRH) + * Capstone: ARM64_INS_LDR, ARM64_INS_LDRB, ARM64_INS_LDRH, ARM64_INS_LDRU, ARM64_INS_LDRUB, ARM64_INS_LDRUH, + * ARM64_INS_LDRSW, ARM64_INS_LDRSB, ARM64_INS_LDRSH, ARM64_INS_LDURSW, ARM64_INS_LDURSB, ARM64_INS_LDURSH, + * ARM64_INS_LDAPR, ARM64_INS_LDAPRB, ARM64_INS_LDAPRH, ARM64_INS_LDAPUR, ARM64_INS_LDAPURB, ARM64_INS_LDAPURH, + * ARM64_INS_LDAPURSB, ARM64_INS_LDAPURSH, ARM64_INS_LDAPURSW, ARM64_INS_LDAR, ARM64_INS_LDARB, ARM64_INS_LDARH, + * ARM64_INS_LDAXP, ARM64_INS_LDXP, ARM64_INS_LDAXR, ARM64_INS_LDAXRB, ARM64_INS_LDAXRH, + * ARM64_INS_LDLAR, ARM64_INS_LDLARB, ARM64_INS_LDLARH, + * ARM64_INS_LDP, ARM64_INS_LDNP, ARM64_INS_LDPSW, + * ARM64_INS_LDRAA, ARM64_INS_LDRAB, + * ARM64_INS_LDTR, ARM64_INS_LDTRB, ARM64_INS_LDTRH, ARM64_INS_LDTRSW, ARM64_INS_LDTRSB, ARM64_INS_LDTRSH, + * ARM64_INS_LDXR, ARM64_INS_LDXRB, ARM64_INS_LDXRH * ARM: ldr, ldrb, ldrh, ldru, ldrub, ldruh, ldrsw, ldrsb, ldrsh, ldursw, ldurwb, ldursh, * ldapr, ldaprb, ldaprh, ldapur, ldapurb, ldapurh, ldapursb, ldapursh, ldapursw, * ldaxp, ldxp, ldaxr, ldaxrb, ldaxrh, ldar, ldarb, ldarh, @@ -1169,8 +1176,8 @@ static RzILOpEffect *ldr(cs_insn *insn) { if (!ISREG(0)) { return NULL; } - bool pair = insn->id == CS_AARCH64(_INS_LDAXP) || insn->id == CS_AARCH64(_INS_LDXP) || - insn->id == CS_AARCH64(_INS_LDP) || insn->id == CS_AARCH64(_INS_LDNP) || insn->id == CS_AARCH64(_INS_LDPSW); + bool pair = insn->id == ARM64_INS_LDAXP || insn->id == ARM64_INS_LDXP || + insn->id == ARM64_INS_LDP || insn->id == ARM64_INS_LDNP || insn->id == ARM64_INS_LDPSW; if (pair && !ISREG(1)) { return NULL; } @@ -1180,65 +1187,65 @@ static RzILOpEffect *ldr(cs_insn *insn) { if (!addr) { return NULL; } - CS_aarch64_reg() dst_reg = REGID(0); + arm64_reg dst_reg = REGID(0); ut64 loadsz; bool is_signed = false; switch (insn->id) { - case CS_AARCH64(_INS_LDRSB): - case CS_AARCH64(_INS_LDURSB): - case CS_AARCH64(_INS_LDTRSB): + case ARM64_INS_LDRSB: + case ARM64_INS_LDURSB: + case ARM64_INS_LDTRSB: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDAPURSB): + case ARM64_INS_LDAPURSB: #endif is_signed = true; // fallthrough - case CS_AARCH64(_INS_LDRB): - case CS_AARCH64(_INS_LDURB): - case CS_AARCH64(_INS_LDARB): - case CS_AARCH64(_INS_LDAXRB): - case CS_AARCH64(_INS_LDTRB): - case CS_AARCH64(_INS_LDXRB): + case ARM64_INS_LDRB: + case ARM64_INS_LDURB: + case ARM64_INS_LDARB: + case ARM64_INS_LDAXRB: + case ARM64_INS_LDTRB: + case ARM64_INS_LDXRB: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDLARB): - case CS_AARCH64(_INS_LDAPRB): - case CS_AARCH64(_INS_LDAPURB): + case ARM64_INS_LDLARB: + case ARM64_INS_LDAPRB: + case ARM64_INS_LDAPURB: #endif loadsz = 8; break; - case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDURSH): - case CS_AARCH64(_INS_LDTRSH): + case ARM64_INS_LDRSH: + case ARM64_INS_LDURSH: + case ARM64_INS_LDTRSH: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDAPURSH): + case ARM64_INS_LDAPURSH: #endif is_signed = true; // fallthrough - case CS_AARCH64(_INS_LDRH): - case CS_AARCH64(_INS_LDURH): - case CS_AARCH64(_INS_LDARH): - case CS_AARCH64(_INS_LDAXRH): - case CS_AARCH64(_INS_LDTRH): - case CS_AARCH64(_INS_LDXRH): + case ARM64_INS_LDRH: + case ARM64_INS_LDURH: + case ARM64_INS_LDARH: + case ARM64_INS_LDAXRH: + case ARM64_INS_LDTRH: + case ARM64_INS_LDXRH: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDAPRH): - case CS_AARCH64(_INS_LDAPURH): - case CS_AARCH64(_INS_LDLARH): + case ARM64_INS_LDAPRH: + case ARM64_INS_LDAPURH: + case ARM64_INS_LDLARH: #endif loadsz = 16; break; - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDURSW): - case CS_AARCH64(_INS_LDPSW): - case CS_AARCH64(_INS_LDTRSW): + case ARM64_INS_LDRSW: + case ARM64_INS_LDURSW: + case ARM64_INS_LDPSW: + case ARM64_INS_LDTRSW: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDAPURSW): + case ARM64_INS_LDAPURSW: #endif is_signed = true; loadsz = 32; break; default: - // CS_AARCH64(_INS_LDR), CS_AARCH64(_INS_LDRU), CS_AARCH64(_INS_LDAPR), CS_AARCH64(_INS_LDAPUR), CS_AARCH64(_INS_LDAR), CS_AARCH64(_INS_LDAXR), CS_AARCH64(_INS_LDLAR), - // CS_AARCH64(_INS_LDP), CS_AARCH64(_INS_LDNP), CS_AARCH64(_INS_LDRAA), CS_AARCH64(_INS_LDRAB), CS_AARCH64(_INS_LDTR), CS_AARCH64(_INS_LDXR) + // ARM64_INS_LDR, ARM64_INS_LDRU, ARM64_INS_LDAPR, ARM64_INS_LDAPUR, ARM64_INS_LDAR, ARM64_INS_LDAXR, ARM64_INS_LDLAR, + // ARM64_INS_LDP, ARM64_INS_LDNP, ARM64_INS_LDRAA, ARM64_INS_LDRAB, ARM64_INS_LDTR, ARM64_INS_LDXR loadsz = is_wreg(dst_reg) ? 32 : 64; break; } @@ -1268,11 +1275,11 @@ static RzILOpEffect *ldr(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_STR), CS_AARCH64(_INS_STUR), CS_AARCH64(_INS_STRB), CS_AARCH64(_INS_STURB), CS_AARCH64(_INS_STRH), CS_AARCH64(_INS_STURH), - * CS_AARCH64(_INS_STLLR), CS_AARCH64(_INS_STLLRB), CS_AARCH64(_INS_STLLRH), CS_AARCH64(_INS_STLR), CS_AARCH64(_INS_STLRB), CS_AARCH64(_INS_STLRH), - * CS_AARCH64(_INS_STLUR), CS_AARCH64(_INS_STLURB), CS_AARCH64(_INS_STLURH), CS_AARCH64(_INS_STP), CS_AARCH64(_INS_STXR), CS_AARCH64(_INS_STXRB), - * CS_AARCH64(_INS_STXRH), CS_AARCH64(_INS_STXP), CS_AARCH64(_INS_STLXR), CS_AARCH64(_INS_STLXRB). CS_AARCH64(_INS_STLXRH), CS_AARCH64(_INS_STLXP), - * CS_AARCH64(_INS_STNP), CS_AARCH64(_INS_STTR), CS_AARCH64(_INS_STTRB), CS_AARCH64(_INS_STTRH) + * Capstone: ARM64_INS_STR, ARM64_INS_STUR, ARM64_INS_STRB, ARM64_INS_STURB, ARM64_INS_STRH, ARM64_INS_STURH, + * ARM64_INS_STLLR, ARM64_INS_STLLRB, ARM64_INS_STLLRH, ARM64_INS_STLR, ARM64_INS_STLRB, ARM64_INS_STLRH, + * ARM64_INS_STLUR, ARM64_INS_STLURB, ARM64_INS_STLURH, ARM64_INS_STP, ARM64_INS_STXR, ARM64_INS_STXRB, + * ARM64_INS_STXRH, ARM64_INS_STXP, ARM64_INS_STLXR, ARM64_INS_STLXRB. ARM64_INS_STLXRH, ARM64_INS_STLXP, + * ARM64_INS_STNP, ARM64_INS_STTR, ARM64_INS_STTRB, ARM64_INS_STTRH * ARM: str, stur, strb, sturb, strh, sturh, stllr, stllrb, stllrh, stlr, stlrb, stlrh, stlur, stlurb, stlurh, stp, stxr, stxrb, * stxrh, stxp, stlxr, stlxrb. stlxrh, stlxp, stnp, sttr, sttrb, sttrh */ @@ -1280,9 +1287,9 @@ static RzILOpEffect *str(cs_insn *insn) { if (!ISREG(0) || !REGBITS(0)) { return NULL; } - bool result = insn->id == CS_AARCH64(_INS_STXR) || insn->id == CS_AARCH64(_INS_STXRB) || insn->id == CS_AARCH64(_INS_STXRH) || insn->id == CS_AARCH64(_INS_STXP) || - insn->id == CS_AARCH64(_INS_STLXR) || insn->id == CS_AARCH64(_INS_STLXRB) || insn->id == CS_AARCH64(_INS_STLXRH) || insn->id == CS_AARCH64(_INS_STLXP); - bool pair = insn->id == CS_AARCH64(_INS_STP) || insn->id == CS_AARCH64(_INS_STNP) || insn->id == CS_AARCH64(_INS_STXP) || insn->id == CS_AARCH64(_INS_STLXP); + bool result = insn->id == ARM64_INS_STXR || insn->id == ARM64_INS_STXRB || insn->id == ARM64_INS_STXRH || insn->id == ARM64_INS_STXP || + insn->id == ARM64_INS_STLXR || insn->id == ARM64_INS_STLXRB || insn->id == ARM64_INS_STLXRH || insn->id == ARM64_INS_STLXP; + bool pair = insn->id == ARM64_INS_STP || insn->id == ARM64_INS_STNP || insn->id == ARM64_INS_STXP || insn->id == ARM64_INS_STLXP; size_t src_op = result ? 1 : 0; size_t addr_op = (result ? 1 : 0) + 1 + (pair ? 1 : 0); ut32 addr_bits = 64; @@ -1292,33 +1299,33 @@ static RzILOpEffect *str(cs_insn *insn) { } ut32 bits; switch (insn->id) { - case CS_AARCH64(_INS_STRB): - case CS_AARCH64(_INS_STURB): - case CS_AARCH64(_INS_STLRB): - case CS_AARCH64(_INS_STXRB): - case CS_AARCH64(_INS_STLXRB): - case CS_AARCH64(_INS_STTRB): + case ARM64_INS_STRB: + case ARM64_INS_STURB: + case ARM64_INS_STLRB: + case ARM64_INS_STXRB: + case ARM64_INS_STLXRB: + case ARM64_INS_STTRB: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_STLLRB): - case CS_AARCH64(_INS_STLURB): + case ARM64_INS_STLLRB: + case ARM64_INS_STLURB: #endif bits = 8; break; - case CS_AARCH64(_INS_STRH): - case CS_AARCH64(_INS_STURH): - case CS_AARCH64(_INS_STLRH): - case CS_AARCH64(_INS_STXRH): - case CS_AARCH64(_INS_STLXRH): - case CS_AARCH64(_INS_STTRH): + case ARM64_INS_STRH: + case ARM64_INS_STURH: + case ARM64_INS_STLRH: + case ARM64_INS_STXRH: + case ARM64_INS_STLXRH: + case ARM64_INS_STTRH: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_STLLRH): - case CS_AARCH64(_INS_STLURH): + case ARM64_INS_STLLRH: + case ARM64_INS_STLURH: #endif bits = 16; break; default: - // CS_AARCH64(_INS_STR), CS_AARCH64(_INS_STUR), CS_AARCH64(_INS_STLLR), CS_AARCH64(_INS_STLR), CS_AARCH64(_INS_STLUR), CS_AARCH64(_INS_STP), - // CS_AARCH64(_INS_STXR), CS_AARCH64(_INS_STXP), CS_AARCH64(_INS_STLXR), CS_AARCH64(_INS_STLXP), CS_AARCH64(_INS_STNP), CS_AARCH64(_INS_STTR) + // ARM64_INS_STR, ARM64_INS_STUR, ARM64_INS_STLLR, ARM64_INS_STLR, ARM64_INS_STLUR, ARM64_INS_STP, + // ARM64_INS_STXR, ARM64_INS_STXP, ARM64_INS_STLXR, ARM64_INS_STLXP, ARM64_INS_STNP, ARM64_INS_STTR bits = REGBITS(src_op); if (!bits) { rz_il_op_pure_free(addr); @@ -1363,34 +1370,34 @@ static RzILOpEffect *str(cs_insn *insn) { #if CS_API_MAJOR > 4 /** - * Capstone: CS_AARCH64(_INS_LDADD), CS_AARCH64(_INS_LDADDA), CS_AARCH64(_INS_LDADDAL), CS_AARCH64(_INS_LDADDL), - * CS_AARCH64(_INS_LDADDB), CS_AARCH64(_INS_LDADDAB), CS_AARCH64(_INS_LDADDALB), CS_AARCH64(_INS_LDADDLB), - * CS_AARCH64(_INS_LDADDH), CS_AARCH64(_INS_LDADDAH), CS_AARCH64(_INS_LDADDALH), CS_AARCH64(_INS_LDADDLH), - * CS_AARCH64(_INS_STADD), CS_AARCH64(_INS_STADDL), CS_AARCH64(_INS_STADDB), CS_AARCH64(_INS_STADDLB), CS_AARCH64(_INS_STADDH), CS_AARCH64(_INS_STADDLH), - * CS_AARCH64(_INS_LDCLRB), CS_AARCH64(_INS_LDCLRAB), CS_AARCH64(_INS_LDCLRALB), CS_AARCH64(_INS_LDCLRLB), - * CS_AARCH64(_INS_LDCLRH), CS_AARCH64(_INS_LDCLRAH), CS_AARCH64(_INS_LDCLRALH), CS_AARCH64(_INS_LDCLRLH) - * CS_AARCH64(_INS_LDCLR), CS_AARCH64(_INS_LDCLRA), CS_AARCH64(_INS_LDCLRAL), CS_AARCH64(_INS_LDCLRL), - * CS_AARCH64(_INS_STSETB), CS_AARCH64(_INS_STSETLB), CS_AARCH64(_INS_STSETH), CS_AARCH64(_INS_STSETLH), CS_AARCH64(_INS_STSET), CS_AARCH64(_INS_STSETL), - * CS_AARCH64(_INS_LDSETB), CS_AARCH64(_INS_LDSETAB), CS_AARCH64(_INS_LDSETALB), CS_AARCH64(_INS_LDSETLB), - * CS_AARCH64(_INS_LDSETH), CS_AARCH64(_INS_LDSETAH), CS_AARCH64(_INS_LDSETALH), CS_AARCH64(_INS_LDSETLH) - * CS_AARCH64(_INS_LDSET), CS_AARCH64(_INS_LDSETA), CS_AARCH64(_INS_LDSETAL), CS_AARCH64(_INS_LDSETL), - * CS_AARCH64(_INS_STSETB), CS_AARCH64(_INS_STSETLB), CS_AARCH64(_INS_STSETH), CS_AARCH64(_INS_STSETLH), CS_AARCH64(_INS_STSET), CS_AARCH64(_INS_STSETL), - * CS_AARCH64(_INS_LDSMAXB), CS_AARCH64(_INS_LDSMAXAB), CS_AARCH64(_INS_LDSMAXALB), CS_AARCH64(_INS_LDSMAXLB), - * CS_AARCH64(_INS_LDSMAXH), CS_AARCH64(_INS_LDSMAXAH), CS_AARCH64(_INS_LDSMAXALH), CS_AARCH64(_INS_LDSMAXLH) - * CS_AARCH64(_INS_LDSMAX), CS_AARCH64(_INS_LDSMAXA), CS_AARCH64(_INS_LDSMAXAL), CS_AARCH64(_INS_LDSMAXL), - * CS_AARCH64(_INS_STSMAXB), CS_AARCH64(_INS_STSMAXLB), CS_AARCH64(_INS_STSMAXH), CS_AARCH64(_INS_STSMAXLH), CS_AARCH64(_INS_STSMAX), CS_AARCH64(_INS_STSMAXL), - * CS_AARCH64(_INS_LDSMINB), CS_AARCH64(_INS_LDSMINAB), CS_AARCH64(_INS_LDSMINALB), CS_AARCH64(_INS_LDSMINLB), - * CS_AARCH64(_INS_LDSMINH), CS_AARCH64(_INS_LDSMINAH), CS_AARCH64(_INS_LDSMINALH), CS_AARCH64(_INS_LDSMINLH) - * CS_AARCH64(_INS_LDSMIN), CS_AARCH64(_INS_LDSMINA), CS_AARCH64(_INS_LDSMINAL), CS_AARCH64(_INS_LDSMINL), - * CS_AARCH64(_INS_STSMINB), CS_AARCH64(_INS_STSMINLB), CS_AARCH64(_INS_STSMINH), CS_AARCH64(_INS_STSMINLH), CS_AARCH64(_INS_STSMIN), CS_AARCH64(_INS_STSMINL), - * CS_AARCH64(_INS_LDUMAXB), CS_AARCH64(_INS_LDUMAXAB), CS_AARCH64(_INS_LDUMAXALB), CS_AARCH64(_INS_LDUMAXLB), - * CS_AARCH64(_INS_LDUMAXH), CS_AARCH64(_INS_LDUMAXAH), CS_AARCH64(_INS_LDUMAXALH), CS_AARCH64(_INS_LDUMAXLH) - * CS_AARCH64(_INS_LDUMAX), CS_AARCH64(_INS_LDUMAXA), CS_AARCH64(_INS_LDUMAXAL), CS_AARCH64(_INS_LDUMAXL), - * CS_AARCH64(_INS_STUMAXB), CS_AARCH64(_INS_STUMAXLB), CS_AARCH64(_INS_STUMAXH), CS_AARCH64(_INS_STUMAXLH), CS_AARCH64(_INS_STUMAX), CS_AARCH64(_INS_STUMAXL), - * CS_AARCH64(_INS_LDUMINB), CS_AARCH64(_INS_LDUMINAB), CS_AARCH64(_INS_LDUMINALB), CS_AARCH64(_INS_LDUMINLB), - * CS_AARCH64(_INS_LDUMINH), CS_AARCH64(_INS_LDUMINAH), CS_AARCH64(_INS_LDUMINALH), CS_AARCH64(_INS_LDUMINLH) - * CS_AARCH64(_INS_LDUMIN), CS_AARCH64(_INS_LDUMINA), CS_AARCH64(_INS_LDUMINAL), CS_AARCH64(_INS_LDUMINL), - * CS_AARCH64(_INS_STUMINB), CS_AARCH64(_INS_STUMINLB), CS_AARCH64(_INS_STUMINH), CS_AARCH64(_INS_STUMINLH), CS_AARCH64(_INS_STUMIN), CS_AARCH64(_INS_STUMINL) + * Capstone: ARM64_INS_LDADD, ARM64_INS_LDADDA, ARM64_INS_LDADDAL, ARM64_INS_LDADDL, + * ARM64_INS_LDADDB, ARM64_INS_LDADDAB, ARM64_INS_LDADDALB, ARM64_INS_LDADDLB, + * ARM64_INS_LDADDH, ARM64_INS_LDADDAH, ARM64_INS_LDADDALH, ARM64_INS_LDADDLH, + * ARM64_INS_STADD, ARM64_INS_STADDL, ARM64_INS_STADDB, ARM64_INS_STADDLB, ARM64_INS_STADDH, ARM64_INS_STADDLH, + * ARM64_INS_LDCLRB, ARM64_INS_LDCLRAB, ARM64_INS_LDCLRALB, ARM64_INS_LDCLRLB, + * ARM64_INS_LDCLRH, ARM64_INS_LDCLRAH, ARM64_INS_LDCLRALH, ARM64_INS_LDCLRLH + * ARM64_INS_LDCLR, ARM64_INS_LDCLRA, ARM64_INS_LDCLRAL, ARM64_INS_LDCLRL, + * ARM64_INS_STSETB, ARM64_INS_STSETLB, ARM64_INS_STSETH, ARM64_INS_STSETLH, ARM64_INS_STSET, ARM64_INS_STSETL, + * ARM64_INS_LDSETB, ARM64_INS_LDSETAB, ARM64_INS_LDSETALB, ARM64_INS_LDSETLB, + * ARM64_INS_LDSETH, ARM64_INS_LDSETAH, ARM64_INS_LDSETALH, ARM64_INS_LDSETLH + * ARM64_INS_LDSET, ARM64_INS_LDSETA, ARM64_INS_LDSETAL, ARM64_INS_LDSETL, + * ARM64_INS_STSETB, ARM64_INS_STSETLB, ARM64_INS_STSETH, ARM64_INS_STSETLH, ARM64_INS_STSET, ARM64_INS_STSETL, + * ARM64_INS_LDSMAXB, ARM64_INS_LDSMAXAB, ARM64_INS_LDSMAXALB, ARM64_INS_LDSMAXLB, + * ARM64_INS_LDSMAXH, ARM64_INS_LDSMAXAH, ARM64_INS_LDSMAXALH, ARM64_INS_LDSMAXLH + * ARM64_INS_LDSMAX, ARM64_INS_LDSMAXA, ARM64_INS_LDSMAXAL, ARM64_INS_LDSMAXL, + * ARM64_INS_STSMAXB, ARM64_INS_STSMAXLB, ARM64_INS_STSMAXH, ARM64_INS_STSMAXLH, ARM64_INS_STSMAX, ARM64_INS_STSMAXL, + * ARM64_INS_LDSMINB, ARM64_INS_LDSMINAB, ARM64_INS_LDSMINALB, ARM64_INS_LDSMINLB, + * ARM64_INS_LDSMINH, ARM64_INS_LDSMINAH, ARM64_INS_LDSMINALH, ARM64_INS_LDSMINLH + * ARM64_INS_LDSMIN, ARM64_INS_LDSMINA, ARM64_INS_LDSMINAL, ARM64_INS_LDSMINL, + * ARM64_INS_STSMINB, ARM64_INS_STSMINLB, ARM64_INS_STSMINH, ARM64_INS_STSMINLH, ARM64_INS_STSMIN, ARM64_INS_STSMINL, + * ARM64_INS_LDUMAXB, ARM64_INS_LDUMAXAB, ARM64_INS_LDUMAXALB, ARM64_INS_LDUMAXLB, + * ARM64_INS_LDUMAXH, ARM64_INS_LDUMAXAH, ARM64_INS_LDUMAXALH, ARM64_INS_LDUMAXLH + * ARM64_INS_LDUMAX, ARM64_INS_LDUMAXA, ARM64_INS_LDUMAXAL, ARM64_INS_LDUMAXL, + * ARM64_INS_STUMAXB, ARM64_INS_STUMAXLB, ARM64_INS_STUMAXH, ARM64_INS_STUMAXLH, ARM64_INS_STUMAX, ARM64_INS_STUMAXL, + * ARM64_INS_LDUMINB, ARM64_INS_LDUMINAB, ARM64_INS_LDUMINALB, ARM64_INS_LDUMINLB, + * ARM64_INS_LDUMINH, ARM64_INS_LDUMINAH, ARM64_INS_LDUMINALH, ARM64_INS_LDUMINLH + * ARM64_INS_LDUMIN, ARM64_INS_LDUMINA, ARM64_INS_LDUMINAL, ARM64_INS_LDUMINL, + * ARM64_INS_STUMINB, ARM64_INS_STUMINLB, ARM64_INS_STUMINH, ARM64_INS_STUMINLH, ARM64_INS_STUMIN, ARM64_INS_STUMINL * ARM: ldadd, ldadda, ldaddal, ldaddl, ldaddb, ldaddab, ldaddalb, ldaddlb, ldaddh, ldaddah, ldaddalh, ldaddlh, * stadd, staddl, staddb, staddlb, stadd, * ldclr, ldclra, ldclral, ldclrl, ldclrb, ldclrab, ldclralb, ldclrlb, ldclrh, ldclrah, ldclralh, ldclrlh, @@ -1411,7 +1418,7 @@ static RzILOpEffect *ldadd(cs_insn *insn) { if (!ISMEM(addr_op)) { return NULL; } - CS_aarch64_reg() addend_reg = REGID(0); + arm64_reg addend_reg = REGID(0); ut64 loadsz; enum { OP_ADD, @@ -1424,254 +1431,254 @@ static RzILOpEffect *ldadd(cs_insn *insn) { OP_UMIN } op = OP_ADD; switch (insn->id) { - case CS_AARCH64(_INS_LDCLRB): - case CS_AARCH64(_INS_LDCLRAB): - case CS_AARCH64(_INS_LDCLRALB): - case CS_AARCH64(_INS_LDCLRLB): + case ARM64_INS_LDCLRB: + case ARM64_INS_LDCLRAB: + case ARM64_INS_LDCLRALB: + case ARM64_INS_LDCLRLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STCLRB): - case CS_AARCH64(_INS_STCLRLB): + case ARM64_INS_STCLRB: + case ARM64_INS_STCLRLB: #endif op = OP_CLR; loadsz = 8; break; - case CS_AARCH64(_INS_LDEORB): - case CS_AARCH64(_INS_LDEORAB): - case CS_AARCH64(_INS_LDEORALB): - case CS_AARCH64(_INS_LDEORLB): + case ARM64_INS_LDEORB: + case ARM64_INS_LDEORAB: + case ARM64_INS_LDEORALB: + case ARM64_INS_LDEORLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STEORB): - case CS_AARCH64(_INS_STEORLB): + case ARM64_INS_STEORB: + case ARM64_INS_STEORLB: #endif op = OP_EOR; loadsz = 8; break; - case CS_AARCH64(_INS_LDSETB): - case CS_AARCH64(_INS_LDSETAB): - case CS_AARCH64(_INS_LDSETALB): - case CS_AARCH64(_INS_LDSETLB): + case ARM64_INS_LDSETB: + case ARM64_INS_LDSETAB: + case ARM64_INS_LDSETALB: + case ARM64_INS_LDSETLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSETB): - case CS_AARCH64(_INS_STSETLB): + case ARM64_INS_STSETB: + case ARM64_INS_STSETLB: #endif op = OP_SET; loadsz = 8; break; - case CS_AARCH64(_INS_LDSMAXB): - case CS_AARCH64(_INS_LDSMAXAB): - case CS_AARCH64(_INS_LDSMAXALB): - case CS_AARCH64(_INS_LDSMAXLB): + case ARM64_INS_LDSMAXB: + case ARM64_INS_LDSMAXAB: + case ARM64_INS_LDSMAXALB: + case ARM64_INS_LDSMAXLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMAXB): - case CS_AARCH64(_INS_STSMAXLB): + case ARM64_INS_STSMAXB: + case ARM64_INS_STSMAXLB: #endif op = OP_SMAX; loadsz = 8; break; - case CS_AARCH64(_INS_LDSMINB): - case CS_AARCH64(_INS_LDSMINAB): - case CS_AARCH64(_INS_LDSMINALB): - case CS_AARCH64(_INS_LDSMINLB): + case ARM64_INS_LDSMINB: + case ARM64_INS_LDSMINAB: + case ARM64_INS_LDSMINALB: + case ARM64_INS_LDSMINLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMINB): - case CS_AARCH64(_INS_STSMINLB): + case ARM64_INS_STSMINB: + case ARM64_INS_STSMINLB: #endif op = OP_SMIN; loadsz = 8; break; - case CS_AARCH64(_INS_LDUMAXB): - case CS_AARCH64(_INS_LDUMAXAB): - case CS_AARCH64(_INS_LDUMAXALB): - case CS_AARCH64(_INS_LDUMAXLB): + case ARM64_INS_LDUMAXB: + case ARM64_INS_LDUMAXAB: + case ARM64_INS_LDUMAXALB: + case ARM64_INS_LDUMAXLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMAXB): - case CS_AARCH64(_INS_STUMAXLB): + case ARM64_INS_STUMAXB: + case ARM64_INS_STUMAXLB: #endif op = OP_UMAX; loadsz = 8; break; - case CS_AARCH64(_INS_LDUMINB): - case CS_AARCH64(_INS_LDUMINAB): - case CS_AARCH64(_INS_LDUMINALB): - case CS_AARCH64(_INS_LDUMINLB): + case ARM64_INS_LDUMINB: + case ARM64_INS_LDUMINAB: + case ARM64_INS_LDUMINALB: + case ARM64_INS_LDUMINLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMINB): - case CS_AARCH64(_INS_STUMINLB): + case ARM64_INS_STUMINB: + case ARM64_INS_STUMINLB: #endif op = OP_UMIN; loadsz = 8; break; - case CS_AARCH64(_INS_LDADDB): - case CS_AARCH64(_INS_LDADDAB): - case CS_AARCH64(_INS_LDADDALB): - case CS_AARCH64(_INS_LDADDLB): + case ARM64_INS_LDADDB: + case ARM64_INS_LDADDAB: + case ARM64_INS_LDADDALB: + case ARM64_INS_LDADDLB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STADDB): - case CS_AARCH64(_INS_STADDLB): + case ARM64_INS_STADDB: + case ARM64_INS_STADDLB: #endif loadsz = 8; break; - case CS_AARCH64(_INS_LDCLRH): - case CS_AARCH64(_INS_LDCLRAH): - case CS_AARCH64(_INS_LDCLRALH): - case CS_AARCH64(_INS_LDCLRLH): + case ARM64_INS_LDCLRH: + case ARM64_INS_LDCLRAH: + case ARM64_INS_LDCLRALH: + case ARM64_INS_LDCLRLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STCLRH): - case CS_AARCH64(_INS_STCLRLH): + case ARM64_INS_STCLRH: + case ARM64_INS_STCLRLH: #endif op = OP_CLR; loadsz = 16; break; - case CS_AARCH64(_INS_LDEORH): - case CS_AARCH64(_INS_LDEORAH): - case CS_AARCH64(_INS_LDEORALH): - case CS_AARCH64(_INS_LDEORLH): + case ARM64_INS_LDEORH: + case ARM64_INS_LDEORAH: + case ARM64_INS_LDEORALH: + case ARM64_INS_LDEORLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STEORH): - case CS_AARCH64(_INS_STEORLH): + case ARM64_INS_STEORH: + case ARM64_INS_STEORLH: #endif op = OP_EOR; loadsz = 16; break; - case CS_AARCH64(_INS_LDSETH): - case CS_AARCH64(_INS_LDSETAH): - case CS_AARCH64(_INS_LDSETALH): - case CS_AARCH64(_INS_LDSETLH): + case ARM64_INS_LDSETH: + case ARM64_INS_LDSETAH: + case ARM64_INS_LDSETALH: + case ARM64_INS_LDSETLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSETH): - case CS_AARCH64(_INS_STSETLH): + case ARM64_INS_STSETH: + case ARM64_INS_STSETLH: #endif op = OP_SET; loadsz = 16; break; - case CS_AARCH64(_INS_LDSMAXH): - case CS_AARCH64(_INS_LDSMAXAH): - case CS_AARCH64(_INS_LDSMAXALH): - case CS_AARCH64(_INS_LDSMAXLH): + case ARM64_INS_LDSMAXH: + case ARM64_INS_LDSMAXAH: + case ARM64_INS_LDSMAXALH: + case ARM64_INS_LDSMAXLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMAXH): - case CS_AARCH64(_INS_STSMAXLH): + case ARM64_INS_STSMAXH: + case ARM64_INS_STSMAXLH: #endif op = OP_SMAX; loadsz = 16; break; - case CS_AARCH64(_INS_LDSMINH): - case CS_AARCH64(_INS_LDSMINAH): - case CS_AARCH64(_INS_LDSMINALH): - case CS_AARCH64(_INS_LDSMINLH): + case ARM64_INS_LDSMINH: + case ARM64_INS_LDSMINAH: + case ARM64_INS_LDSMINALH: + case ARM64_INS_LDSMINLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMINH): - case CS_AARCH64(_INS_STSMINLH): + case ARM64_INS_STSMINH: + case ARM64_INS_STSMINLH: #endif op = OP_SMIN; loadsz = 16; break; - case CS_AARCH64(_INS_LDUMAXH): - case CS_AARCH64(_INS_LDUMAXAH): - case CS_AARCH64(_INS_LDUMAXALH): - case CS_AARCH64(_INS_LDUMAXLH): + case ARM64_INS_LDUMAXH: + case ARM64_INS_LDUMAXAH: + case ARM64_INS_LDUMAXALH: + case ARM64_INS_LDUMAXLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMAXH): - case CS_AARCH64(_INS_STUMAXLH): + case ARM64_INS_STUMAXH: + case ARM64_INS_STUMAXLH: #endif op = OP_UMAX; loadsz = 16; break; - case CS_AARCH64(_INS_LDUMINH): - case CS_AARCH64(_INS_LDUMINAH): - case CS_AARCH64(_INS_LDUMINALH): - case CS_AARCH64(_INS_LDUMINLH): + case ARM64_INS_LDUMINH: + case ARM64_INS_LDUMINAH: + case ARM64_INS_LDUMINALH: + case ARM64_INS_LDUMINLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMINH): - case CS_AARCH64(_INS_STUMINLH): + case ARM64_INS_STUMINH: + case ARM64_INS_STUMINLH: #endif op = OP_UMIN; loadsz = 16; break; - case CS_AARCH64(_INS_LDADDH): - case CS_AARCH64(_INS_LDADDAH): - case CS_AARCH64(_INS_LDADDALH): - case CS_AARCH64(_INS_LDADDLH): + case ARM64_INS_LDADDH: + case ARM64_INS_LDADDAH: + case ARM64_INS_LDADDALH: + case ARM64_INS_LDADDLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STADDH): - case CS_AARCH64(_INS_STADDLH): + case ARM64_INS_STADDH: + case ARM64_INS_STADDLH: #endif loadsz = 16; break; - case CS_AARCH64(_INS_LDCLR): - case CS_AARCH64(_INS_LDCLRA): - case CS_AARCH64(_INS_LDCLRAL): - case CS_AARCH64(_INS_LDCLRL): + case ARM64_INS_LDCLR: + case ARM64_INS_LDCLRA: + case ARM64_INS_LDCLRAL: + case ARM64_INS_LDCLRL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STCLR): - case CS_AARCH64(_INS_STCLRL): + case ARM64_INS_STCLR: + case ARM64_INS_STCLRL: #endif op = OP_CLR; goto size_from_reg; - case CS_AARCH64(_INS_LDEOR): - case CS_AARCH64(_INS_LDEORA): - case CS_AARCH64(_INS_LDEORAL): - case CS_AARCH64(_INS_LDEORL): + case ARM64_INS_LDEOR: + case ARM64_INS_LDEORA: + case ARM64_INS_LDEORAL: + case ARM64_INS_LDEORL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STEOR): - case CS_AARCH64(_INS_STEORL): + case ARM64_INS_STEOR: + case ARM64_INS_STEORL: #endif op = OP_EOR; goto size_from_reg; - case CS_AARCH64(_INS_LDSET): - case CS_AARCH64(_INS_LDSETA): - case CS_AARCH64(_INS_LDSETAL): - case CS_AARCH64(_INS_LDSETL): + case ARM64_INS_LDSET: + case ARM64_INS_LDSETA: + case ARM64_INS_LDSETAL: + case ARM64_INS_LDSETL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSET): - case CS_AARCH64(_INS_STSETL): + case ARM64_INS_STSET: + case ARM64_INS_STSETL: #endif op = OP_SET; goto size_from_reg; - case CS_AARCH64(_INS_LDSMAX): - case CS_AARCH64(_INS_LDSMAXA): - case CS_AARCH64(_INS_LDSMAXAL): - case CS_AARCH64(_INS_LDSMAXL): + case ARM64_INS_LDSMAX: + case ARM64_INS_LDSMAXA: + case ARM64_INS_LDSMAXAL: + case ARM64_INS_LDSMAXL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMAX): - case CS_AARCH64(_INS_STSMAXL): + case ARM64_INS_STSMAX: + case ARM64_INS_STSMAXL: #endif op = OP_SMAX; goto size_from_reg; - case CS_AARCH64(_INS_LDSMIN): - case CS_AARCH64(_INS_LDSMINA): - case CS_AARCH64(_INS_LDSMINAL): - case CS_AARCH64(_INS_LDSMINL): + case ARM64_INS_LDSMIN: + case ARM64_INS_LDSMINA: + case ARM64_INS_LDSMINAL: + case ARM64_INS_LDSMINL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMIN): - case CS_AARCH64(_INS_STSMINL): + case ARM64_INS_STSMIN: + case ARM64_INS_STSMINL: #endif op = OP_SMIN; goto size_from_reg; - case CS_AARCH64(_INS_LDUMAX): - case CS_AARCH64(_INS_LDUMAXA): - case CS_AARCH64(_INS_LDUMAXAL): - case CS_AARCH64(_INS_LDUMAXL): + case ARM64_INS_LDUMAX: + case ARM64_INS_LDUMAXA: + case ARM64_INS_LDUMAXAL: + case ARM64_INS_LDUMAXL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMAX): - case CS_AARCH64(_INS_STUMAXL): + case ARM64_INS_STUMAX: + case ARM64_INS_STUMAXL: #endif op = OP_UMAX; goto size_from_reg; - case CS_AARCH64(_INS_LDUMIN): - case CS_AARCH64(_INS_LDUMINA): - case CS_AARCH64(_INS_LDUMINAL): - case CS_AARCH64(_INS_LDUMINL): + case ARM64_INS_LDUMIN: + case ARM64_INS_LDUMINA: + case ARM64_INS_LDUMINAL: + case ARM64_INS_LDUMINL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMIN): - case CS_AARCH64(_INS_STUMINL): + case ARM64_INS_STUMIN: + case ARM64_INS_STUMINL: #endif op = OP_UMIN; // fallthrough size_from_reg: - default: // CS_AARCH64(_INS_LDADD), CS_AARCH64(_INS_LDADDA), CS_AARCH64(_INS_LDADDAL), CS_AARCH64(_INS_LDADDL), CS_AARCH64(_INS_STADD), CS_AARCH64(_INS_STADDL) + default: // ARM64_INS_LDADD, ARM64_INS_LDADDA, ARM64_INS_LDADDAL, ARM64_INS_LDADDL, ARM64_INS_STADD, ARM64_INS_STADDL loadsz = is_wreg(addend_reg) ? 32 : 64; break; } @@ -1688,7 +1695,7 @@ static RzILOpEffect *ldadd(cs_insn *insn) { rz_il_op_pure_free(addr); return NULL; } - CS_aarch64_reg() dst_reg = REGID(1); + arm64_reg dst_reg = REGID(1); dst_reg = xreg_of_reg(dst_reg); ld_eff = write_reg(dst_reg, loadsz != 64 ? UNSIGNED(64, VARL("old")) : VARL("old")); if (!ld_eff) { @@ -1741,7 +1748,7 @@ static RzILOpEffect *ldadd(cs_insn *insn) { #endif /** - * Capstone: CS_AARCH64(_INS_MADD), CS_AARCH64(_INS_MSUB) + * Capstone: ARM64_INS_MADD, ARM64_INS_MSUB * ARM: madd, msub */ static RzILOpEffect *madd(cs_insn *insn) { @@ -1759,7 +1766,7 @@ static RzILOpEffect *madd(cs_insn *insn) { return NULL; } RzILOpBitVector *res; - if (insn->id == CS_AARCH64(_INS_MSUB)) { + if (insn->id == ARM64_INS_MSUB) { res = SUB(addend, MUL(ma, mb)); } else { res = ADD(MUL(ma, mb), addend); @@ -1768,7 +1775,7 @@ static RzILOpEffect *madd(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_MUL), CS_AARCH64(_INS_MNEG) + * Capstone: ARM64_INS_MUL, ARM64_INS_MNEG * ARM: mul, mneg */ static RzILOpEffect *mul(cs_insn *insn) { @@ -1788,11 +1795,11 @@ static RzILOpEffect *mul(cs_insn *insn) { } RzILOpBitVector *res = MUL(ma, mb); #if CS_NEXT_VERSION < 6 - if (insn->id == CS_AARCH64(_INS_MNEG)) { + if (insn->id == ARM64_INS_MNEG) { res = NEG(res); } #else - if (insn->alias_id == AArch64_INS_ALIAS_MNEG) { + if (insn->alias_id == AARCH64_INS_ALIAS_MNEG) { res = NEG(res); } #endif @@ -1802,7 +1809,7 @@ static RzILOpEffect *mul(cs_insn *insn) { static RzILOpEffect *movn(cs_insn *insn); /** - * Capstone: CS_AARCH64(_INS_MOV), CS_AARCH64(_INS_MOVZ) + * Capstone: ARM64_INS_MOV, ARM64_INS_MOVZ * ARM: mov, movz */ static RzILOpEffect *mov(cs_insn *insn) { @@ -1824,8 +1831,8 @@ static RzILOpEffect *mov(cs_insn *insn) { RzILOpBitVector *src = ARG(1, &bits); #else RzILOpBitVector *src = NULL; - if ((insn->alias_id == AArch64_INS_ALIAS_MOV || insn->alias_id == AArch64_INS_ALIAS_MOVZ) && - (REGID(1) == AArch64_REG_XZR || REGID(1) == AArch64_REG_WZR)) { + if ((insn->alias_id == AARCH64_INS_ALIAS_MOV || insn->alias_id == AARCH64_INS_ALIAS_MOVZ) && + (REGID(1) == AARCH64_REG_XZR || REGID(1) == AARCH64_REG_WZR)) { // Sometimes regs are ORed with the zero register for the MOV alias. // Sometimes not. src = ARG(2, &bits); @@ -1840,7 +1847,7 @@ static RzILOpEffect *mov(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_MOVK) + * Capstone: ARM64_INS_MOVK * ARM: movk */ static RzILOpEffect *movk(cs_insn *insn) { @@ -1852,13 +1859,13 @@ static RzILOpEffect *movk(cs_insn *insn) { if (!src) { return NULL; } - CS_aarch64_op() *op = &insn->detail->CS_aarch64_.operands[1]; - ut32 shift = op->shift.type == CS_AARCH64(_SFT_LSL) ? op->shift.value : 0; + cs_arm64_op *op = &insn->detail->arm64.operands[1]; + ut32 shift = op->shift.type == ARM64_SFT_LSL ? op->shift.value : 0; return write_reg(REGID(0), LOGOR(LOGAND(src, UN(bits, ~(0xffffull << shift))), UN(bits, ((ut64)op->imm) << shift))); } /** - * Capstone: CS_AARCH64(_INS_MOVN) + * Capstone: ARM64_INS_MOVN * ARM: movn */ static RzILOpEffect *movn(cs_insn *insn) { @@ -1868,8 +1875,8 @@ static RzILOpEffect *movn(cs_insn *insn) { // The only case where the movn encoding should be disassembled as "movn" is // when (IsZero(imm16) && hw != '00'), according to the "alias conditions" in the reference manual. // Unfortunately, capstone v4 seems to always disassemble as movn, so we still have to implement this. - CS_aarch64_op() *op = &insn->detail->CS_aarch64_.operands[1]; - ut32 shift = op->shift.type == CS_AARCH64(_SFT_LSL) ? op->shift.value : 0; + cs_arm64_op *op = &insn->detail->arm64.operands[1]; + ut32 shift = op->shift.type == ARM64_SFT_LSL ? op->shift.value : 0; ut32 bits = REGBITS(0); if (!bits) { return NULL; @@ -1878,21 +1885,21 @@ static RzILOpEffect *movn(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_MSR) + * Capstone: ARM64_INS_MSR * ARM: msr */ static RzILOpEffect *msr(cs_insn *insn) { - CS_aarch64_op() *op = &insn->detail->CS_aarch64_.operands[0]; + cs_arm64_op *op = &insn->detail->arm64.operands[0]; #if CS_NEXT_VERSION >= 6 - if (op->type != CS_AARCH64(_OP_SYSREG) || (ut64)op->sysop.reg.sysreg != (ut64)CS_AARCH64(_SYSREG_NZCV)) { + if (op->type != ARM64_OP_SYSREG || (ut64)op->sysop.reg.sysreg != (ut64)ARM64_SYSREG_NZCV) { return NULL; } #elif CS_API_MAJOR > 4 && CS_NEXT_VERSION < 6 - if (op->type != CS_AARCH64(_OP_SYS) || (ut64)op->sys != (ut64)ARM64_SYSREG_NZCV) { + if (op->type != ARM64_OP_SYS || (ut64)op->sys != (ut64)ARM64_SYSREG_NZCV) { return NULL; } #else - if (op->type != CS_AARCH64(_OP_REG_MSR) || op->reg != 0xda10) { + if (op->type != ARM64_OP_REG_MSR || op->reg != 0xda10) { return NULL; } #endif @@ -1910,7 +1917,7 @@ static RzILOpEffect *msr(cs_insn *insn) { #if CS_API_MAJOR > 4 /** - * Capstone: CS_AARCH64(_INS_RMIF) + * Capstone: ARM64_INS_RMIF * ARM: rmif */ static RzILOpEffect *rmif(cs_insn *insn) { @@ -1944,7 +1951,7 @@ static RzILOpEffect *rmif(cs_insn *insn) { #endif /** - * Capstone: CS_AARCH64(_INS_SBFX), CS_AARCH64(_INS_SBFIZ), CS_AARCH64(_INS_UBFX), CS_AARCH64(_INS_UBFIZ) + * Capstone: ARM64_INS_SBFX, ARM64_INS_SBFIZ, ARM64_INS_UBFX, ARM64_INS_UBFIZ * ARM: sbfx, sbfiz, ubfx, ubfiz */ static RzILOpEffect *usbfm(cs_insn *insn) { @@ -1963,61 +1970,61 @@ static RzILOpEffect *usbfm(cs_insn *insn) { ut64 width = IMM(3); RzILOpBitVector *res; #if CS_NEXT_VERSION < 6 - if (insn->id == CS_AARCH64(_INS_SBFIZ) || insn->id == CS_AARCH64(_INS_UBFIZ)) { + if (insn->id == ARM64_INS_SBFIZ || insn->id == ARM64_INS_UBFIZ) { res = SHIFTL0(UNSIGNED(width + lsb, src), UN(6, lsb)); } else { - // CS_AARCH64(_INS_SBFX), CS_AARCH64(_INS_UBFX) + // ARM64_INS_SBFX, ARM64_INS_UBFX res = UNSIGNED(width, SHIFTR0(src, UN(6, lsb))); } - bool is_signed = insn->id == CS_AARCH64(_INS_SBFX) || insn->id == CS_AARCH64(_INS_SBFIZ); + bool is_signed = insn->id == ARM64_INS_SBFX || insn->id == ARM64_INS_SBFIZ; #else - if (insn->alias_id == AArch64_INS_ALIAS_SBFIZ || insn->alias_id == AArch64_INS_ALIAS_UBFIZ) { + if (insn->alias_id == AARCH64_INS_ALIAS_SBFIZ || insn->alias_id == AARCH64_INS_ALIAS_UBFIZ) { // TODO: modulo usage depends on N and SF bit. // sf == 0 && N == 0 => mod 32. // sf == 1 && N == 1 => mod 64. width += 1; lsb = -lsb % 64; res = SHIFTL0(UNSIGNED(width + lsb, src), UN(6, lsb)); - } else if (insn->alias_id == AArch64_INS_ALIAS_SBFX || insn->alias_id == AArch64_INS_ALIAS_UBFX) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_SBFX || insn->alias_id == AARCH64_INS_ALIAS_UBFX) { width = width - lsb + 1; res = UNSIGNED(width, SHIFTR0(src, UN(6, lsb))); - } else if (insn->alias_id == AArch64_INS_ALIAS_LSL) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_LSL) { // imms != 0x1f => mod 32 // imms != 0x3f => mod 64 ut32 m = IMM(3) != 0x1f ? 32 : 64; return write_reg(REGID(0), SHIFTL0(src, UN(6, -IMM(2) % m))); - } else if (insn->alias_id == AArch64_INS_ALIAS_LSR) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_LSR) { return write_reg(REGID(0), SHIFTR0(src, UN(6, IMM(2)))); - } else if (insn->alias_id == AArch64_INS_ALIAS_ASR) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_ASR) { return write_reg(REGID(0), SHIFTR(MSB(src), DUP(src), UN(6, IMM(2)))); } else { return NULL; } - bool is_signed = insn->alias_id == AArch64_INS_ALIAS_SBFX || insn->alias_id == AArch64_INS_ALIAS_SBFIZ; + bool is_signed = insn->alias_id == AARCH64_INS_ALIAS_SBFX || insn->alias_id == AARCH64_INS_ALIAS_SBFIZ; #endif res = LET("res", res, is_signed ? SIGNED(bits, VARLP("res")) : UNSIGNED(bits, VARLP("res"))); return write_reg(REGID(0), res); } /** - * Capstone: CS_AARCH64(_INS_MRS) + * Capstone: ARM64_INS_MRS * ARM: mrs */ static RzILOpEffect *mrs(cs_insn *insn) { if (!ISREG(0)) { return NULL; } - CS_aarch64_op() *op = &insn->detail->CS_aarch64_.operands[1]; + cs_arm64_op *op = &insn->detail->arm64.operands[1]; #if CS_NEXT_VERSION >= 6 - if (op->type != CS_AARCH64(_OP_SYSREG) || (ut64)op->sysop.reg.sysreg != (ut64)CS_AARCH64(_SYSREG_NZCV)) { + if (op->type != ARM64_OP_SYSREG || (ut64)op->sysop.reg.sysreg != (ut64)ARM64_SYSREG_NZCV) { return NULL; } #elif CS_API_MAJOR > 4 && CS_NEXT_VERSION < 6 - if (op->type != CS_AARCH64(_OP_SYS) || (ut64)op->sys != (ut64)ARM64_SYSREG_NZCV) { + if (op->type != ARM64_OP_SYS || (ut64)op->sys != (ut64)ARM64_SYSREG_NZCV) { return NULL; } #else - if (op->type != CS_AARCH64(_OP_REG_MRS) || op->reg != 0xda10) { + if (op->type != ARM64_OP_REG_MRS || op->reg != 0xda10) { return NULL; } #endif @@ -2033,7 +2040,7 @@ static RzILOpEffect *mrs(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_MVN), CS_AARCH64(_INS_NEG), CS_AARCH64(_INS_NEGS), CS_AARCH64(_INS_NGC), CS_AARCH64(_INS_NGCS) + * Capstone: ARM64_INS_MVN, ARM64_INS_NEG, ARM64_INS_NEGS, ARM64_INS_NGC, ARM64_INS_NGCS * ARM: mvn, neg, negs, ngc, ngcs */ static RzILOpEffect *mvn(cs_insn *insn) { @@ -2053,29 +2060,29 @@ static RzILOpEffect *mvn(cs_insn *insn) { RzILOpBitVector *res; #if CS_NEXT_VERSION < 6 switch (insn->id) { - case CS_AARCH64(_INS_NEG): - case CS_AARCH64(_INS_NEGS): + case ARM64_INS_NEG: + case ARM64_INS_NEGS: res = NEG(val); break; - case CS_AARCH64(_INS_NGC): - case CS_AARCH64(_INS_NGCS): + case ARM64_INS_NGC: + case ARM64_INS_NGCS: res = NEG(ADD(val, ITE(VARG("cf"), UN(bits, 0), UN(bits, 1)))); break; - default: // CS_AARCH64(_INS_MVN) + default: // ARM64_INS_MVN res = LOGNOT(val); break; } #else switch (insn->alias_id) { - case AArch64_INS_ALIAS_NEG: - case AArch64_INS_ALIAS_NEGS: + case AARCH64_INS_ALIAS_NEG: + case AARCH64_INS_ALIAS_NEGS: res = NEG(val); break; - case AArch64_INS_ALIAS_NGC: - case AArch64_INS_ALIAS_NGCS: + case AARCH64_INS_ALIAS_NGC: + case AARCH64_INS_ALIAS_NGCS: res = NEG(ADD(val, ITE(VARG("cf"), UN(bits, 0), UN(bits, 1)))); break; - case AArch64_INS_ALIAS_MVN: + case AARCH64_INS_ALIAS_MVN: res = LOGNOT(val); break; default: @@ -2086,13 +2093,13 @@ static RzILOpEffect *mvn(cs_insn *insn) { if (!set) { return NULL; } - if (insn->detail->CS_aarch64_.update_flags) { + if (insn->detail->arm64.update_flags) { // MSVC pre-processor can't parse "#if CS_NEXT... SETG(...) ..." if it is inlined. // So we define a variable here. Otherwise we get "error C2121". #if CS_NEXT_VERSION < 6 - RzILOpEffect *set_cf = SETG("cf", sub_carry(UN(bits, 0), VARL("b"), insn->id == CS_AARCH64(_INS_NGC), bits)); + RzILOpEffect *set_cf = SETG("cf", sub_carry(UN(bits, 0), VARL("b"), insn->id == ARM64_INS_NGC, bits)); #else - RzILOpEffect *set_cf = SETG("cf", sub_carry(UN(bits, 0), VARL("b"), insn->alias_id == AArch64_INS_ALIAS_NGC, bits)); + RzILOpEffect *set_cf = SETG("cf", sub_carry(UN(bits, 0), VARL("b"), insn->alias_id == AARCH64_INS_ALIAS_NGC, bits)); #endif return SEQ5( SETL("b", DUP(val)), @@ -2105,7 +2112,7 @@ static RzILOpEffect *mvn(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_RBIT) + * Capstone: ARM64_INS_RBIT * ARM: rbit */ static RzILOpEffect *rbit(cs_insn *insn) { @@ -2134,7 +2141,7 @@ static RzILOpEffect *rbit(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_REV), CS_AARCH64(_INS_REV32), CS_AARCH64(_INS_REV16) + * Capstone: ARM64_INS_REV, ARM64_INS_REV32, ARM64_INS_REV16 * ARM: rev, rev32, rev16 */ static RzILOpEffect *rev(cs_insn *insn) { @@ -2145,11 +2152,11 @@ static RzILOpEffect *rev(cs_insn *insn) { if (!dst_bits) { return NULL; } - CS_aarch64_reg() src_reg = xreg_of_reg(REGID(1)); + arm64_reg src_reg = xreg_of_reg(REGID(1)); ut32 container_bits = dst_bits; - if (insn->id == CS_AARCH64(_INS_REV32)) { + if (insn->id == ARM64_INS_REV32) { container_bits = 32; - } else if (insn->id == CS_AARCH64(_INS_REV16)) { + } else if (insn->id == ARM64_INS_REV16) { container_bits = 16; } RzILOpBitVector *src = read_reg(src_reg); @@ -2200,7 +2207,7 @@ static RzILOpEffect *rev(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_SDIV) + * Capstone: ARM64_INS_SDIV * ARM: sdiv */ static RzILOpEffect *sdiv(cs_insn *insn) { @@ -2226,7 +2233,7 @@ static RzILOpEffect *sdiv(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_UDIV) + * Capstone: ARM64_INS_UDIV * ARM: udiv */ static RzILOpEffect *udiv(cs_insn *insn) { @@ -2250,7 +2257,7 @@ static RzILOpEffect *udiv(cs_insn *insn) { #if CS_API_MAJOR > 4 /** - * Capstone: CS_AARCH64(_INS_SETF8), CS_AARCH64(_INS_SETF16) + * Capstone: ARM64_INS_SETF8, ARM64_INS_SETF16 * ARM: setf8, setf16 */ static RzILOpEffect *setf(cs_insn *insn) { @@ -2261,7 +2268,7 @@ static RzILOpEffect *setf(cs_insn *insn) { if (!val) { return NULL; } - ut32 bits = insn->id == CS_AARCH64(_INS_SETF16) ? 16 : 8; + ut32 bits = insn->id == ARM64_INS_SETF16 ? 16 : 8; return SEQ2( SETG("vf", XOR(MSB(UNSIGNED(bits + 1, val)), MSB(UNSIGNED(bits, DUP(val))))), update_flags_zn(UNSIGNED(bits, DUP(val)))); @@ -2269,7 +2276,7 @@ static RzILOpEffect *setf(cs_insn *insn) { #endif /** - * Capstone: CS_AARCH64(_INS_SMADDL), CS_AARCH64(_INS_SMSUBL), CS_AARCH64(_INS_UMADDL), CS_AARCH64(_INS_UMSUBL) + * Capstone: ARM64_INS_SMADDL, ARM64_INS_SMSUBL, ARM64_INS_UMADDL, ARM64_INS_UMSUBL * ARM: smaddl, smsubl, umaddl, umsubl */ static RzILOpEffect *smaddl(cs_insn *insn) { @@ -2287,9 +2294,9 @@ static RzILOpEffect *smaddl(cs_insn *insn) { rz_il_op_pure_free(addend); return NULL; } - bool is_signed = insn->id == CS_AARCH64(_INS_SMADDL) || insn->id == CS_AARCH64(_INS_SMSUBL); + bool is_signed = insn->id == ARM64_INS_SMADDL || insn->id == ARM64_INS_SMSUBL; RzILOpBitVector *res = MUL(is_signed ? SIGNED(64, x) : UNSIGNED(64, x), is_signed ? SIGNED(64, y) : UNSIGNED(64, y)); - if (insn->id == CS_AARCH64(_INS_SMSUBL) || insn->id == CS_AARCH64(_INS_UMSUBL)) { + if (insn->id == ARM64_INS_SMSUBL || insn->id == ARM64_INS_UMSUBL) { res = SUB(addend, res); } else { res = ADD(addend, res); @@ -2298,7 +2305,7 @@ static RzILOpEffect *smaddl(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_SMULL), CS_AARCH64(_INS_SMNEGL), CS_AARCH64(_INS_UMULL), CS_AARCH64(_INS_UMNEGL) + * Capstone: ARM64_INS_SMULL, ARM64_INS_SMNEGL, ARM64_INS_UMULL, ARM64_INS_UMNEGL * ARM: smull, smnegl, umull, umnegl */ static RzILOpEffect *smull(cs_insn *insn) { @@ -2314,17 +2321,17 @@ static RzILOpEffect *smull(cs_insn *insn) { return NULL; } #if CS_NEXT_VERSION < 6 - bool is_signed = insn->id == CS_AARCH64(_INS_SMULL) || insn->id == CS_AARCH64(_INS_SMNEGL); + bool is_signed = insn->id == ARM64_INS_SMULL || insn->id == ARM64_INS_SMNEGL; #else - bool is_signed = insn->alias_id == AArch64_INS_ALIAS_SMULL || insn->alias_id == AArch64_INS_ALIAS_SMNEGL; + bool is_signed = insn->alias_id == AARCH64_INS_ALIAS_SMULL || insn->alias_id == AARCH64_INS_ALIAS_SMNEGL; #endif RzILOpBitVector *res = MUL(is_signed ? SIGNED(64, x) : UNSIGNED(64, x), is_signed ? SIGNED(64, y) : UNSIGNED(64, y)); #if CS_NEXT_VERSION < 6 - if (insn->id == CS_AARCH64(_INS_SMNEGL) || insn->id == CS_AARCH64(_INS_UMNEGL)) { + if (insn->id == ARM64_INS_SMNEGL || insn->id == ARM64_INS_UMNEGL) { res = NEG(res); } #else - if (insn->alias_id == AArch64_INS_ALIAS_SMNEGL || insn->alias_id == AArch64_INS_ALIAS_UMNEGL) { + if (insn->alias_id == AARCH64_INS_ALIAS_SMNEGL || insn->alias_id == AARCH64_INS_ALIAS_UMNEGL) { res = NEG(res); } #endif @@ -2332,7 +2339,7 @@ static RzILOpEffect *smull(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_SMULH), CS_AARCH64(_INS_UMULH) + * Capstone: ARM64_INS_SMULH, ARM64_INS_UMULH * ARM: smulh, umulh */ static RzILOpEffect *smulh(cs_insn *insn) { @@ -2347,16 +2354,16 @@ static RzILOpEffect *smulh(cs_insn *insn) { rz_il_op_pure_free(y); return NULL; } - bool is_signed = insn->id == CS_AARCH64(_INS_SMULH); + bool is_signed = insn->id == ARM64_INS_SMULH; RzILOpBitVector *res = MUL(is_signed ? SIGNED(128, x) : UNSIGNED(128, x), is_signed ? SIGNED(128, y) : UNSIGNED(128, y)); return write_reg(REGID(0), UNSIGNED(64, SHIFTR0(res, UN(7, 64)))); } #if CS_API_MAJOR > 4 /** - * Capstone: CS_AARCH64(_INS_SWP), CS_AARCH64(_INS_SWPA), CS_AARCH64(_INS_SWPAL), CS_AARCH64(_INS_SWPL), - * CS_AARCH64(_INS_SWPB), CS_AARCH64(_INS_SWPAB), CS_AARCH64(_INS_SWPALB), CS_AARCH64(_INS_SWPLB) - * CS_AARCH64(_INS_SWPH), CS_AARCH64(_INS_SWPAH), CS_AARCH64(_INS_SWPALH), CS_AARCH64(_INS_SWPLH) + * Capstone: ARM64_INS_SWP, ARM64_INS_SWPA, ARM64_INS_SWPAL, ARM64_INS_SWPL, + * ARM64_INS_SWPB, ARM64_INS_SWPAB, ARM64_INS_SWPALB, ARM64_INS_SWPLB + * ARM64_INS_SWPH, ARM64_INS_SWPAH, ARM64_INS_SWPALH, ARM64_INS_SWPLH * ARM: swp, swpa, swpal, swpl, swpb, swpab, swpalb, swplb, swph, swpah, swpalh, swplh */ static RzILOpEffect *swp(cs_insn *insn) { @@ -2365,19 +2372,19 @@ static RzILOpEffect *swp(cs_insn *insn) { } ut32 bits; switch (insn->id) { - case CS_AARCH64(_INS_SWPB): - case CS_AARCH64(_INS_SWPAB): - case CS_AARCH64(_INS_SWPALB): - case CS_AARCH64(_INS_SWPLB): + case ARM64_INS_SWPB: + case ARM64_INS_SWPAB: + case ARM64_INS_SWPALB: + case ARM64_INS_SWPLB: bits = 8; break; - case CS_AARCH64(_INS_SWPH): - case CS_AARCH64(_INS_SWPAH): - case CS_AARCH64(_INS_SWPALH): - case CS_AARCH64(_INS_SWPLH): + case ARM64_INS_SWPH: + case ARM64_INS_SWPAH: + case ARM64_INS_SWPALH: + case ARM64_INS_SWPLH: bits = 16; break; - default: // CS_AARCH64(_INS_SWP), CS_AARCH64(_INS_SWPA), CS_AARCH64(_INS_SWPAL), CS_AARCH64(_INS_SWPL): + default: // ARM64_INS_SWP, ARM64_INS_SWPA, ARM64_INS_SWPAL, ARM64_INS_SWPL: bits = REGBITS(0); if (!bits) { return NULL; @@ -2396,8 +2403,8 @@ static RzILOpEffect *swp(cs_insn *insn) { return NULL; } RzILOpEffect *store_eff = bits == 8 ? STORE(addr, store_val) : STOREW(addr, store_val); - CS_aarch64_reg() ret_reg = xreg_of_reg(REGID(1)); - if (ret_reg == CS_AARCH64(_REG_XZR)) { + arm64_reg ret_reg = xreg_of_reg(REGID(1)); + if (ret_reg == ARM64_REG_XZR) { return store_eff; } RzILOpEffect *ret_eff = write_reg(ret_reg, bits != 64 ? UNSIGNED(64, VARL("ret")) : VARL("ret")); @@ -2413,7 +2420,7 @@ static RzILOpEffect *swp(cs_insn *insn) { #endif /** - * Capstone: CS_AARCH64(_INS_SXTB), CS_AARCH64(_INS_SXTH), CS_AARCH64(_INS_SXTW), CS_AARCH64(_INS_UXTB), CS_AARCH64(_INS_UXTH) + * Capstone: ARM64_INS_SXTB, ARM64_INS_SXTH, ARM64_INS_SXTW, ARM64_INS_UXTB, ARM64_INS_UXTH * ARM: sxtb, sxth, sxtw, uxtb, uxth */ static RzILOpEffect *sxt(cs_insn *insn) { @@ -2424,19 +2431,19 @@ static RzILOpEffect *sxt(cs_insn *insn) { bool is_signed = true; #if CS_NEXT_VERSION < 6 switch (insn->id) { - case CS_AARCH64(_INS_UXTB): + case ARM64_INS_UXTB: is_signed = false; // fallthrough - case CS_AARCH64(_INS_SXTB): + case ARM64_INS_SXTB: bits = 8; break; - case CS_AARCH64(_INS_UXTH): + case ARM64_INS_UXTH: is_signed = false; // fallthrough - case CS_AARCH64(_INS_SXTH): + case ARM64_INS_SXTH: bits = 16; break; - default: // CS_AARCH64(_INS_SXTW) + default: // ARM64_INS_SXTW bits = 32; break; } @@ -2444,19 +2451,19 @@ static RzILOpEffect *sxt(cs_insn *insn) { switch (insn->alias_id) { default: return NULL; - case AArch64_INS_ALIAS_UXTB: + case AARCH64_INS_ALIAS_UXTB: is_signed = false; // fallthrough - case AArch64_INS_ALIAS_SXTB: + case AARCH64_INS_ALIAS_SXTB: bits = 8; break; - case AArch64_INS_ALIAS_UXTH: + case AARCH64_INS_ALIAS_UXTH: is_signed = false; // fallthrough - case AArch64_INS_ALIAS_SXTH: + case AARCH64_INS_ALIAS_SXTH: bits = 16; break; - case AArch64_INS_ALIAS_SXTW: + case AARCH64_INS_ALIAS_SXTW: bits = 32; break; } @@ -2469,7 +2476,7 @@ static RzILOpEffect *sxt(cs_insn *insn) { } /** - * Capstone: CS_AARCH64(_INS_TBNZ), ARM64_TBZ + * Capstone: ARM64_INS_TBNZ, ARM64_TBZ * ARM: tbnz, tbz */ static RzILOpEffect *tbz(cs_insn *insn) { @@ -2485,13 +2492,13 @@ static RzILOpEffect *tbz(cs_insn *insn) { return NULL; } RzILOpBool *c = LSB(SHIFTR0(src, UN(6, IMM(1)))); - return insn->id == CS_AARCH64(_INS_TBNZ) + return insn->id == ARM64_INS_TBNZ ? BRANCH(c, JMP(tgt), NULL) : BRANCH(c, NULL, JMP(tgt)); } /** - * Capstone: CS_AARCH64(_INS_TST) + * Capstone: ARM64_INS_TST * ARM: tst */ static RzILOpEffect *tst(cs_insn *insn) { @@ -2589,533 +2596,533 @@ static RzILOpEffect *tst(cs_insn *insn) { */ RZ_IPI RzILOpEffect *rz_arm_cs_64_il(csh *handle, cs_insn *insn) { switch (insn->id) { - case CS_AARCH64(_INS_HINT): - case CS_AARCH64(_INS_PRFM): - case CS_AARCH64(_INS_PRFUM): + case ARM64_INS_HINT: + case ARM64_INS_PRFM: + case ARM64_INS_PRFUM: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_NOP): - case CS_AARCH64(_INS_SEV): - case CS_AARCH64(_INS_SEVL): - case CS_AARCH64(_INS_WFE): - case CS_AARCH64(_INS_WFI): - case CS_AARCH64(_INS_YIELD): + case ARM64_INS_NOP: + case ARM64_INS_SEV: + case ARM64_INS_SEVL: + case ARM64_INS_WFE: + case ARM64_INS_WFI: + case ARM64_INS_YIELD: #endif return NOP(); - case CS_AARCH64(_INS_ADD): - case CS_AARCH64(_INS_ADC): - case CS_AARCH64(_INS_SUB): - case CS_AARCH64(_INS_SBC): + case ARM64_INS_ADD: + case ARM64_INS_ADC: + case ARM64_INS_SUB: + case ARM64_INS_SBC: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_ADDS): - case CS_AARCH64(_INS_SUBS): - case CS_AARCH64(_INS_ADCS): - case CS_AARCH64(_INS_SBCS): + case ARM64_INS_ADDS: + case ARM64_INS_SUBS: + case ARM64_INS_ADCS: + case ARM64_INS_SBCS: #endif #if CS_NEXT_VERSION >= 6 - if (insn->alias_id == AArch64_INS_ALIAS_MOV || - insn->alias_id == AArch64_INS_ALIAS_MOVZ) { + if (insn->alias_id == AARCH64_INS_ALIAS_MOV || + insn->alias_id == AARCH64_INS_ALIAS_MOVZ) { return mov(insn); - } else if (insn->alias_id == AArch64_INS_ALIAS_CMP || - insn->alias_id == AArch64_INS_ALIAS_CMN) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_CMP || + insn->alias_id == AARCH64_INS_ALIAS_CMN) { return cmp(insn); - } else if (insn->alias_id == AArch64_INS_ALIAS_NEG || - insn->alias_id == AArch64_INS_ALIAS_NGC || - insn->alias_id == AArch64_INS_ALIAS_NEGS || - insn->alias_id == AArch64_INS_ALIAS_NGCS) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_NEG || + insn->alias_id == AARCH64_INS_ALIAS_NGC || + insn->alias_id == AARCH64_INS_ALIAS_NEGS || + insn->alias_id == AARCH64_INS_ALIAS_NGCS) { return mvn(insn); } #endif return add_sub(insn); - case CS_AARCH64(_INS_ADR): - case CS_AARCH64(_INS_ADRP): + case ARM64_INS_ADR: + case ARM64_INS_ADRP: return adr(insn); - case CS_AARCH64(_INS_AND): + case ARM64_INS_AND: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_ANDS): + case ARM64_INS_ANDS: #endif - case CS_AARCH64(_INS_EOR): - case CS_AARCH64(_INS_EON): - case CS_AARCH64(_INS_ORN): - case CS_AARCH64(_INS_ORR): + case ARM64_INS_EOR: + case ARM64_INS_EON: + case ARM64_INS_ORN: + case ARM64_INS_ORR: #if CS_NEXT_VERSION >= 6 - if (insn->alias_id == AArch64_INS_ALIAS_MOV || - insn->alias_id == AArch64_INS_ALIAS_MOVZ) { + if (insn->alias_id == AARCH64_INS_ALIAS_MOV || + insn->alias_id == AARCH64_INS_ALIAS_MOVZ) { return mov(insn); - } else if (insn->alias_id == AArch64_INS_ALIAS_TST) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_TST) { return tst(insn); - } else if (insn->alias_id == AArch64_INS_ALIAS_MVN) { + } else if (insn->alias_id == AARCH64_INS_ALIAS_MVN) { return mvn(insn); } #endif return bitwise(insn); - case CS_AARCH64(_INS_ASR): - case CS_AARCH64(_INS_LSL): - case CS_AARCH64(_INS_LSR): - case CS_AARCH64(_INS_ROR): + case ARM64_INS_ASR: + case ARM64_INS_LSL: + case ARM64_INS_LSR: + case ARM64_INS_ROR: return shift(insn); - case CS_AARCH64(_INS_B): - case CS_AARCH64(_INS_BR): - case CS_AARCH64(_INS_RET): + case ARM64_INS_B: + case ARM64_INS_BR: + case ARM64_INS_RET: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_BRAA): - case CS_AARCH64(_INS_BRAAZ): - case CS_AARCH64(_INS_BRAB): - case CS_AARCH64(_INS_BRABZ): - case CS_AARCH64(_INS_RETAA): - case CS_AARCH64(_INS_RETAB): + case ARM64_INS_BRAA: + case ARM64_INS_BRAAZ: + case ARM64_INS_BRAB: + case ARM64_INS_BRABZ: + case ARM64_INS_RETAA: + case ARM64_INS_RETAB: #endif return branch(insn); - case CS_AARCH64(_INS_BL): - case CS_AARCH64(_INS_BLR): + case ARM64_INS_BL: + case ARM64_INS_BLR: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_BLRAA): - case CS_AARCH64(_INS_BLRAAZ): - case CS_AARCH64(_INS_BLRAB): - case CS_AARCH64(_INS_BLRABZ): + case ARM64_INS_BLRAA: + case ARM64_INS_BLRAAZ: + case ARM64_INS_BLRAB: + case ARM64_INS_BLRABZ: #endif return bl(insn); - case CS_AARCH64(_INS_BFM): + case ARM64_INS_BFM: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_BFI): - case CS_AARCH64(_INS_BFXIL): + case ARM64_INS_BFI: + case ARM64_INS_BFXIL: #endif return bfm(insn); - case CS_AARCH64(_INS_BIC): + case ARM64_INS_BIC: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_BICS): + case ARM64_INS_BICS: #endif return bic(insn); #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_CAS): - case CS_AARCH64(_INS_CASA): - case CS_AARCH64(_INS_CASAL): - case CS_AARCH64(_INS_CASL): - case CS_AARCH64(_INS_CASB): - case CS_AARCH64(_INS_CASAB): - case CS_AARCH64(_INS_CASALB): - case CS_AARCH64(_INS_CASLB): - case CS_AARCH64(_INS_CASH): - case CS_AARCH64(_INS_CASAH): - case CS_AARCH64(_INS_CASALH): - case CS_AARCH64(_INS_CASLH): + case ARM64_INS_CAS: + case ARM64_INS_CASA: + case ARM64_INS_CASAL: + case ARM64_INS_CASL: + case ARM64_INS_CASB: + case ARM64_INS_CASAB: + case ARM64_INS_CASALB: + case ARM64_INS_CASLB: + case ARM64_INS_CASH: + case ARM64_INS_CASAH: + case ARM64_INS_CASALH: + case ARM64_INS_CASLH: return cas(insn); - case CS_AARCH64(_INS_CASP): - case CS_AARCH64(_INS_CASPA): - case CS_AARCH64(_INS_CASPAL): - case CS_AARCH64(_INS_CASPL): + case ARM64_INS_CASP: + case ARM64_INS_CASPA: + case ARM64_INS_CASPAL: + case ARM64_INS_CASPL: return casp(insn); #endif - case CS_AARCH64(_INS_CBZ): - case CS_AARCH64(_INS_CBNZ): + case ARM64_INS_CBZ: + case ARM64_INS_CBNZ: return cbz(insn); #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CMP): - case CS_AARCH64(_INS_CMN): + case ARM64_INS_CMP: + case ARM64_INS_CMN: #endif - case CS_AARCH64(_INS_CCMP): - case CS_AARCH64(_INS_CCMN): + case ARM64_INS_CCMP: + case ARM64_INS_CCMN: return cmp(insn); #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_CFINV): + case ARM64_INS_CFINV: return SETG("cf", INV(VARG("cf"))); #endif - case CS_AARCH64(_INS_CSINC): - case CS_AARCH64(_INS_CSINV): - case CS_AARCH64(_INS_CSNEG): - case CS_AARCH64(_INS_CSEL): + case ARM64_INS_CSINC: + case ARM64_INS_CSINV: + case ARM64_INS_CSNEG: + case ARM64_INS_CSEL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CINC): - case CS_AARCH64(_INS_CINV): - case CS_AARCH64(_INS_CNEG): + case ARM64_INS_CINC: + case ARM64_INS_CINV: + case ARM64_INS_CNEG: #else - if (insn->alias_id == AArch64_INS_ALIAS_CSET || - insn->alias_id == AArch64_INS_ALIAS_CSETM) { + if (insn->alias_id == AARCH64_INS_ALIAS_CSET || + insn->alias_id == AARCH64_INS_ALIAS_CSETM) { return cset(insn); } #endif return csinc(insn); #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CSET): - case CS_AARCH64(_INS_CSETM): + case ARM64_INS_CSET: + case ARM64_INS_CSETM: return cset(insn); #endif - case CS_AARCH64(_INS_CLS): + case ARM64_INS_CLS: return cls(insn); - case CS_AARCH64(_INS_CLZ): + case ARM64_INS_CLZ: return clz(insn); - case CS_AARCH64(_INS_EXTR): + case ARM64_INS_EXTR: #if CS_NEXT_VERSION >= 6 - if (insn->alias_id == AArch64_INS_ALIAS_ROR) { + if (insn->alias_id == AARCH64_INS_ALIAS_ROR) { return shift(insn); } #endif return extr(insn); - case CS_AARCH64(_INS_HVC): + case ARM64_INS_HVC: return hvc(insn); - case CS_AARCH64(_INS_SVC): + case ARM64_INS_SVC: return svc(insn); - case CS_AARCH64(_INS_LDR): - case CS_AARCH64(_INS_LDRB): - case CS_AARCH64(_INS_LDRH): - case CS_AARCH64(_INS_LDUR): - case CS_AARCH64(_INS_LDURB): - case CS_AARCH64(_INS_LDURH): - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDRSB): - case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDURSW): - case CS_AARCH64(_INS_LDURSB): - case CS_AARCH64(_INS_LDURSH): - case CS_AARCH64(_INS_LDAR): - case CS_AARCH64(_INS_LDARB): - case CS_AARCH64(_INS_LDARH): - case CS_AARCH64(_INS_LDAXP): - case CS_AARCH64(_INS_LDXP): - case CS_AARCH64(_INS_LDAXR): - case CS_AARCH64(_INS_LDAXRB): - case CS_AARCH64(_INS_LDAXRH): - case CS_AARCH64(_INS_LDP): - case CS_AARCH64(_INS_LDNP): - case CS_AARCH64(_INS_LDPSW): - case CS_AARCH64(_INS_LDTR): - case CS_AARCH64(_INS_LDTRB): - case CS_AARCH64(_INS_LDTRH): - case CS_AARCH64(_INS_LDTRSW): - case CS_AARCH64(_INS_LDTRSB): - case CS_AARCH64(_INS_LDTRSH): - case CS_AARCH64(_INS_LDXR): - case CS_AARCH64(_INS_LDXRB): - case CS_AARCH64(_INS_LDXRH): + case ARM64_INS_LDR: + case ARM64_INS_LDRB: + case ARM64_INS_LDRH: + case ARM64_INS_LDUR: + case ARM64_INS_LDURB: + case ARM64_INS_LDURH: + case ARM64_INS_LDRSW: + case ARM64_INS_LDRSB: + case ARM64_INS_LDRSH: + case ARM64_INS_LDURSW: + case ARM64_INS_LDURSB: + case ARM64_INS_LDURSH: + case ARM64_INS_LDAR: + case ARM64_INS_LDARB: + case ARM64_INS_LDARH: + case ARM64_INS_LDAXP: + case ARM64_INS_LDXP: + case ARM64_INS_LDAXR: + case ARM64_INS_LDAXRB: + case ARM64_INS_LDAXRH: + case ARM64_INS_LDP: + case ARM64_INS_LDNP: + case ARM64_INS_LDPSW: + case ARM64_INS_LDTR: + case ARM64_INS_LDTRB: + case ARM64_INS_LDTRH: + case ARM64_INS_LDTRSW: + case ARM64_INS_LDTRSB: + case ARM64_INS_LDTRSH: + case ARM64_INS_LDXR: + case ARM64_INS_LDXRB: + case ARM64_INS_LDXRH: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDAPR): - case CS_AARCH64(_INS_LDAPRB): - case CS_AARCH64(_INS_LDAPRH): - case CS_AARCH64(_INS_LDAPUR): - case CS_AARCH64(_INS_LDAPURB): - case CS_AARCH64(_INS_LDAPURH): - case CS_AARCH64(_INS_LDAPURSB): - case CS_AARCH64(_INS_LDAPURSH): - case CS_AARCH64(_INS_LDAPURSW): - case CS_AARCH64(_INS_LDLAR): - case CS_AARCH64(_INS_LDLARB): - case CS_AARCH64(_INS_LDLARH): - case CS_AARCH64(_INS_LDRAA): - case CS_AARCH64(_INS_LDRAB): + case ARM64_INS_LDAPR: + case ARM64_INS_LDAPRB: + case ARM64_INS_LDAPRH: + case ARM64_INS_LDAPUR: + case ARM64_INS_LDAPURB: + case ARM64_INS_LDAPURH: + case ARM64_INS_LDAPURSB: + case ARM64_INS_LDAPURSH: + case ARM64_INS_LDAPURSW: + case ARM64_INS_LDLAR: + case ARM64_INS_LDLARB: + case ARM64_INS_LDLARH: + case ARM64_INS_LDRAA: + case ARM64_INS_LDRAB: #endif return ldr(insn); #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_LDADD): - case CS_AARCH64(_INS_LDADDA): - case CS_AARCH64(_INS_LDADDAL): - case CS_AARCH64(_INS_LDADDL): - case CS_AARCH64(_INS_LDADDB): - case CS_AARCH64(_INS_LDADDAB): - case CS_AARCH64(_INS_LDADDALB): - case CS_AARCH64(_INS_LDADDLB): - case CS_AARCH64(_INS_LDADDH): - case CS_AARCH64(_INS_LDADDAH): - case CS_AARCH64(_INS_LDADDALH): - case CS_AARCH64(_INS_LDADDLH): + case ARM64_INS_LDADD: + case ARM64_INS_LDADDA: + case ARM64_INS_LDADDAL: + case ARM64_INS_LDADDL: + case ARM64_INS_LDADDB: + case ARM64_INS_LDADDAB: + case ARM64_INS_LDADDALB: + case ARM64_INS_LDADDLB: + case ARM64_INS_LDADDH: + case ARM64_INS_LDADDAH: + case ARM64_INS_LDADDALH: + case ARM64_INS_LDADDLH: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STADD): - case CS_AARCH64(_INS_STADDL): - case CS_AARCH64(_INS_STADDB): - case CS_AARCH64(_INS_STADDLB): - case CS_AARCH64(_INS_STADDH): - case CS_AARCH64(_INS_STADDLH): -#endif - case CS_AARCH64(_INS_LDCLRB): - case CS_AARCH64(_INS_LDCLRAB): - case CS_AARCH64(_INS_LDCLRALB): - case CS_AARCH64(_INS_LDCLRLB): - case CS_AARCH64(_INS_LDCLRH): - case CS_AARCH64(_INS_LDCLRAH): - case CS_AARCH64(_INS_LDCLRALH): - case CS_AARCH64(_INS_LDCLRLH): - case CS_AARCH64(_INS_LDCLR): - case CS_AARCH64(_INS_LDCLRA): - case CS_AARCH64(_INS_LDCLRAL): - case CS_AARCH64(_INS_LDCLRL): + case ARM64_INS_STADD: + case ARM64_INS_STADDL: + case ARM64_INS_STADDB: + case ARM64_INS_STADDLB: + case ARM64_INS_STADDH: + case ARM64_INS_STADDLH: +#endif + case ARM64_INS_LDCLRB: + case ARM64_INS_LDCLRAB: + case ARM64_INS_LDCLRALB: + case ARM64_INS_LDCLRLB: + case ARM64_INS_LDCLRH: + case ARM64_INS_LDCLRAH: + case ARM64_INS_LDCLRALH: + case ARM64_INS_LDCLRLH: + case ARM64_INS_LDCLR: + case ARM64_INS_LDCLRA: + case ARM64_INS_LDCLRAL: + case ARM64_INS_LDCLRL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STCLR): - case CS_AARCH64(_INS_STCLRL): - case CS_AARCH64(_INS_STCLRB): - case CS_AARCH64(_INS_STCLRLB): - case CS_AARCH64(_INS_STCLRH): - case CS_AARCH64(_INS_STCLRLH): -#endif - case CS_AARCH64(_INS_LDEORB): - case CS_AARCH64(_INS_LDEORAB): - case CS_AARCH64(_INS_LDEORALB): - case CS_AARCH64(_INS_LDEORLB): - case CS_AARCH64(_INS_LDEORH): - case CS_AARCH64(_INS_LDEORAH): - case CS_AARCH64(_INS_LDEORALH): - case CS_AARCH64(_INS_LDEORLH): - case CS_AARCH64(_INS_LDEOR): - case CS_AARCH64(_INS_LDEORA): - case CS_AARCH64(_INS_LDEORAL): - case CS_AARCH64(_INS_LDEORL): + case ARM64_INS_STCLR: + case ARM64_INS_STCLRL: + case ARM64_INS_STCLRB: + case ARM64_INS_STCLRLB: + case ARM64_INS_STCLRH: + case ARM64_INS_STCLRLH: +#endif + case ARM64_INS_LDEORB: + case ARM64_INS_LDEORAB: + case ARM64_INS_LDEORALB: + case ARM64_INS_LDEORLB: + case ARM64_INS_LDEORH: + case ARM64_INS_LDEORAH: + case ARM64_INS_LDEORALH: + case ARM64_INS_LDEORLH: + case ARM64_INS_LDEOR: + case ARM64_INS_LDEORA: + case ARM64_INS_LDEORAL: + case ARM64_INS_LDEORL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STEOR): - case CS_AARCH64(_INS_STEORL): - case CS_AARCH64(_INS_STEORB): - case CS_AARCH64(_INS_STEORLB): - case CS_AARCH64(_INS_STEORH): - case CS_AARCH64(_INS_STEORLH): -#endif - case CS_AARCH64(_INS_LDSETB): - case CS_AARCH64(_INS_LDSETAB): - case CS_AARCH64(_INS_LDSETALB): - case CS_AARCH64(_INS_LDSETLB): - case CS_AARCH64(_INS_LDSETH): - case CS_AARCH64(_INS_LDSETAH): - case CS_AARCH64(_INS_LDSETALH): - case CS_AARCH64(_INS_LDSETLH): - case CS_AARCH64(_INS_LDSET): - case CS_AARCH64(_INS_LDSETA): - case CS_AARCH64(_INS_LDSETAL): - case CS_AARCH64(_INS_LDSETL): + case ARM64_INS_STEOR: + case ARM64_INS_STEORL: + case ARM64_INS_STEORB: + case ARM64_INS_STEORLB: + case ARM64_INS_STEORH: + case ARM64_INS_STEORLH: +#endif + case ARM64_INS_LDSETB: + case ARM64_INS_LDSETAB: + case ARM64_INS_LDSETALB: + case ARM64_INS_LDSETLB: + case ARM64_INS_LDSETH: + case ARM64_INS_LDSETAH: + case ARM64_INS_LDSETALH: + case ARM64_INS_LDSETLH: + case ARM64_INS_LDSET: + case ARM64_INS_LDSETA: + case ARM64_INS_LDSETAL: + case ARM64_INS_LDSETL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSET): - case CS_AARCH64(_INS_STSETL): - case CS_AARCH64(_INS_STSETB): - case CS_AARCH64(_INS_STSETLB): - case CS_AARCH64(_INS_STSETH): - case CS_AARCH64(_INS_STSETLH): -#endif - case CS_AARCH64(_INS_LDSMAXB): - case CS_AARCH64(_INS_LDSMAXAB): - case CS_AARCH64(_INS_LDSMAXALB): - case CS_AARCH64(_INS_LDSMAXLB): - case CS_AARCH64(_INS_LDSMAXH): - case CS_AARCH64(_INS_LDSMAXAH): - case CS_AARCH64(_INS_LDSMAXALH): - case CS_AARCH64(_INS_LDSMAXLH): - case CS_AARCH64(_INS_LDSMAX): - case CS_AARCH64(_INS_LDSMAXA): - case CS_AARCH64(_INS_LDSMAXAL): - case CS_AARCH64(_INS_LDSMAXL): + case ARM64_INS_STSET: + case ARM64_INS_STSETL: + case ARM64_INS_STSETB: + case ARM64_INS_STSETLB: + case ARM64_INS_STSETH: + case ARM64_INS_STSETLH: +#endif + case ARM64_INS_LDSMAXB: + case ARM64_INS_LDSMAXAB: + case ARM64_INS_LDSMAXALB: + case ARM64_INS_LDSMAXLB: + case ARM64_INS_LDSMAXH: + case ARM64_INS_LDSMAXAH: + case ARM64_INS_LDSMAXALH: + case ARM64_INS_LDSMAXLH: + case ARM64_INS_LDSMAX: + case ARM64_INS_LDSMAXA: + case ARM64_INS_LDSMAXAL: + case ARM64_INS_LDSMAXL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMAX): - case CS_AARCH64(_INS_STSMAXL): - case CS_AARCH64(_INS_STSMAXB): - case CS_AARCH64(_INS_STSMAXLB): - case CS_AARCH64(_INS_STSMAXH): - case CS_AARCH64(_INS_STSMAXLH): -#endif - case CS_AARCH64(_INS_LDSMINB): - case CS_AARCH64(_INS_LDSMINAB): - case CS_AARCH64(_INS_LDSMINALB): - case CS_AARCH64(_INS_LDSMINLB): - case CS_AARCH64(_INS_LDSMINH): - case CS_AARCH64(_INS_LDSMINAH): - case CS_AARCH64(_INS_LDSMINALH): - case CS_AARCH64(_INS_LDSMINLH): - case CS_AARCH64(_INS_LDSMIN): - case CS_AARCH64(_INS_LDSMINA): - case CS_AARCH64(_INS_LDSMINAL): - case CS_AARCH64(_INS_LDSMINL): + case ARM64_INS_STSMAX: + case ARM64_INS_STSMAXL: + case ARM64_INS_STSMAXB: + case ARM64_INS_STSMAXLB: + case ARM64_INS_STSMAXH: + case ARM64_INS_STSMAXLH: +#endif + case ARM64_INS_LDSMINB: + case ARM64_INS_LDSMINAB: + case ARM64_INS_LDSMINALB: + case ARM64_INS_LDSMINLB: + case ARM64_INS_LDSMINH: + case ARM64_INS_LDSMINAH: + case ARM64_INS_LDSMINALH: + case ARM64_INS_LDSMINLH: + case ARM64_INS_LDSMIN: + case ARM64_INS_LDSMINA: + case ARM64_INS_LDSMINAL: + case ARM64_INS_LDSMINL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STSMIN): - case CS_AARCH64(_INS_STSMINL): - case CS_AARCH64(_INS_STSMINB): - case CS_AARCH64(_INS_STSMINLB): - case CS_AARCH64(_INS_STSMINH): - case CS_AARCH64(_INS_STSMINLH): -#endif - case CS_AARCH64(_INS_LDUMAXB): - case CS_AARCH64(_INS_LDUMAXAB): - case CS_AARCH64(_INS_LDUMAXALB): - case CS_AARCH64(_INS_LDUMAXLB): - case CS_AARCH64(_INS_LDUMAXH): - case CS_AARCH64(_INS_LDUMAXAH): - case CS_AARCH64(_INS_LDUMAXALH): - case CS_AARCH64(_INS_LDUMAXLH): - case CS_AARCH64(_INS_LDUMAX): - case CS_AARCH64(_INS_LDUMAXA): - case CS_AARCH64(_INS_LDUMAXAL): - case CS_AARCH64(_INS_LDUMAXL): + case ARM64_INS_STSMIN: + case ARM64_INS_STSMINL: + case ARM64_INS_STSMINB: + case ARM64_INS_STSMINLB: + case ARM64_INS_STSMINH: + case ARM64_INS_STSMINLH: +#endif + case ARM64_INS_LDUMAXB: + case ARM64_INS_LDUMAXAB: + case ARM64_INS_LDUMAXALB: + case ARM64_INS_LDUMAXLB: + case ARM64_INS_LDUMAXH: + case ARM64_INS_LDUMAXAH: + case ARM64_INS_LDUMAXALH: + case ARM64_INS_LDUMAXLH: + case ARM64_INS_LDUMAX: + case ARM64_INS_LDUMAXA: + case ARM64_INS_LDUMAXAL: + case ARM64_INS_LDUMAXL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMAX): - case CS_AARCH64(_INS_STUMAXL): - case CS_AARCH64(_INS_STUMAXB): - case CS_AARCH64(_INS_STUMAXLB): - case CS_AARCH64(_INS_STUMAXH): - case CS_AARCH64(_INS_STUMAXLH): -#endif - case CS_AARCH64(_INS_LDUMINB): - case CS_AARCH64(_INS_LDUMINAB): - case CS_AARCH64(_INS_LDUMINALB): - case CS_AARCH64(_INS_LDUMINLB): - case CS_AARCH64(_INS_LDUMINH): - case CS_AARCH64(_INS_LDUMINAH): - case CS_AARCH64(_INS_LDUMINALH): - case CS_AARCH64(_INS_LDUMINLH): - case CS_AARCH64(_INS_LDUMIN): - case CS_AARCH64(_INS_LDUMINA): - case CS_AARCH64(_INS_LDUMINAL): - case CS_AARCH64(_INS_LDUMINL): + case ARM64_INS_STUMAX: + case ARM64_INS_STUMAXL: + case ARM64_INS_STUMAXB: + case ARM64_INS_STUMAXLB: + case ARM64_INS_STUMAXH: + case ARM64_INS_STUMAXLH: +#endif + case ARM64_INS_LDUMINB: + case ARM64_INS_LDUMINAB: + case ARM64_INS_LDUMINALB: + case ARM64_INS_LDUMINLB: + case ARM64_INS_LDUMINH: + case ARM64_INS_LDUMINAH: + case ARM64_INS_LDUMINALH: + case ARM64_INS_LDUMINLH: + case ARM64_INS_LDUMIN: + case ARM64_INS_LDUMINA: + case ARM64_INS_LDUMINAL: + case ARM64_INS_LDUMINL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_STUMIN): - case CS_AARCH64(_INS_STUMINL): - case CS_AARCH64(_INS_STUMINB): - case CS_AARCH64(_INS_STUMINLB): - case CS_AARCH64(_INS_STUMINH): - case CS_AARCH64(_INS_STUMINLH): + case ARM64_INS_STUMIN: + case ARM64_INS_STUMINL: + case ARM64_INS_STUMINB: + case ARM64_INS_STUMINLB: + case ARM64_INS_STUMINH: + case ARM64_INS_STUMINLH: #endif return ldadd(insn); #endif - case CS_AARCH64(_INS_MADD): - case CS_AARCH64(_INS_MSUB): + case ARM64_INS_MADD: + case ARM64_INS_MSUB: #if CS_NEXT_VERSION >= 6 - if (insn->alias_id == AArch64_INS_ALIAS_MUL || - insn->alias_id == AArch64_INS_ALIAS_MNEG) { + if (insn->alias_id == AARCH64_INS_ALIAS_MUL || + insn->alias_id == AARCH64_INS_ALIAS_MNEG) { return mul(insn); } #endif return madd(insn); - case CS_AARCH64(_INS_MUL): + case ARM64_INS_MUL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_MNEG): + case ARM64_INS_MNEG: #endif return mul(insn); - case CS_AARCH64(_INS_MOV): - case CS_AARCH64(_INS_MOVZ): + case ARM64_INS_MOV: + case ARM64_INS_MOVZ: return mov(insn); - case CS_AARCH64(_INS_MOVK): + case ARM64_INS_MOVK: return movk(insn); - case CS_AARCH64(_INS_MOVN): + case ARM64_INS_MOVN: return movn(insn); - case CS_AARCH64(_INS_MSR): + case ARM64_INS_MSR: return msr(insn); - case CS_AARCH64(_INS_MRS): + case ARM64_INS_MRS: return mrs(insn); - case CS_AARCH64(_INS_NEG): + case ARM64_INS_NEG: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_MVN): - case CS_AARCH64(_INS_NGC): - case CS_AARCH64(_INS_NEGS): - case CS_AARCH64(_INS_NGCS): + case ARM64_INS_MVN: + case ARM64_INS_NGC: + case ARM64_INS_NEGS: + case ARM64_INS_NGCS: #endif return mvn(insn); - case CS_AARCH64(_INS_RBIT): + case ARM64_INS_RBIT: return rbit(insn); - case CS_AARCH64(_INS_REV): - case CS_AARCH64(_INS_REV32): - case CS_AARCH64(_INS_REV16): + case ARM64_INS_REV: + case ARM64_INS_REV32: + case ARM64_INS_REV16: return rev(insn); #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_RMIF): + case ARM64_INS_RMIF: return rmif(insn); #endif - case CS_AARCH64(_INS_SBFM): - case CS_AARCH64(_INS_UBFM): + case ARM64_INS_SBFM: + case ARM64_INS_UBFM: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_SBFIZ): - case CS_AARCH64(_INS_SBFX): - case CS_AARCH64(_INS_UBFIZ): - case CS_AARCH64(_INS_UBFX): + case ARM64_INS_SBFIZ: + case ARM64_INS_SBFX: + case ARM64_INS_UBFIZ: + case ARM64_INS_UBFX: #else - if (insn->alias_id == AArch64_INS_ALIAS_UXTH || - insn->alias_id == AArch64_INS_ALIAS_UXTB || - insn->alias_id == AArch64_INS_ALIAS_SXTH || - insn->alias_id == AArch64_INS_ALIAS_SXTB || - insn->alias_id == AArch64_INS_ALIAS_SXTW) { + if (insn->alias_id == AARCH64_INS_ALIAS_UXTH || + insn->alias_id == AARCH64_INS_ALIAS_UXTB || + insn->alias_id == AARCH64_INS_ALIAS_SXTH || + insn->alias_id == AARCH64_INS_ALIAS_SXTB || + insn->alias_id == AARCH64_INS_ALIAS_SXTW) { return sxt(insn); } #endif return usbfm(insn); - case CS_AARCH64(_INS_SDIV): + case ARM64_INS_SDIV: return sdiv(insn); #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_SETF8): - case CS_AARCH64(_INS_SETF16): + case ARM64_INS_SETF8: + case ARM64_INS_SETF16: return setf(insn); #endif - case CS_AARCH64(_INS_SMADDL): - case CS_AARCH64(_INS_SMSUBL): - case CS_AARCH64(_INS_UMADDL): - case CS_AARCH64(_INS_UMSUBL): + case ARM64_INS_SMADDL: + case ARM64_INS_SMSUBL: + case ARM64_INS_UMADDL: + case ARM64_INS_UMSUBL: #if CS_NEXT_VERSION >= 6 - if (insn->alias_id == AArch64_INS_ALIAS_SMULL || - insn->alias_id == AArch64_INS_ALIAS_UMULL || - insn->alias_id == AArch64_INS_ALIAS_SMNEGL || - insn->alias_id == AArch64_INS_ALIAS_UMNEGL) { + if (insn->alias_id == AARCH64_INS_ALIAS_SMULL || + insn->alias_id == AARCH64_INS_ALIAS_UMULL || + insn->alias_id == AARCH64_INS_ALIAS_SMNEGL || + insn->alias_id == AARCH64_INS_ALIAS_UMNEGL) { return smull(insn); } #endif return smaddl(insn); - case CS_AARCH64(_INS_SMULL): - case CS_AARCH64(_INS_UMULL): + case ARM64_INS_SMULL: + case ARM64_INS_UMULL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_SMNEGL): - case CS_AARCH64(_INS_UMNEGL): + case ARM64_INS_SMNEGL: + case ARM64_INS_UMNEGL: #endif return smull(insn); - case CS_AARCH64(_INS_SMULH): - case CS_AARCH64(_INS_UMULH): + case ARM64_INS_SMULH: + case ARM64_INS_UMULH: return smulh(insn); - case CS_AARCH64(_INS_STR): - case CS_AARCH64(_INS_STUR): - case CS_AARCH64(_INS_STRB): - case CS_AARCH64(_INS_STURB): - case CS_AARCH64(_INS_STRH): - case CS_AARCH64(_INS_STURH): - case CS_AARCH64(_INS_STLR): - case CS_AARCH64(_INS_STLRB): - case CS_AARCH64(_INS_STLRH): - case CS_AARCH64(_INS_STP): - case CS_AARCH64(_INS_STNP): - case CS_AARCH64(_INS_STXR): - case CS_AARCH64(_INS_STXRB): - case CS_AARCH64(_INS_STXRH): - case CS_AARCH64(_INS_STXP): - case CS_AARCH64(_INS_STLXR): - case CS_AARCH64(_INS_STLXRB): - case CS_AARCH64(_INS_STLXRH): - case CS_AARCH64(_INS_STLXP): - case CS_AARCH64(_INS_STTR): - case CS_AARCH64(_INS_STTRB): - case CS_AARCH64(_INS_STTRH): + case ARM64_INS_STR: + case ARM64_INS_STUR: + case ARM64_INS_STRB: + case ARM64_INS_STURB: + case ARM64_INS_STRH: + case ARM64_INS_STURH: + case ARM64_INS_STLR: + case ARM64_INS_STLRB: + case ARM64_INS_STLRH: + case ARM64_INS_STP: + case ARM64_INS_STNP: + case ARM64_INS_STXR: + case ARM64_INS_STXRB: + case ARM64_INS_STXRH: + case ARM64_INS_STXP: + case ARM64_INS_STLXR: + case ARM64_INS_STLXRB: + case ARM64_INS_STLXRH: + case ARM64_INS_STLXP: + case ARM64_INS_STTR: + case ARM64_INS_STTRB: + case ARM64_INS_STTRH: #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_STLLR): - case CS_AARCH64(_INS_STLLRB): - case CS_AARCH64(_INS_STLLRH): - case CS_AARCH64(_INS_STLUR): - case CS_AARCH64(_INS_STLURB): - case CS_AARCH64(_INS_STLURH): + case ARM64_INS_STLLR: + case ARM64_INS_STLLRB: + case ARM64_INS_STLLRH: + case ARM64_INS_STLUR: + case ARM64_INS_STLURB: + case ARM64_INS_STLURH: #endif return str(insn); #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_SWP): - case CS_AARCH64(_INS_SWPA): - case CS_AARCH64(_INS_SWPAL): - case CS_AARCH64(_INS_SWPL): - case CS_AARCH64(_INS_SWPB): - case CS_AARCH64(_INS_SWPAB): - case CS_AARCH64(_INS_SWPALB): - case CS_AARCH64(_INS_SWPLB): - case CS_AARCH64(_INS_SWPH): - case CS_AARCH64(_INS_SWPAH): - case CS_AARCH64(_INS_SWPALH): - case CS_AARCH64(_INS_SWPLH): + case ARM64_INS_SWP: + case ARM64_INS_SWPA: + case ARM64_INS_SWPAL: + case ARM64_INS_SWPL: + case ARM64_INS_SWPB: + case ARM64_INS_SWPAB: + case ARM64_INS_SWPALB: + case ARM64_INS_SWPLB: + case ARM64_INS_SWPH: + case ARM64_INS_SWPAH: + case ARM64_INS_SWPALH: + case ARM64_INS_SWPLH: return swp(insn); #endif - case CS_AARCH64(_INS_SXTB): - case CS_AARCH64(_INS_SXTH): - case CS_AARCH64(_INS_SXTW): - case CS_AARCH64(_INS_UXTB): - case CS_AARCH64(_INS_UXTH): + case ARM64_INS_SXTB: + case ARM64_INS_SXTH: + case ARM64_INS_SXTW: + case ARM64_INS_UXTB: + case ARM64_INS_UXTH: return sxt(insn); - case CS_AARCH64(_INS_TBNZ): - case CS_AARCH64(_INS_TBZ): + case ARM64_INS_TBNZ: + case ARM64_INS_TBZ: return tbz(insn); #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_TST): + case ARM64_INS_TST: return tst(insn); #endif - case CS_AARCH64(_INS_UDIV): + case ARM64_INS_UDIV: return udiv(insn); default: break; diff --git a/librz/arch/isa/arm/asm-arm.h b/librz/arch/isa/arm/asm-arm.h index 1cd11e600fb..e669817688c 100644 --- a/librz/arch/isa/arm/asm-arm.h +++ b/librz/arch/isa/arm/asm-arm.h @@ -5,7 +5,6 @@ #define _INCLUDE_ARMASS_H_ #include -#include "aarch64_meta_macros.h" int armass_assemble(const char *str, ut64 off, int thumb); diff --git a/librz/arch/isa/x86/common.c b/librz/arch/isa/x86/common.c index 0e0eafb8101..1c3bf4813ae 100644 --- a/librz/arch/isa/x86/common.c +++ b/librz/arch/isa/x86/common.c @@ -739,9 +739,9 @@ RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, return x86_il_get_reg_bits(op.reg, analysis_bits, pc); case X86_OP_IMM: /* Immediate values are always sign extended */ - return SN(op.size * BITS_PER_BYTE, op.imm); + return SN((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, op.imm); case X86_OP_MEM: - return LOADW(BITS_PER_BYTE * op.size, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc)); + return LOADW((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc)); default: return NULL; } diff --git a/librz/arch/p/analysis/analysis_arm_cs.c b/librz/arch/p/analysis/analysis_arm_cs.c index 48fd939f8ea..4c016996f7b 100644 --- a/librz/arch/p/analysis/analysis_arm_cs.c +++ b/librz/arch/p/analysis/analysis_arm_cs.c @@ -4,6 +4,10 @@ #include #include #include + +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #include #include @@ -93,8 +97,10 @@ static const char *shift_type_name(arm_shifter type) { return "lsr_reg"; case ARM_SFT_ROR_REG: return "ror_reg"; +#if CS_NEXT_VERSION < 6 case ARM_SFT_RRX_REG: return "rrx_reg"; +#endif default: return ""; } @@ -181,11 +187,11 @@ static const char *vector_data_type_name(arm_vectordata_type type) { } } -static bool cc_holds_cond(CS_aarch64_cc() cc) { +static bool cc_holds_cond(ARM64CC_CondCode cc) { #if CS_NEXT_VERSION >= 6 - return (cc != CS_AARCH64CC(_Invalid) && cc != CS_AARCH64CC(_AL) && cc != CS_AARCH64CC(_NV)); + return (cc != ARM64CC_Invalid && cc != ARM64CC_AL && cc != ARM64CC_NV); #else - return (cc != CS_AARCH64CC(_INVALID) && cc != CS_AARCH64CC(_AL) && cc != CS_AARCH64CC(_NV)); + return (cc != ARM64CC_INVALID && cc != ARM64CC_AL && cc != ARM64CC_NV); #endif } @@ -274,7 +280,9 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { case ARM_SFT_LSL_REG: case ARM_SFT_LSR_REG: case ARM_SFT_ROR_REG: +#if CS_NEXT_VERSION < 6 case ARM_SFT_RRX_REG: +#endif pj_ks(pj, "type", shift_type_name(op->shift.type)); pj_ks(pj, "value", cs_reg_name(handle, op->shift.value)); break; @@ -336,94 +344,94 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { pj_free(pj); } -static const char *cc_name64(CS_aarch64_cc() cc) { +static const char *cc_name64(ARM64CC_CondCode cc) { switch (cc) { - case CS_AARCH64CC(_EQ): // Equal + case ARM64CC_EQ: // Equal return "eq"; - case CS_AARCH64CC(_NE): // Not equal: Not equal, or unordered + case ARM64CC_NE: // Not equal: Not equal, or unordered return "ne"; - case CS_AARCH64CC(_HS): // Unsigned higher or same: >, ==, or unordered + case ARM64CC_HS: // Unsigned higher or same: >, ==, or unordered return "hs"; - case CS_AARCH64CC(_LO): // Unsigned lower or same: Less than + case ARM64CC_LO: // Unsigned lower or same: Less than return "lo"; - case CS_AARCH64CC(_MI): // Minus, negative: Less than + case ARM64CC_MI: // Minus, negative: Less than return "mi"; - case CS_AARCH64CC(_PL): // Plus, positive or zero: >, ==, or unordered + case ARM64CC_PL: // Plus, positive or zero: >, ==, or unordered return "pl"; - case CS_AARCH64CC(_VS): // Overflow: Unordered + case ARM64CC_VS: // Overflow: Unordered return "vs"; - case CS_AARCH64CC(_VC): // No overflow: Ordered + case ARM64CC_VC: // No overflow: Ordered return "vc"; - case CS_AARCH64CC(_HI): // Unsigned higher: Greater than, or unordered + case ARM64CC_HI: // Unsigned higher: Greater than, or unordered return "hi"; - case CS_AARCH64CC(_LS): // Unsigned lower or same: Less than or equal + case ARM64CC_LS: // Unsigned lower or same: Less than or equal return "ls"; - case CS_AARCH64CC(_GE): // Greater than or equal: Greater than or equal + case ARM64CC_GE: // Greater than or equal: Greater than or equal return "ge"; - case CS_AARCH64CC(_LT): // Less than: Less than, or unordered + case ARM64CC_LT: // Less than: Less than, or unordered return "lt"; - case CS_AARCH64CC(_GT): // Signed greater than: Greater than + case ARM64CC_GT: // Signed greater than: Greater than return "gt"; - case CS_AARCH64CC(_LE): // Signed less than or equal: <, ==, or unordered + case ARM64CC_LE: // Signed less than or equal: <, ==, or unordered return "le"; default: return ""; } } -static const char *extender_name(CS_aarch64_extender() extender) { +static const char *extender_name(aarch64_extender extender) { switch (extender) { - case CS_AARCH64(_EXT_UXTB): + case ARM64_EXT_UXTB: return "uxtb"; - case CS_AARCH64(_EXT_UXTH): + case ARM64_EXT_UXTH: return "uxth"; - case CS_AARCH64(_EXT_UXTW): + case ARM64_EXT_UXTW: return "uxtw"; - case CS_AARCH64(_EXT_UXTX): + case ARM64_EXT_UXTX: return "uxtx"; - case CS_AARCH64(_EXT_SXTB): + case ARM64_EXT_SXTB: return "sxtb"; - case CS_AARCH64(_EXT_SXTH): + case ARM64_EXT_SXTH: return "sxth"; - case CS_AARCH64(_EXT_SXTW): + case ARM64_EXT_SXTW: return "sxtw"; - case CS_AARCH64(_EXT_SXTX): + case ARM64_EXT_SXTX: return "sxtx"; default: return ""; } } -static const char *vas_name(CS_aarch64_vas() vas) { +static const char *vas_name(ARM64Layout_VectorLayout vas) { switch (vas) { - case CS_AARCH64_VL_(8B): + case ARM64LAYOUT_VL_8B: return "8b"; - case CS_AARCH64_VL_(16B): + case ARM64LAYOUT_VL_16B: return "16b"; - case CS_AARCH64_VL_(4H): + case ARM64LAYOUT_VL_4H: return "4h"; - case CS_AARCH64_VL_(8H): + case ARM64LAYOUT_VL_8H: return "8h"; - case CS_AARCH64_VL_(2S): + case ARM64LAYOUT_VL_2S: return "2s"; - case CS_AARCH64_VL_(4S): + case ARM64LAYOUT_VL_4S: return "4s"; - case CS_AARCH64_VL_(2D): + case ARM64LAYOUT_VL_2D: return "2d"; - case CS_AARCH64_VL_(1D): + case ARM64LAYOUT_VL_1D: return "1d"; - case CS_AARCH64_VL_(1Q): + case ARM64LAYOUT_VL_1Q: return "1q"; #if CS_API_MAJOR > 4 && CS_NEXT_VERSION < 6 - case CS_AARCH64_VL_(1B): + case ARM64LAYOUT_VL_1B: return "8b"; - case CS_AARCH64_VL_(4B): + case ARM64LAYOUT_VL_4B: return "8b"; - case CS_AARCH64_VL_(2H): + case ARM64LAYOUT_VL_2H: return "2h"; - case CS_AARCH64_VL_(1H): + case ARM64LAYOUT_VL_1H: return "1h"; - case CS_AARCH64_VL_(1S): + case ARM64LAYOUT_VL_1S: return "1s"; #endif default: @@ -456,42 +464,42 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { } pj_o(pj); pj_ka(pj, "operands"); - CS_cs_aarch64() *x = &insn->detail->CS_aarch64_; + cs_arm64 *x = &insn->detail->arm64; for (i = 0; i < x->op_count; i++) { - CS_aarch64_op() *op = x->operands + i; + cs_arm64_op *op = x->operands + i; pj_o(pj); switch (op->type) { - case CS_AARCH64(_OP_REG): + case ARM64_OP_REG: pj_ks(pj, "type", "reg"); pj_ks(pj, "value", cs_reg_name(handle, op->reg)); break; - case CS_AARCH64(_OP_REG_MRS): + case ARM64_OP_REG_MRS: pj_ks(pj, "type", "reg_mrs"); // TODO value break; - case CS_AARCH64(_OP_REG_MSR): + case ARM64_OP_REG_MSR: pj_ks(pj, "type", "reg_msr"); // TODO value break; - case CS_AARCH64(_OP_IMM): + case ARM64_OP_IMM: pj_ks(pj, "type", "imm"); pj_kN(pj, "value", op->imm); break; - case CS_AARCH64(_OP_MEM): + case ARM64_OP_MEM: pj_ks(pj, "type", "mem"); - if (op->mem.base != CS_AARCH64(_REG_INVALID)) { + if (op->mem.base != ARM64_REG_INVALID) { pj_ks(pj, "base", cs_reg_name(handle, op->mem.base)); } - if (op->mem.index != CS_AARCH64(_REG_INVALID)) { + if (op->mem.index != ARM64_REG_INVALID) { pj_ks(pj, "index", cs_reg_name(handle, op->mem.index)); } pj_ki(pj, "disp", op->mem.disp); break; - case CS_AARCH64(_OP_FP): + case ARM64_OP_FP: pj_ks(pj, "type", "fp"); pj_kd(pj, "value", op->fp); break; - case CS_AARCH64(_OP_CIMM): + case ARM64_OP_CIMM: pj_ks(pj, "type", "cimm"); pj_kN(pj, "value", op->imm); break; @@ -525,37 +533,37 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { pj_ki(pj, "value", op->barrier - 1); break; #else - case AArch64_OP_SYSALIAS: + case AARCH64_OP_SYSALIAS: switch (op->sysop.sub_type) { default: pj_ks(pj, "type", "sys"); pj_kn(pj, "value", op->sysop.alias.raw_val); break; - case AArch64_OP_PSTATEIMM0_1: + case AARCH64_OP_PSTATEIMM0_1: pj_ks(pj, "type", "pstate"); pj_ki(pj, "value", op->sysop.alias.pstateimm0_1); break; - case AArch64_OP_PSTATEIMM0_15: + case AARCH64_OP_PSTATEIMM0_15: pj_ks(pj, "type", "pstate"); switch (op->sysop.alias.pstateimm0_15) { - case AArch64_PSTATEIMM0_15_SPSEL: + case AARCH64_PSTATEIMM0_15_SPSEL: pj_ks(pj, "value", "spsel"); break; - case AArch64_PSTATEIMM0_15_DAIFSET: + case AARCH64_PSTATEIMM0_15_DAIFSET: pj_ks(pj, "value", "daifset"); break; - case AArch64_PSTATEIMM0_15_DAIFCLR: + case AARCH64_PSTATEIMM0_15_DAIFCLR: pj_ks(pj, "value", "daifclr"); break; default: pj_ki(pj, "value", op->sysop.alias.pstateimm0_15); } break; - case AArch64_OP_PRFM: + case AARCH64_OP_PRFM: pj_ks(pj, "type", "prefetch"); pj_ki(pj, "value", op->sysop.alias.prfm); break; - case AArch64_OP_DB: + case AARCH64_OP_DB: pj_ks(pj, "type", "prefetch"); pj_ki(pj, "value", op->sysop.alias.db); break; @@ -566,22 +574,22 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { pj_ks(pj, "type", "invalid"); break; } - if (op->shift.type != CS_AARCH64(_SFT_INVALID)) { + if (op->shift.type != ARM64_SFT_INVALID) { pj_ko(pj, "shift"); switch (op->shift.type) { - case CS_AARCH64(_SFT_LSL): + case ARM64_SFT_LSL: pj_ks(pj, "type", "lsl"); break; - case CS_AARCH64(_SFT_MSL): + case ARM64_SFT_MSL: pj_ks(pj, "type", "msl"); break; - case CS_AARCH64(_SFT_LSR): + case ARM64_SFT_LSR: pj_ks(pj, "type", "lsr"); break; - case CS_AARCH64(_SFT_ASR): + case ARM64_SFT_ASR: pj_ks(pj, "type", "asr"); break; - case CS_AARCH64(_SFT_ROR): + case ARM64_SFT_ROR: pj_ks(pj, "type", "ror"); break; default: @@ -590,19 +598,19 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { pj_kn(pj, "value", (ut64)op->shift.value); pj_end(pj); } - if (op->ext != CS_AARCH64(_EXT_INVALID)) { + if (op->ext != ARM64_EXT_INVALID) { pj_ks(pj, "ext", extender_name(op->ext)); } if (op->vector_index != -1) { pj_ki(pj, "vector_index", op->vector_index); } #if CS_NEXT_VERSION < 6 - if (op->vas != CS_AARCH64_VL_(INVALID)) { + if (op->vas != ARM64LAYOUT_VL_INVALID)) { #else - if (op->vas != AArch64Layout_Invalid) { + if (op->vas != AARCH64LAYOUT_INVALID) { #endif - pj_ks(pj, "vas", vas_name(op->vas)); - } + pj_ks(pj, "vas", vas_name(op->vas)); + } #if CS_API_MAJOR == 4 if (op->vess != ARM64_VESS_INVALID) { pj_ks(pj, "vess", vess_name(op->vess)); @@ -660,27 +668,27 @@ static int cond_cs2rz_32(int cc) { } static int cond_cs2rz_64(int cc) { - if (cc == CS_AARCH64CC(_AL) || cc < 0) { + if (cc == ARM64CC_AL || cc < 0) { cc = RZ_TYPE_COND_AL; } else { switch (cc) { - case CS_AARCH64CC(_EQ): cc = RZ_TYPE_COND_EQ; break; - case CS_AARCH64CC(_NE): cc = RZ_TYPE_COND_NE; break; - case CS_AARCH64CC(_HS): cc = RZ_TYPE_COND_HS; break; - case CS_AARCH64CC(_LO): cc = RZ_TYPE_COND_LO; break; - case CS_AARCH64CC(_MI): cc = RZ_TYPE_COND_MI; break; - case CS_AARCH64CC(_PL): cc = RZ_TYPE_COND_PL; break; - case CS_AARCH64CC(_VS): cc = RZ_TYPE_COND_VS; break; - case CS_AARCH64CC(_VC): cc = RZ_TYPE_COND_VC; break; - case CS_AARCH64CC(_HI): cc = RZ_TYPE_COND_HI; break; - case CS_AARCH64CC(_LS): cc = RZ_TYPE_COND_LS; break; - case CS_AARCH64CC(_GE): cc = RZ_TYPE_COND_GE; break; - case CS_AARCH64CC(_LT): cc = RZ_TYPE_COND_LT; break; - case CS_AARCH64CC(_GT): cc = RZ_TYPE_COND_GT; break; - case CS_AARCH64CC(_LE): cc = RZ_TYPE_COND_LE; break; - case CS_AARCH64CC(_NV): cc = RZ_TYPE_COND_AL; break; + case ARM64CC_EQ: cc = RZ_TYPE_COND_EQ; break; + case ARM64CC_NE: cc = RZ_TYPE_COND_NE; break; + case ARM64CC_HS: cc = RZ_TYPE_COND_HS; break; + case ARM64CC_LO: cc = RZ_TYPE_COND_LO; break; + case ARM64CC_MI: cc = RZ_TYPE_COND_MI; break; + case ARM64CC_PL: cc = RZ_TYPE_COND_PL; break; + case ARM64CC_VS: cc = RZ_TYPE_COND_VS; break; + case ARM64CC_VC: cc = RZ_TYPE_COND_VC; break; + case ARM64CC_HI: cc = RZ_TYPE_COND_HI; break; + case ARM64CC_LS: cc = RZ_TYPE_COND_LS; break; + case ARM64CC_GE: cc = RZ_TYPE_COND_GE; break; + case ARM64CC_LT: cc = RZ_TYPE_COND_LT; break; + case ARM64CC_GT: cc = RZ_TYPE_COND_GT; break; + case ARM64CC_LE: cc = RZ_TYPE_COND_LE; break; + case ARM64CC_NV: cc = RZ_TYPE_COND_AL; break; #if CS_NEXT_VERSION >= 6 - case CS_AARCH64CC(_Invalid): cc = RZ_TYPE_COND_AL; break; + case ARM64CC_Invalid: cc = RZ_TYPE_COND_AL; break; #endif } } @@ -689,23 +697,23 @@ static int cond_cs2rz_64(int cc) { #if CS_NEXT_VERSION >= 6 static bool is_system_hint(const cs_insn *insn) { - rz_return_val_if_fail(insn && insn->id == AArch64_INS_HINT, false); + rz_return_val_if_fail(insn && insn->id == AARCH64_INS_HINT, false); switch (insn->alias_id) { default: return false; - case AArch64_INS_ALIAS_PACIA1716: - case AArch64_INS_ALIAS_PACIASP: - case AArch64_INS_ALIAS_PACIAZ: - case AArch64_INS_ALIAS_PACIB1716: - case AArch64_INS_ALIAS_PACIBSP: - case AArch64_INS_ALIAS_PACIBZ: - case AArch64_INS_ALIAS_AUTIA1716: - case AArch64_INS_ALIAS_AUTIASP: - case AArch64_INS_ALIAS_AUTIAZ: - case AArch64_INS_ALIAS_AUTIB1716: - case AArch64_INS_ALIAS_AUTIBSP: - case AArch64_INS_ALIAS_AUTIBZ: - case AArch64_INS_ALIAS_XPACLRI: + case AARCH64_INS_ALIAS_PACIA1716: + case AARCH64_INS_ALIAS_PACIASP: + case AARCH64_INS_ALIAS_PACIAZ: + case AARCH64_INS_ALIAS_PACIB1716: + case AARCH64_INS_ALIAS_PACIBSP: + case AARCH64_INS_ALIAS_PACIBZ: + case AARCH64_INS_ALIAS_AUTIA1716: + case AARCH64_INS_ALIAS_AUTIASP: + case AARCH64_INS_ALIAS_AUTIAZ: + case AARCH64_INS_ALIAS_AUTIB1716: + case AARCH64_INS_ALIAS_AUTIBSP: + case AARCH64_INS_ALIAS_AUTIBZ: + case AARCH64_INS_ALIAS_XPACLRI: return true; } } @@ -732,34 +740,34 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } #else /* grab family */ - if (cs_insn_group(handle, insn, AArch64_FEATURE_HasAES)) { + if (cs_insn_group(handle, insn, AARCH64_FEATURE_HASAES)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; - } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasCRC)) { + } else if (cs_insn_group(handle, insn, AARCH64_FEATURE_HASCRC)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; - } else if (cs_insn_group(handle, insn, AArch64_GRP_PRIVILEGE)) { + } else if (cs_insn_group(handle, insn, AARCH64_GRP_PRIVILEGE)) { op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; - } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasNEON)) { + } else if (cs_insn_group(handle, insn, AARCH64_FEATURE_HASNEON)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; - } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasMTE)) { + } else if (cs_insn_group(handle, insn, AARCH64_FEATURE_HASMTE)) { op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; - } else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasFPARMv8)) { + } else if (cs_insn_group(handle, insn, AARCH64_FEATURE_HASFPARMV8)) { op->family = RZ_ANALYSIS_OP_FAMILY_FPU; } else { op->family = RZ_ANALYSIS_OP_FAMILY_CPU; } #endif - op->cond = cond_cs2rz_64(insn->detail->CS_aarch64_.cc); + op->cond = cond_cs2rz_64(insn->detail->arm64.cc); if (op->cond == RZ_TYPE_COND_NV) { op->type = RZ_ANALYSIS_OP_TYPE_NOP; return; } - switch (insn->detail->CS_aarch64_.cc) { - case CS_AARCH64CC(_GE): - case CS_AARCH64CC(_GT): - case CS_AARCH64CC(_LE): - case CS_AARCH64CC(_LT): + switch (insn->detail->arm64.cc) { + case ARM64CC_GE: + case ARM64CC_GT: + case ARM64CC_LE: + case ARM64CC_LT: op->sign = true; break; default: @@ -768,58 +776,58 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { switch (insn->id) { #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_PACDA): - case CS_AARCH64(_INS_PACDB): - case CS_AARCH64(_INS_PACDZA): - case CS_AARCH64(_INS_PACDZB): - case CS_AARCH64(_INS_PACGA): - case CS_AARCH64(_INS_PACIA): - case CS_AARCH64(_INS_PACIB): + case ARM64_INS_PACDA: + case ARM64_INS_PACDB: + case ARM64_INS_PACDZA: + case ARM64_INS_PACDZB: + case ARM64_INS_PACGA: + case ARM64_INS_PACIA: + case ARM64_INS_PACIB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_PACIA1716): - case CS_AARCH64(_INS_PACIASP): - case CS_AARCH64(_INS_PACIAZ): - case CS_AARCH64(_INS_PACIB1716): - case CS_AARCH64(_INS_PACIBSP): - case CS_AARCH64(_INS_PACIBZ): + case ARM64_INS_PACIA1716: + case ARM64_INS_PACIASP: + case ARM64_INS_PACIAZ: + case ARM64_INS_PACIB1716: + case ARM64_INS_PACIBSP: + case ARM64_INS_PACIBZ: #endif - case CS_AARCH64(_INS_PACIZA): - case CS_AARCH64(_INS_PACIZB): - case CS_AARCH64(_INS_AUTDA): - case CS_AARCH64(_INS_AUTDB): - case CS_AARCH64(_INS_AUTDZA): - case CS_AARCH64(_INS_AUTDZB): - case CS_AARCH64(_INS_AUTIA): - case CS_AARCH64(_INS_AUTIB): + case ARM64_INS_PACIZA: + case ARM64_INS_PACIZB: + case ARM64_INS_AUTDA: + case ARM64_INS_AUTDB: + case ARM64_INS_AUTDZA: + case ARM64_INS_AUTDZB: + case ARM64_INS_AUTIA: + case ARM64_INS_AUTIB: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_AUTIA1716): - case CS_AARCH64(_INS_AUTIASP): - case CS_AARCH64(_INS_AUTIAZ): - case CS_AARCH64(_INS_AUTIB1716): - case CS_AARCH64(_INS_AUTIBSP): - case CS_AARCH64(_INS_AUTIBZ): - case CS_AARCH64(_INS_XPACLRI): + case ARM64_INS_AUTIA1716: + case ARM64_INS_AUTIASP: + case ARM64_INS_AUTIAZ: + case ARM64_INS_AUTIB1716: + case ARM64_INS_AUTIBSP: + case ARM64_INS_AUTIBZ: + case ARM64_INS_XPACLRI: #endif - case CS_AARCH64(_INS_AUTIZA): - case CS_AARCH64(_INS_AUTIZB): - case CS_AARCH64(_INS_XPACD): - case CS_AARCH64(_INS_XPACI): + case ARM64_INS_AUTIZA: + case ARM64_INS_AUTIZB: + case ARM64_INS_XPACD: + case ARM64_INS_XPACI: op->type = RZ_ANALYSIS_OP_TYPE_CMP; op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; break; #endif - case CS_AARCH64(_INS_SVC): + case ARM64_INS_SVC: op->type = RZ_ANALYSIS_OP_TYPE_SWI; op->val = IMM64(0); break; - case CS_AARCH64(_INS_ADRP): - case CS_AARCH64(_INS_ADR): + case ARM64_INS_ADRP: + case ARM64_INS_ADR: op->type = RZ_ANALYSIS_OP_TYPE_LEA; op->ptr = IMM64(1); break; - case CS_AARCH64(_INS_HINT): + case ARM64_INS_HINT: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_NOP): + case ARM64_INS_NOP: #else if (is_system_hint(insn)) { op->type = RZ_ANALYSIS_OP_TYPE_CMP; @@ -830,13 +838,13 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->type = RZ_ANALYSIS_OP_TYPE_NOP; op->cycles = 1; break; - case CS_AARCH64(_INS_SUB): - if (ISREG64(0) && REGID64(0) == CS_AARCH64(_REG_SP)) { + case ARM64_INS_SUB: + if (ISREG64(0) && REGID64(0) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; if (ISIMM64(1)) { // sub sp, 0x54 op->stackptr = IMM(1); - } else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == CS_AARCH64(_REG_SP)) { + } else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == ARM64_REG_SP) { // sub sp, sp, 0x10 op->stackptr = IMM64(2); } @@ -844,31 +852,31 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } op->cycles = 1; /* fallthru */ - case CS_AARCH64(_INS_MSUB): + case ARM64_INS_MSUB: op->type = RZ_ANALYSIS_OP_TYPE_SUB; break; - case CS_AARCH64(_INS_FDIV): - case CS_AARCH64(_INS_SDIV): - case CS_AARCH64(_INS_UDIV): + case ARM64_INS_FDIV: + case ARM64_INS_SDIV: + case ARM64_INS_UDIV: op->cycles = 4; op->type = RZ_ANALYSIS_OP_TYPE_DIV; break; - case CS_AARCH64(_INS_MUL): - case CS_AARCH64(_INS_SMULL): - case CS_AARCH64(_INS_FMUL): - case CS_AARCH64(_INS_UMULL): + case ARM64_INS_MUL: + case ARM64_INS_SMULL: + case ARM64_INS_FMUL: + case ARM64_INS_UMULL: /* TODO: if next instruction is also a MUL, cycles are /=2 */ /* also known as Register Indexing Addressing */ op->cycles = 4; op->type = RZ_ANALYSIS_OP_TYPE_MUL; break; - case CS_AARCH64(_INS_ADD): - if (ISREG64(0) && REGID64(0) == CS_AARCH64(_REG_SP)) { + case ARM64_INS_ADD: + if (ISREG64(0) && REGID64(0) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; if (ISIMM64(1)) { // add sp, 0x54 op->stackptr = -(st64)IMM(1); - } else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == CS_AARCH64(_REG_SP)) { + } else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == ARM64_REG_SP) { // add sp, sp, 0x10 op->stackptr = -(st64)IMM64(2); } @@ -878,24 +886,24 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } op->cycles = 1; /* fallthru */ - case CS_AARCH64(_INS_ADC): - // case CS_AARCH64(_INS_ADCS): - case CS_AARCH64(_INS_UMADDL): - case CS_AARCH64(_INS_SMADDL): - case CS_AARCH64(_INS_FMADD): - case CS_AARCH64(_INS_MADD): + case ARM64_INS_ADC: + // case ARM64_INS_ADCS: + case ARM64_INS_UMADDL: + case ARM64_INS_SMADDL: + case ARM64_INS_FMADD: + case ARM64_INS_MADD: op->type = RZ_ANALYSIS_OP_TYPE_ADD; break; - case CS_AARCH64(_INS_CSEL): - case CS_AARCH64(_INS_FCSEL): + case ARM64_INS_CSEL: + case ARM64_INS_FCSEL: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CSET): - case CS_AARCH64(_INS_CINC): + case ARM64_INS_CSET: + case ARM64_INS_CINC: #endif op->type = RZ_ANALYSIS_OP_TYPE_CMOV; break; - case CS_AARCH64(_INS_MOV): - if (REGID64(0) == CS_AARCH64(_REG_SP)) { + case ARM64_INS_MOV: + if (REGID64(0) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_RESET; op->stackptr = 0; } @@ -904,106 +912,106 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } op->cycles = 1; /* fallthru */ - case CS_AARCH64(_INS_MOVI): - case CS_AARCH64(_INS_MOVK): - case CS_AARCH64(_INS_MOVN): - case CS_AARCH64(_INS_SMOV): - case CS_AARCH64(_INS_UMOV): - case CS_AARCH64(_INS_FMOV): - case CS_AARCH64(_INS_UBFM): - case CS_AARCH64(_INS_BIC): + case ARM64_INS_MOVI: + case ARM64_INS_MOVK: + case ARM64_INS_MOVN: + case ARM64_INS_SMOV: + case ARM64_INS_UMOV: + case ARM64_INS_FMOV: + case ARM64_INS_UBFM: + case ARM64_INS_BIC: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_SBFX): - case CS_AARCH64(_INS_UBFX): - case CS_AARCH64(_INS_SBFIZ): - case CS_AARCH64(_INS_UBFIZ): - case CS_AARCH64(_INS_BFI): - case CS_AARCH64(_INS_BFXIL): + case ARM64_INS_SBFX: + case ARM64_INS_UBFX: + case ARM64_INS_SBFIZ: + case ARM64_INS_UBFIZ: + case ARM64_INS_BFI: + case ARM64_INS_BFXIL: #endif op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; - case CS_AARCH64(_INS_MRS): - case CS_AARCH64(_INS_MSR): + case ARM64_INS_MRS: + case ARM64_INS_MSR: op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; break; - case CS_AARCH64(_INS_MOVZ): + case ARM64_INS_MOVZ: op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->ptr = 0LL; op->ptrsize = 8; op->val = IMM64(1); break; - case CS_AARCH64(_INS_UXTB): - case CS_AARCH64(_INS_SXTB): + case ARM64_INS_UXTB: + case ARM64_INS_SXTB: op->type = RZ_ANALYSIS_OP_TYPE_CAST; op->ptr = 0LL; op->ptrsize = 1; break; - case CS_AARCH64(_INS_UXTH): - case CS_AARCH64(_INS_SXTH): + case ARM64_INS_UXTH: + case ARM64_INS_SXTH: op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->ptr = 0LL; op->ptrsize = 2; break; - case CS_AARCH64(_INS_UXTW): - case CS_AARCH64(_INS_SXTW): + case ARM64_INS_UXTW: + case ARM64_INS_SXTW: op->type = RZ_ANALYSIS_OP_TYPE_MOV; op->ptr = 0LL; op->ptrsize = 4; break; - case CS_AARCH64(_INS_BRK): - case CS_AARCH64(_INS_HLT): + case ARM64_INS_BRK: + case ARM64_INS_HLT: op->type = RZ_ANALYSIS_OP_TYPE_TRAP; // hlt stops the process, not skips some cycles like in x86 break; - case CS_AARCH64(_INS_DMB): - case CS_AARCH64(_INS_DSB): - case CS_AARCH64(_INS_ISB): + case ARM64_INS_DMB: + case ARM64_INS_DSB: + case ARM64_INS_ISB: op->family = RZ_ANALYSIS_OP_FAMILY_THREAD; #if CS_NEXT_VERSION < 6 // intentional fallthrough - case CS_AARCH64(_INS_IC): // instruction cache invalidate - case CS_AARCH64(_INS_DC): // data cache invalidate + case ARM64_INS_IC: // instruction cache invalidate + case ARM64_INS_DC: // data cache invalidate #endif op->type = RZ_ANALYSIS_OP_TYPE_SYNC; // or cache break; // XXX unimplemented instructions - case CS_AARCH64(_INS_DUP): - case CS_AARCH64(_INS_XTN): - case CS_AARCH64(_INS_XTN2): - case CS_AARCH64(_INS_REV64): - case CS_AARCH64(_INS_EXT): - case CS_AARCH64(_INS_INS): + case ARM64_INS_DUP: + case ARM64_INS_XTN: + case ARM64_INS_XTN2: + case ARM64_INS_REV64: + case ARM64_INS_EXT: + case ARM64_INS_INS: op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; - case CS_AARCH64(_INS_LSL): + case ARM64_INS_LSL: op->cycles = 1; /* fallthru */ - case CS_AARCH64(_INS_SHL): - case CS_AARCH64(_INS_USHLL): + case ARM64_INS_SHL: + case ARM64_INS_USHLL: op->type = RZ_ANALYSIS_OP_TYPE_SHL; break; - case CS_AARCH64(_INS_LSR): + case ARM64_INS_LSR: op->cycles = 1; op->type = RZ_ANALYSIS_OP_TYPE_SHR; break; - case CS_AARCH64(_INS_ASR): + case ARM64_INS_ASR: op->cycles = 1; op->type = RZ_ANALYSIS_OP_TYPE_SAR; break; - case CS_AARCH64(_INS_NEG): + case ARM64_INS_NEG: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_NEGS): + case ARM64_INS_NEGS: #endif op->type = RZ_ANALYSIS_OP_TYPE_NOT; break; - case CS_AARCH64(_INS_FCMP): - case CS_AARCH64(_INS_CCMP): - case CS_AARCH64(_INS_CCMN): + case ARM64_INS_FCMP: + case ARM64_INS_CCMP: + case ARM64_INS_CCMN: #if CS_NEXT_VERSION < 6 - case CS_AARCH64(_INS_CMP): - case CS_AARCH64(_INS_CMN): - case CS_AARCH64(_INS_TST): + case ARM64_INS_CMP: + case ARM64_INS_CMN: + case ARM64_INS_TST: #endif if (ISIMM64(1)) { op->val = IMM64(1); @@ -1011,8 +1019,8 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->type = RZ_ANALYSIS_OP_TYPE_CMP; break; #if CS_NEXT_VERSION >= 6 - case CS_AARCH64(_INS_ADDS): - if (is_alias64(insn, AArch64_INS_ALIAS_CMN)) { + case ARM64_INS_ADDS: + if (is_alias64(insn, AARCH64_INS_ALIAS_CMN)) { op->type = RZ_ANALYSIS_OP_TYPE_CMP; } else { op->type = RZ_ANALYSIS_OP_TYPE_ADD; @@ -1021,8 +1029,8 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->val = IMM64(1); } break; - case CS_AARCH64(_INS_SUBS): - if (is_alias64(insn, AArch64_INS_ALIAS_CMP)) { + case ARM64_INS_SUBS: + if (is_alias64(insn, AARCH64_INS_ALIAS_CMP)) { op->type = RZ_ANALYSIS_OP_TYPE_CMP; } else { op->type = RZ_ANALYSIS_OP_TYPE_SUB; @@ -1031,8 +1039,8 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->val = IMM64(1); } break; - case CS_AARCH64(_INS_ANDS): - if (is_alias64(insn, AArch64_INS_ALIAS_TST)) { + case ARM64_INS_ANDS: + if (is_alias64(insn, AARCH64_INS_ALIAS_TST)) { op->type = RZ_ANALYSIS_OP_TYPE_CMP; } else { op->type = RZ_ANALYSIS_OP_TYPE_AND; @@ -1041,88 +1049,88 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->val = IMM64(1); } break; - case CS_AARCH64(_INS_ADDG): + case ARM64_INS_ADDG: op->type = RZ_ANALYSIS_OP_TYPE_ADD; if (ISIMM64(1)) { op->val = IMM64(1); } break; - case CS_AARCH64(_INS_IRG): + case ARM64_INS_IRG: op->type = RZ_ANALYSIS_OP_TYPE_MOV; break; - case CS_AARCH64(_INS_SUBG): + case ARM64_INS_SUBG: op->type = RZ_ANALYSIS_OP_TYPE_SUB; if (ISIMM64(1)) { op->val = IMM64(1); } break; #endif - case CS_AARCH64(_INS_ROR): + case ARM64_INS_ROR: op->cycles = 1; op->type = RZ_ANALYSIS_OP_TYPE_ROR; break; - case CS_AARCH64(_INS_AND): + case ARM64_INS_AND: op->type = RZ_ANALYSIS_OP_TYPE_AND; break; - case CS_AARCH64(_INS_ORR): - case CS_AARCH64(_INS_ORN): + case ARM64_INS_ORR: + case ARM64_INS_ORN: op->type = RZ_ANALYSIS_OP_TYPE_OR; if (ISIMM64(2)) { op->val = IMM64(2); } break; - case CS_AARCH64(_INS_EOR): - case CS_AARCH64(_INS_EON): + case ARM64_INS_EOR: + case ARM64_INS_EON: op->type = RZ_ANALYSIS_OP_TYPE_XOR; break; - case CS_AARCH64(_INS_STRB): - case CS_AARCH64(_INS_STURB): - case CS_AARCH64(_INS_STUR): - case CS_AARCH64(_INS_STR): - case CS_AARCH64(_INS_STP): - case CS_AARCH64(_INS_STNP): - case CS_AARCH64(_INS_STXR): - case CS_AARCH64(_INS_STXRH): - case CS_AARCH64(_INS_STLXR): - case CS_AARCH64(_INS_STLXRH): - case CS_AARCH64(_INS_STXRB): + case ARM64_INS_STRB: + case ARM64_INS_STURB: + case ARM64_INS_STUR: + case ARM64_INS_STR: + case ARM64_INS_STP: + case ARM64_INS_STNP: + case ARM64_INS_STXR: + case ARM64_INS_STXRH: + case ARM64_INS_STLXR: + case ARM64_INS_STLXRH: + case ARM64_INS_STXRB: op->type = RZ_ANALYSIS_OP_TYPE_STORE; - if (ISPREINDEX64() && REGBASE64(2) == CS_AARCH64(_REG_SP)) { + if (ISPREINDEX64() && REGBASE64(2) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -MEMDISP64(2); - } else if (ISPOSTINDEX64() && REGID64(2) == CS_AARCH64(_REG_SP)) { + } else if (ISPOSTINDEX64() && REGID64(2) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -IMM64(3); - } else if (ISPREINDEX64() && REGBASE64(1) == CS_AARCH64(_REG_SP)) { + } else if (ISPREINDEX64() && REGBASE64(1) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -MEMDISP64(1); - } else if (ISPOSTINDEX64() && REGID64(1) == CS_AARCH64(_REG_SP)) { + } else if (ISPOSTINDEX64() && REGID64(1) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -IMM64(2); } break; - case CS_AARCH64(_INS_LDUR): - case CS_AARCH64(_INS_LDURB): - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDRSB): - case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDR): - case CS_AARCH64(_INS_LDURSW): - case CS_AARCH64(_INS_LDP): - case CS_AARCH64(_INS_LDNP): - case CS_AARCH64(_INS_LDPSW): - case CS_AARCH64(_INS_LDRH): - case CS_AARCH64(_INS_LDRB): - if (ISPREINDEX64() && REGBASE64(2) == CS_AARCH64(_REG_SP)) { + case ARM64_INS_LDUR: + case ARM64_INS_LDURB: + case ARM64_INS_LDRSW: + case ARM64_INS_LDRSB: + case ARM64_INS_LDRSH: + case ARM64_INS_LDR: + case ARM64_INS_LDURSW: + case ARM64_INS_LDP: + case ARM64_INS_LDNP: + case ARM64_INS_LDPSW: + case ARM64_INS_LDRH: + case ARM64_INS_LDRB: + if (ISPREINDEX64() && REGBASE64(2) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -MEMDISP64(2); - } else if (ISPOSTINDEX64() && REGID64(2) == CS_AARCH64(_REG_SP)) { + } else if (ISPOSTINDEX64() && REGID64(2) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -IMM64(3); - } else if (ISPREINDEX64() && REGBASE64(1) == CS_AARCH64(_REG_SP)) { + } else if (ISPREINDEX64() && REGBASE64(1) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; op->stackptr = -MEMDISP64(1); - } else if (ISPOSTINDEX64() && REGID64(1) == CS_AARCH64(_REG_SP)) { + } else if (ISPOSTINDEX64() && REGID64(1) == ARM64_REG_SP) { op->stackop = RZ_ANALYSIS_STACK_INC; #if CS_NEXT_VERSION >= 6 op->stackptr = -MEMDISP64(1); @@ -1140,14 +1148,14 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { op->type = RZ_ANALYSIS_OP_TYPE_LOAD; } switch (insn->id) { - case CS_AARCH64(_INS_LDPSW): - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDRSH): - case CS_AARCH64(_INS_LDRSB): + case ARM64_INS_LDPSW: + case ARM64_INS_LDRSW: + case ARM64_INS_LDRSH: + case ARM64_INS_LDRSB: op->sign = true; break; } - if (REGBASE64(1) == CS_AARCH64(_REG_X29)) { + if (REGBASE64(1) == ARM64_REG_X29) { op->stackop = RZ_ANALYSIS_STACK_GET; op->stackptr = 0; op->ptr = MEMDISP64(1); @@ -1164,73 +1172,73 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } break; #if CS_API_MAJOR > 4 - case CS_AARCH64(_INS_BLRAA): - case CS_AARCH64(_INS_BLRAAZ): - case CS_AARCH64(_INS_BLRAB): - case CS_AARCH64(_INS_BLRABZ): + case ARM64_INS_BLRAA: + case ARM64_INS_BLRAAZ: + case ARM64_INS_BLRAB: + case ARM64_INS_BLRABZ: op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; op->type = RZ_ANALYSIS_OP_TYPE_RCALL; break; - case CS_AARCH64(_INS_BRAA): - case CS_AARCH64(_INS_BRAAZ): - case CS_AARCH64(_INS_BRAB): - case CS_AARCH64(_INS_BRABZ): + case ARM64_INS_BRAA: + case ARM64_INS_BRAAZ: + case ARM64_INS_BRAB: + case ARM64_INS_BRABZ: op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; op->type = RZ_ANALYSIS_OP_TYPE_RJMP; break; - case CS_AARCH64(_INS_LDRAA): - case CS_AARCH64(_INS_LDRAB): + case ARM64_INS_LDRAA: + case ARM64_INS_LDRAB: op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; op->type = RZ_ANALYSIS_OP_TYPE_LOAD; break; - case CS_AARCH64(_INS_RETAA): - case CS_AARCH64(_INS_RETAB): - case CS_AARCH64(_INS_ERETAA): - case CS_AARCH64(_INS_ERETAB): + case ARM64_INS_RETAA: + case ARM64_INS_RETAB: + case ARM64_INS_ERETAA: + case ARM64_INS_ERETAB: op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY; op->type = RZ_ANALYSIS_OP_TYPE_RET; break; #endif - case CS_AARCH64(_INS_ERET): + case ARM64_INS_ERET: op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; op->type = RZ_ANALYSIS_OP_TYPE_RET; break; - case CS_AARCH64(_INS_RET): + case ARM64_INS_RET: op->type = RZ_ANALYSIS_OP_TYPE_RET; break; - case CS_AARCH64(_INS_BL): // bl 0x89480 + case ARM64_INS_BL: // bl 0x89480 op->type = RZ_ANALYSIS_OP_TYPE_CALL; op->jump = IMM64(0); op->fail = addr + 4; break; - case CS_AARCH64(_INS_BLR): // blr x0 + case ARM64_INS_BLR: // blr x0 op->type = RZ_ANALYSIS_OP_TYPE_RCALL; op->reg = cs_reg_name(handle, REGID64(0)); op->fail = addr + 4; // op->jump = IMM64(0); break; - case CS_AARCH64(_INS_CBZ): - case CS_AARCH64(_INS_CBNZ): + case ARM64_INS_CBZ: + case ARM64_INS_CBNZ: op->type = RZ_ANALYSIS_OP_TYPE_CJMP; op->jump = IMM64(1); op->fail = addr + op->size; break; - case CS_AARCH64(_INS_TBZ): - case CS_AARCH64(_INS_TBNZ): + case ARM64_INS_TBZ: + case ARM64_INS_TBNZ: op->type = RZ_ANALYSIS_OP_TYPE_CJMP; op->jump = IMM64(2); op->fail = addr + op->size; break; - case CS_AARCH64(_INS_BR): + case ARM64_INS_BR: op->type = RZ_ANALYSIS_OP_TYPE_RJMP; op->reg = cs_reg_name(handle, REGID64(0)); op->eob = true; break; - case CS_AARCH64(_INS_B): + case ARM64_INS_B: // BX LR == RET - if (insn->detail->CS_aarch64_.operands[0].reg == CS_AARCH64(_REG_LR)) { + if (insn->detail->arm64.operands[0].reg == ARM64_REG_LR) { op->type = RZ_ANALYSIS_OP_TYPE_RET; - } else if (cc_holds_cond(insn->detail->CS_aarch64_.cc)) { + } else if (cc_holds_cond(insn->detail->arm64.cc)) { op->type = RZ_ANALYSIS_OP_TYPE_CJMP; op->jump = IMM64(0); op->fail = addr + op->size; @@ -1240,7 +1248,7 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } break; #if CS_NEXT_VERSION >= 6 - case CS_AARCH64(_INS_UDF): + case ARM64_INS_UDF: op->type = RZ_ANALYSIS_OP_TYPE_ILL; break; #endif @@ -1850,8 +1858,8 @@ static int parse_reg_name(RzReg *reg, RzRegItem **reg_base, RzRegItem **reg_delt return 0; } -static bool is_valid64(CS_aarch64_reg() reg) { - return reg != CS_AARCH64(_REG_INVALID); +static bool is_valid64(arm64_reg reg) { + return reg != ARM64_REG_INVALID; } static char *reg_list[] = { @@ -1865,12 +1873,12 @@ static char *reg_list[] = { }; static int parse_reg64_name(RzReg *reg, RzRegItem **reg_base, RzRegItem **reg_delta, csh handle, cs_insn *insn, int reg_num) { - CS_aarch64_op() armop = INSOP64(reg_num); + cs_arm64_op armop = INSOP64(reg_num); switch (armop.type) { - case CS_AARCH64(_OP_REG): + case ARM64_OP_REG: *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.reg), RZ_REG_TYPE_ANY); break; - case CS_AARCH64(_OP_MEM): + case ARM64_OP_MEM: if (is_valid64(armop.mem.base) && is_valid64(armop.mem.index)) { *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.base), RZ_REG_TYPE_ANY); *reg_delta = rz_reg_get(reg, cs_reg_name(handle, armop.mem.index), RZ_REG_TYPE_ANY); @@ -1915,7 +1923,7 @@ static void set_opdir(RzAnalysisOp *op) { static void set_src_dst(RzAnalysisValue *val, RzReg *reg, csh *handle, cs_insn *insn, int x, int bits) { cs_arm_op armop = INSOP(x); - CS_aarch64_op() arm64op = INSOP64(x); + cs_arm64_op arm64op = INSOP64(x); if (bits == 64) { parse_reg64_name(reg, &val->reg, &val->regdelta, *handle, insn, x); } else { @@ -1923,14 +1931,14 @@ static void set_src_dst(RzAnalysisValue *val, RzReg *reg, csh *handle, cs_insn * } if (bits == 64) { switch (arm64op.type) { - case CS_AARCH64(_OP_REG): + case ARM64_OP_REG: val->type = RZ_ANALYSIS_VAL_REG; break; - case CS_AARCH64(_OP_MEM): + case ARM64_OP_MEM: val->type = RZ_ANALYSIS_VAL_MEM; val->delta = arm64op.mem.disp; break; - case CS_AARCH64(_OP_IMM): + case ARM64_OP_IMM: val->type = RZ_ANALYSIS_VAL_IMM; val->imm = arm64op.imm; break; @@ -1944,7 +1952,7 @@ static void set_src_dst(RzAnalysisValue *val, RzReg *reg, csh *handle, cs_insn * break; case ARM_OP_MEM: val->type = RZ_ANALYSIS_VAL_MEM; - val->mul = armop.mem.scale << armop.mem.lshift; + val->mul = armop.mem.scale << armop.shift.value; #if CS_NEXT_VERSION >= 6 val->delta = MEMDISP(x); #else @@ -1971,7 +1979,7 @@ static void create_src_dst(RzAnalysisOp *op) { static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_insn *insn, int bits) { create_src_dst(op); int i, j; - int count = bits == 64 ? insn->detail->CS_aarch64_.op_count : insn->detail->arm.op_count; + int count = bits == 64 ? insn->detail->arm64.op_count : insn->detail->arm.op_count; switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) { case RZ_ANALYSIS_OP_TYPE_MOV: case RZ_ANALYSIS_OP_TYPE_CMP: @@ -1995,7 +2003,7 @@ static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_in case RZ_ANALYSIS_OP_TYPE_CAST: for (i = 1; i < count; i++) { if (bits == 64) { - CS_aarch64_op() arm64op = INSOP64(i); + cs_arm64_op arm64op = INSOP64(i); if (arm64op.access == CS_AC_WRITE) { continue; } @@ -2016,8 +2024,8 @@ static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_in case RZ_ANALYSIS_OP_TYPE_STORE: if (count > 2) { if (bits == 64) { - CS_aarch64_op() arm64op = INSOP64(count - 1); - if (arm64op.type == CS_AARCH64(_OP_IMM)) { + cs_arm64_op arm64op = INSOP64(count - 1); + if (arm64op.type == ARM64_OP_IMM) { count--; } } else { @@ -2084,7 +2092,7 @@ static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *bu op->size = (a->bits == 16) ? 2 : 4; op->addr = addr; if (ctx->handle == 0) { - ret = (a->bits == 64) ? cs_open(CS_AARCH64pre(CS_ARCH_), mode, &ctx->handle) : cs_open(CS_ARCH_ARM, mode, &ctx->handle); + ret = (a->bits == 64) ? cs_open(CS_ARCH_ARM64, mode, &ctx->handle) : cs_open(CS_ARCH_ARM, mode, &ctx->handle); cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_ON); #if CS_NEXT_VERSION >= 6 cs_option(ctx->handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS); @@ -2602,47 +2610,47 @@ static ut8 *analysis_mask(RzAnalysis *analysis, int size, const ut8 *data, ut64 case 4: if (analysis->bits == 64) { switch (op->id) { - case CS_AARCH64(_INS_LDP): - case CS_AARCH64(_INS_LDXP): - case CS_AARCH64(_INS_LDXR): - case CS_AARCH64(_INS_LDXRB): - case CS_AARCH64(_INS_LDXRH): - case CS_AARCH64(_INS_LDPSW): - case CS_AARCH64(_INS_LDNP): - case CS_AARCH64(_INS_LDTR): - case CS_AARCH64(_INS_LDTRB): - case CS_AARCH64(_INS_LDTRH): - case CS_AARCH64(_INS_LDTRSB): - case CS_AARCH64(_INS_LDTRSH): - case CS_AARCH64(_INS_LDTRSW): - case CS_AARCH64(_INS_LDUR): - case CS_AARCH64(_INS_LDURB): - case CS_AARCH64(_INS_LDURH): - case CS_AARCH64(_INS_LDURSB): - case CS_AARCH64(_INS_LDURSH): - case CS_AARCH64(_INS_LDURSW): - case CS_AARCH64(_INS_STP): - case CS_AARCH64(_INS_STNP): - case CS_AARCH64(_INS_STXR): - case CS_AARCH64(_INS_STXRB): - case CS_AARCH64(_INS_STXRH): + case ARM64_INS_LDP: + case ARM64_INS_LDXP: + case ARM64_INS_LDXR: + case ARM64_INS_LDXRB: + case ARM64_INS_LDXRH: + case ARM64_INS_LDPSW: + case ARM64_INS_LDNP: + case ARM64_INS_LDTR: + case ARM64_INS_LDTRB: + case ARM64_INS_LDTRH: + case ARM64_INS_LDTRSB: + case ARM64_INS_LDTRSH: + case ARM64_INS_LDTRSW: + case ARM64_INS_LDUR: + case ARM64_INS_LDURB: + case ARM64_INS_LDURH: + case ARM64_INS_LDURSB: + case ARM64_INS_LDURSH: + case ARM64_INS_LDURSW: + case ARM64_INS_STP: + case ARM64_INS_STNP: + case ARM64_INS_STXR: + case ARM64_INS_STXRB: + case ARM64_INS_STXRH: rz_write_ble(ret + idx, 0xffffffff, analysis->big_endian, 32); break; - case CS_AARCH64(_INS_STRB): - case CS_AARCH64(_INS_STURB): - case CS_AARCH64(_INS_STURH): - case CS_AARCH64(_INS_STUR): - case CS_AARCH64(_INS_STR): - case CS_AARCH64(_INS_STTR): - case CS_AARCH64(_INS_STTRB): - case CS_AARCH64(_INS_STRH): - case CS_AARCH64(_INS_STTRH): - case CS_AARCH64(_INS_LDR): - case CS_AARCH64(_INS_LDRB): - case CS_AARCH64(_INS_LDRH): - case CS_AARCH64(_INS_LDRSB): - case CS_AARCH64(_INS_LDRSW): - case CS_AARCH64(_INS_LDRSH): { + case ARM64_INS_STRB: + case ARM64_INS_STURB: + case ARM64_INS_STURH: + case ARM64_INS_STUR: + case ARM64_INS_STR: + case ARM64_INS_STTR: + case ARM64_INS_STTRB: + case ARM64_INS_STRH: + case ARM64_INS_STTRH: + case ARM64_INS_LDR: + case ARM64_INS_LDRB: + case ARM64_INS_LDRH: + case ARM64_INS_LDRSB: + case ARM64_INS_LDRSW: + case ARM64_INS_LDRSH: { bool is_literal = (opcode & 0x38000000) == 0x18000000; if (is_literal) { rz_write_ble(ret + idx, 0xff000000, analysis->big_endian, 32); @@ -2651,22 +2659,22 @@ static ut8 *analysis_mask(RzAnalysis *analysis, int size, const ut8 *data, ut64 } break; } - case CS_AARCH64(_INS_B): - case CS_AARCH64(_INS_BL): - case CS_AARCH64(_INS_CBZ): - case CS_AARCH64(_INS_CBNZ): + case ARM64_INS_B: + case ARM64_INS_BL: + case ARM64_INS_CBZ: + case ARM64_INS_CBNZ: if (op->type == RZ_ANALYSIS_OP_TYPE_CJMP) { rz_write_ble(ret + idx, 0xff00001f, analysis->big_endian, 32); } else { rz_write_ble(ret + idx, 0xfc000000, analysis->big_endian, 32); } break; - case CS_AARCH64(_INS_TBZ): - case CS_AARCH64(_INS_TBNZ): + case ARM64_INS_TBZ: + case ARM64_INS_TBNZ: rz_write_ble(ret + idx, 0xfff8001f, analysis->big_endian, 32); break; - case CS_AARCH64(_INS_ADR): - case CS_AARCH64(_INS_ADRP): + case ARM64_INS_ADR: + case ARM64_INS_ADRP: rz_write_ble(ret + idx, 0xff00001f, analysis->big_endian, 32); break; default: diff --git a/librz/arch/p/analysis/analysis_mips_cs.c b/librz/arch/p/analysis/analysis_mips_cs.c index af524566c6b..bf230eb28dc 100644 --- a/librz/arch/p/analysis/analysis_mips_cs.c +++ b/librz/arch/p/analysis/analysis_mips_cs.c @@ -246,9 +246,11 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 ARG(0), ARG(1)); break; case MIPS_INS_CMP: +#if CS_NEXT_VERSION < 6 case MIPS_INS_CMPU: case MIPS_INS_CMPGU: case MIPS_INS_CMPGDU: +#endif case MIPS_INS_CMPI: rz_strbuf_appendf(&op->esil, "%s,%s,==", ARG(1), ARG(0)); break; @@ -257,6 +259,7 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 "%s,%s,>>,31,%s,>>,?{,32,%s,32,-,0xffffffff,<<,0xffffffff,&,<<,}{,0,},|,%s,=", ARG(2), ARG(1), ARG(1), ARG(2), ARG(0)); break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_SHRAV: case MIPS_INS_SHRAV_R: case MIPS_INS_SHRA: @@ -272,6 +275,7 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case MIPS_INS_SRL: rz_strbuf_appendf(&op->esil, "%s,%s,>>,%s,=", ARG(2), ARG(1), ARG(0)); break; +#endif case MIPS_INS_SLLV: case MIPS_INS_SLL: rz_strbuf_appendf(&op->esil, "%s,%s,<<,%s,=", ARG(2), ARG(1), ARG(0)); @@ -320,7 +324,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 rz_strbuf_appendf(&op->esil, ES_TRAP_DS() "%s,%s,==,$z,?{," ES_J("%s") ",}", ARG(0), ARG(1), ARG(2)); break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_BZ: +#endif case MIPS_INS_BEQZ: case MIPS_INS_BEQZC: rz_strbuf_appendf(&op->esil, ES_TRAP_DS() "%s,0,==,$z,?{," ES_J("%s") ",}", @@ -383,7 +389,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 case MIPS_INS_BTNEZ: rz_strbuf_appendf(&op->esil, ES_TRAP_DS() "0,t,==,$z,!,?{," ES_J("%s") ",}", ARG(0)); break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_MOV: +#endif case MIPS_INS_MOVE: PROTECT_ZERO() { rz_strbuf_appendf(&op->esil, "%s,%s,=", ARG(1), REG(0)); @@ -402,7 +410,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 ARG(2), ARG(1), REG(0)); } break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_FSUB: +#endif case MIPS_INS_SUB: case MIPS_INS_SUBU: case MIPS_INS_DSUB: @@ -413,7 +423,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 } break; case MIPS_INS_NEG: +#if CS_NEXT_VERSION < 6 case MIPS_INS_NEGU: +#endif rz_strbuf_appendf(&op->esil, "%s,0,-,%s,=,", ARG(1), ARG(0)); break; @@ -452,7 +464,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 } } break; case MIPS_INS_LI: +#if CS_NEXT_VERSION < 6 case MIPS_INS_LDI: +#endif rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,=", (ut64)IMM(1), ARG(0)); break; case MIPS_INS_LUI: @@ -859,11 +873,20 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u case MIPS_INS_JALR: op->type = RZ_ANALYSIS_OP_TYPE_UCALL; op->delay = 1; +#if CS_NEXT_VERSION < 6 if (REGID(0) == MIPS_REG_25) { op->jump = t9_pre; t9_pre = UT64_MAX; op->type = RZ_ANALYSIS_OP_TYPE_RCALL; } +#else + if (REGID(0) == MIPS_REG_T9 || + REGID(0) == MIPS_REG_T9_64) { + op->jump = t9_pre; + t9_pre = UT64_MAX; + op->type = RZ_ANALYSIS_OP_TYPE_RCALL; + } +#endif break; case MIPS_INS_JAL: case MIPS_INS_JALS: @@ -927,26 +950,30 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u op->stackptr = -IMM(2); } break; - case MIPS_INS_SUB: +#if CS_NEXT_VERSION < 6 case MIPS_INS_SUBV: case MIPS_INS_SUBVI: - case MIPS_INS_DSUBU: case MIPS_INS_FSUB: case MIPS_INS_FMSUB: - case MIPS_INS_SUBU: - case MIPS_INS_DSUB: case MIPS_INS_SUBS_S: case MIPS_INS_SUBS_U: case MIPS_INS_SUBUH: case MIPS_INS_SUBUH_R: +#endif + case MIPS_INS_SUB: + case MIPS_INS_DSUBU: + case MIPS_INS_SUBU: + case MIPS_INS_DSUB: SET_VAL(op, 2); op->sign = insn->id == MIPS_INS_SUB; op->type = RZ_ANALYSIS_OP_TYPE_SUB; break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_MULV: - case MIPS_INS_MULT: case MIPS_INS_MULSA: case MIPS_INS_FMUL: +#endif + case MIPS_INS_MULT: case MIPS_INS_MUL: case MIPS_INS_DMULT: case MIPS_INS_DMULTU: @@ -977,28 +1004,34 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u case MIPS_INS_DIVU: case MIPS_INS_DDIV: case MIPS_INS_DDIVU: - case MIPS_INS_FDIV: case MIPS_INS_DIV_S: +#if CS_NEXT_VERSION < 6 + case MIPS_INS_FDIV: case MIPS_INS_DIV_U: +#endif op->type = RZ_ANALYSIS_OP_TYPE_DIV; break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_CMPGDU: case MIPS_INS_CMPGU: case MIPS_INS_CMPU: +#endif case MIPS_INS_CMPI: op->type = RZ_ANALYSIS_OP_TYPE_CMP; break; +#if CS_NEXT_VERSION < 6 + case MIPS_INS_BZ: + case MIPS_INS_BNZ: + case MIPS_INS_BNEG: + case MIPS_INS_BNEGI: +#endif case MIPS_INS_J: case MIPS_INS_B: - case MIPS_INS_BZ: case MIPS_INS_BEQ: - case MIPS_INS_BNZ: case MIPS_INS_BNE: case MIPS_INS_BNEL: case MIPS_INS_BEQL: case MIPS_INS_BEQZ: - case MIPS_INS_BNEG: - case MIPS_INS_BNEGI: case MIPS_INS_BNEZ: case MIPS_INS_BTEQZ: case MIPS_INS_BTNEZ: @@ -1053,10 +1086,19 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u op->type = RZ_ANALYSIS_OP_TYPE_RET; t9_pre = UT64_MAX; } +#if CS_NEXT_VERSION < 6 if (REGID(0) == MIPS_REG_25) { op->jump = t9_pre; t9_pre = UT64_MAX; } +#else + if (REGID(0) == MIPS_REG_T9 || + REGID(0) == MIPS_REG_T9_64) { + op->jump = t9_pre; + t9_pre = UT64_MAX; + op->type = RZ_ANALYSIS_OP_TYPE_RCALL; + } +#endif break; case MIPS_INS_SLT: @@ -1067,6 +1109,7 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u case MIPS_INS_SLTIU: SET_VAL(op, 2); break; +#if CS_NEXT_VERSION < 6 case MIPS_INS_SHRAV: case MIPS_INS_SHRAV_R: case MIPS_INS_SHRA: @@ -1076,8 +1119,9 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u SET_VAL(op, 2); break; case MIPS_INS_SHRL: - case MIPS_INS_SRLV: case MIPS_INS_SRL: +#endif + case MIPS_INS_SRLV: op->type = RZ_ANALYSIS_OP_TYPE_SHR; SET_VAL(op, 2); break; diff --git a/librz/arch/p/analysis/analysis_sysz.c b/librz/arch/p/analysis/analysis_sysz.c index 855ed57a627..4825c561f81 100644 --- a/librz/arch/p/analysis/analysis_sysz.c +++ b/librz/arch/p/analysis/analysis_sysz.c @@ -3,6 +3,9 @@ #include #include +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_SYSTEMZ_COMPAT_HEADER #include #include // instruction set: http://www.tachyonsoft.com/inst390m.htm @@ -96,35 +99,37 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf case SYSZ_INS_BRCTG: op->type = RZ_ANALYSIS_OP_TYPE_CJMP; break; - case SYSZ_INS_JE: +#if CS_NEXT_VERSION < 6 case SYSZ_INS_JGE: - case SYSZ_INS_JHE: case SYSZ_INS_JGHE: - case SYSZ_INS_JH: case SYSZ_INS_JGH: - case SYSZ_INS_JLE: case SYSZ_INS_JGLE: - case SYSZ_INS_JLH: case SYSZ_INS_JGLH: - case SYSZ_INS_JL: case SYSZ_INS_JGL: - case SYSZ_INS_JNE: case SYSZ_INS_JGNE: - case SYSZ_INS_JNHE: case SYSZ_INS_JGNHE: - case SYSZ_INS_JNH: case SYSZ_INS_JGNH: - case SYSZ_INS_JNLE: case SYSZ_INS_JGNLE: - case SYSZ_INS_JNLH: case SYSZ_INS_JGNLH: - case SYSZ_INS_JNL: case SYSZ_INS_JGNL: - case SYSZ_INS_JNO: case SYSZ_INS_JGNO: - case SYSZ_INS_JO: case SYSZ_INS_JGO: case SYSZ_INS_JG: +#endif + case SYSZ_INS_JNE: + case SYSZ_INS_JNHE: + case SYSZ_INS_JNH: + case SYSZ_INS_JNL: + case SYSZ_INS_JE: + case SYSZ_INS_JHE: + case SYSZ_INS_JH: + case SYSZ_INS_JLE: + case SYSZ_INS_JLH: + case SYSZ_INS_JL: + case SYSZ_INS_JNLE: + case SYSZ_INS_JNLH: + case SYSZ_INS_JNO: + case SYSZ_INS_JO: op->type = RZ_ANALYSIS_OP_TYPE_CJMP; op->jump = INSOP(0).imm; op->fail = addr + op->size; diff --git a/librz/arch/p/asm/asm_arm_cs.c b/librz/arch/p/asm/asm_arm_cs.c index dc82025d1e4..02c577c350e 100644 --- a/librz/arch/p/asm/asm_arm_cs.c +++ b/librz/arch/p/asm/asm_arm_cs.c @@ -4,6 +4,9 @@ #include #include #include +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_AARCH64_COMPAT_HEADER #include #include "arm/asm-arm.h" #include "arm/arm_it.h" @@ -95,7 +98,7 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { rz_strbuf_set(&op->buf_asm, ""); } if (!ctx->cd || mode != ctx->omode) { - ret = (a->bits == 64) ? cs_open(CS_AARCH64pre(CS_ARCH_), mode, &ctx->cd) : cs_open(CS_ARCH_ARM, mode, &ctx->cd); + ret = (a->bits == 64) ? cs_open(CS_ARCH_ARM64, mode, &ctx->cd) : cs_open(CS_ARCH_ARM, mode, &ctx->cd); if (ret) { ret = -1; goto beach; diff --git a/librz/arch/p/asm/asm_sysz.c b/librz/arch/p/asm/asm_sysz.c index 2d09897ec95..d68e70efec3 100644 --- a/librz/arch/p/asm/asm_sysz.c +++ b/librz/arch/p/asm/asm_sysz.c @@ -7,6 +7,7 @@ #include #include "cs_helper.h" +#include CAPSTONE_DEFINE_PLUGIN_FUNCTIONS(sysz); @@ -25,6 +26,7 @@ static int sysz_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { if (!ctx->handle) { ret = cs_open(CS_ARCH_SYSZ, mode, &ctx->handle); if (ret) { + RZ_LOG_ERROR("Failed to initialize Capstone: '%s'\n", cs_strerror(ret)); return -1; } ctx->omode = mode; diff --git a/librz/arch/p/asm/cs_helper.h b/librz/arch/p/asm/cs_helper.h index d001f15c316..5666a67edd7 100644 --- a/librz/arch/p/asm/cs_helper.h +++ b/librz/arch/p/asm/cs_helper.h @@ -3,6 +3,9 @@ // SPDX-License-Identifier: LGPL-3.0-only #include +#pragma GCC diagnostic ignored "-Wenum-compare" +#pragma GCC diagnostic ignored "-Wenum-conversion" +#define CAPSTONE_SYSTEMZ_COMPAT_HEADER #include typedef struct { diff --git a/meson_options.txt b/meson_options.txt index b774ad26a4b..e46e8a12e5d 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -21,7 +21,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).') option('use_sys_capstone', type: 'feature', value: 'disabled') -option('use_capstone_version', type: 'combo', choices: ['v4', 'v5', 'next'], value: 'next', description: 'Specify which version of capstone to use') +option('use_capstone_version', type: 'combo', choices: ['v4', 'v5', 'v6', 'next'], value: 'next', description: 'Specify which version of capstone to use') option('use_sys_magic', type: 'feature', value: 'disabled') option('use_sys_libzip', type: 'feature', value: 'disabled') option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip') diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap index eaf386f5954..227de334888 100644 --- a/subprojects/capstone-next.wrap +++ b/subprojects/capstone-next.wrap @@ -1,6 +1,6 @@ [wrap-git] url = https://github.com/capstone-engine/capstone.git -revision = eb4fc2d7612db10379adf7aeb287a7923dcc0fc7 +revision = 32519c01efbcfb1bf29bdfc3ad0ad574aea369d9 directory = capstone-next patch_directory = capstone-next depth = 1 diff --git a/subprojects/capstone-v6.wrap b/subprojects/capstone-v6.wrap new file mode 100644 index 00000000000..8ce03a97cd5 --- /dev/null +++ b/subprojects/capstone-v6.wrap @@ -0,0 +1,6 @@ +[wrap-git] +url = https://github.com/capstone-engine/capstone.git +revision = v6 +patch_directory = capstone-6.0.0-alpha1 +directory = capstone-6.0.0 +depth = 1 diff --git a/subprojects/packagefiles/capstone-auto-sync-aarch64/meson.build b/subprojects/packagefiles/capstone-6.0.0-alpha1/meson.build similarity index 83% rename from subprojects/packagefiles/capstone-auto-sync-aarch64/meson.build rename to subprojects/packagefiles/capstone-6.0.0-alpha1/meson.build index 64318608e4e..d92f1ab6f3a 100644 --- a/subprojects/packagefiles/capstone-auto-sync-aarch64/meson.build +++ b/subprojects/packagefiles/capstone-6.0.0-alpha1/meson.build @@ -1,6 +1,10 @@ -project('capstone', 'c', version: '5.0.1', meson_version: '>=0.55.0') +project('capstone', 'c', version: 'next', meson_version: '>=0.55.0') cs_files = [ + 'arch/Alpha/AlphaDisassembler.c', + 'arch/Alpha/AlphaInstPrinter.c', + 'arch/Alpha/AlphaMapping.c', + 'arch/Alpha/AlphaModule.c', 'arch/AArch64/AArch64BaseInfo.c', 'arch/AArch64/AArch64Disassembler.c', 'arch/AArch64/AArch64DisassemblerExtension.c', @@ -13,6 +17,10 @@ cs_files = [ 'arch/ARM/ARMInstPrinter.c', 'arch/ARM/ARMMapping.c', 'arch/ARM/ARMModule.c', + 'arch/HPPA/HPPADisassembler.c', + 'arch/HPPA/HPPAInstPrinter.c', + 'arch/HPPA/HPPAMapping.c', + 'arch/HPPA/HPPAModule.c', 'arch/M680X/M680XDisassembler.c', 'arch/M680X/M680XInstPrinter.c', 'arch/M680X/M680XModule.c', @@ -31,11 +39,12 @@ cs_files = [ 'arch/Sparc/SparcInstPrinter.c', 'arch/Sparc/SparcMapping.c', 'arch/Sparc/SparcModule.c', - 'arch/SystemZ/SystemZDisassembler.c', 'arch/SystemZ/SystemZInstPrinter.c', + 'arch/SystemZ/SystemZModule.c', 'arch/SystemZ/SystemZMapping.c', + 'arch/SystemZ/SystemZDisassemblerExtension.c', 'arch/SystemZ/SystemZMCTargetDesc.c', - 'arch/SystemZ/SystemZModule.c', + 'arch/SystemZ/SystemZDisassembler.c', 'arch/TMS320C64x/TMS320C64xDisassembler.c', 'arch/TMS320C64x/TMS320C64xInstPrinter.c', 'arch/TMS320C64x/TMS320C64xMapping.c', @@ -72,20 +81,26 @@ libcapstone_c_args = [ '-DCAPSTONE_X86_REDUCE_NO', '-DCAPSTONE_USE_SYS_DYN_MEM', '-DCAPSTONE_DIET_NO', + '-DCAPSTONE_HAS_ALPHA', '-DCAPSTONE_HAS_ARM', '-DCAPSTONE_HAS_AARCH64', + '-DCAPSTONE_HAS_HPPA', '-DCAPSTONE_HAS_M68K', '-DCAPSTONE_HAS_M680X', '-DCAPSTONE_HAS_MIPS', '-DCAPSTONE_HAS_POWERPC', '-DCAPSTONE_HAS_SPARC', - '-DCAPSTONE_HAS_SYSZ', + '-DCAPSTONE_HAS_SYSTEMZ', '-DCAPSTONE_HAS_X86', '-DCAPSTONE_HAS_XCORE', '-DCAPSTONE_HAS_TMS320C64X', '-DCAPSTONE_HAS_TRICORE', ] +if meson.get_compiler('c').has_argument('-Wmaybe-uninitialized') + libcapstone_c_args += '-Wno-maybe-uninitialized' +endif + libcapstone = library('capstone', cs_files, c_args: libcapstone_c_args, include_directories: capstone_includes, diff --git a/subprojects/packagefiles/capstone-next/meson.build b/subprojects/packagefiles/capstone-next/meson.build index 8fbd1488a85..f22e3606a7b 100644 --- a/subprojects/packagefiles/capstone-next/meson.build +++ b/subprojects/packagefiles/capstone-next/meson.build @@ -39,6 +39,7 @@ cs_files = [ 'arch/Sparc/SparcInstPrinter.c', 'arch/Sparc/SparcMapping.c', 'arch/Sparc/SparcModule.c', + 'arch/SystemZ/SystemZDisassemblerExtension.c', 'arch/SystemZ/SystemZDisassembler.c', 'arch/SystemZ/SystemZInstPrinter.c', 'arch/SystemZ/SystemZMapping.c', @@ -89,7 +90,7 @@ libcapstone_c_args = [ '-DCAPSTONE_HAS_MIPS', '-DCAPSTONE_HAS_POWERPC', '-DCAPSTONE_HAS_SPARC', - '-DCAPSTONE_HAS_SYSZ', + '-DCAPSTONE_HAS_SYSTEMZ', '-DCAPSTONE_HAS_X86', '-DCAPSTONE_HAS_XCORE', '-DCAPSTONE_HAS_TMS320C64X', diff --git a/test/db/analysis/arm64 b/test/db/analysis/arm64 index bb53e497e7d..997e0bdf1de 100644 --- a/test/db/analysis/arm64 +++ b/test/db/analysis/arm64 @@ -108,7 +108,7 @@ pseudo: asm("irg x8, sp, x8") mnemonic: irg mask: ffffffff prefix: 0 -id: 455 +id: 495 bytes: e813c89a refptr: 0 size: 4 @@ -190,7 +190,7 @@ pseudo: asm("irg x8, sp, x8") mnemonic: irg mask: ffffffff prefix: 0 -id: 455 +id: 495 bytes: 9ac813e8 refptr: 0 size: 4 diff --git a/test/db/analysis/mips b/test/db/analysis/mips index aa679477880..fdf040f3353 100644 --- a/test/db/analysis/mips +++ b/test/db/analysis/mips @@ -12,6 +12,7 @@ RUN NAME=mozi aae functions FILE=bins/elf/mips-mozi +BROKEN=1 CMDS=< 344 sym.extract_dirs_from_files -0x00015c2c 13 396 -> 364 sym.sort_files -0x00015f6c 129 2740 -> 2472 sym.gobble_file -0x00016a20 31 748 -> 504 sym.quote_name -0x00016da0 31 420 sym.restore_default_color -0x00017b7c 3 3544 -> 56 sym.print_current_files -0x00018954 4 692 sym.usage -0x00018c08 344 8388 -> 7256 main -0x0001b334 7 136 sym.set_program_name -0x0001b3e4 16 324 -> 316 sym.version_etc_va -0x0001b528 1 48 sym.version_etc -0x0001b558 1 44 sym.xalloc_die -0x0001b59c 14 248 sym.argmatch -0x0001b694 3 88 sym.argmatch_invalid -0x0001b6ec 9 248 sym.argmatch_valid -0x0001b7e4 3 88 sym.__xargmatch_internal -0x0001ba88 1 8 sym.dirfd -0x0001bb8c 4 120 sym.error -0x0001caf4 198 2792 -> 2720 sym.internal_fnmatch -0x0001e84c 3 552 -> 76 sym.gnu_fnmatch -0x0001eb64 181 3004 sym._getopt_internal_r -0x0001f720 1 116 sym._getopt_internal -0x0001f7c4 1 44 sym.rpl_getopt_long -0x0001f8d0 10 184 sym.hard_locale -0x0001f998 1 8 sym.hash_get_n_entries -0x0001ff34 27 480 sym.hash_initialize -0x000201f0 26 324 sym.hash_free -0x00021a50 26 416 -> 396 sym.human_options -0x00022250 8 224 sym._obstack_begin -0x00022414 23 408 sym._obstack_newchunk -0x00022768 1 700 sym.quote -0x00022a24 2 56 sym.clone_quoting_options -0x00022a5c 2 24 sym.get_quoting_style -0x00022a74 2 24 sym.set_quoting_style -0x00022a8c 2 80 sym.set_char_quoting -0x00022afc 1 12 sym.quoting_options_from_style -0x00023634 15 372 sym.quotearg_n_options -0x000237a8 1 28 sym.quotearg_n -0x000237c4 1 24 sym.quotearg_n_mem -0x000237dc 1 108 sym.quotearg -0x0002396c 3 588 sym.quotearg_colon -0x000255f0 3 56 sym.xmalloc -0x00025720 1 32 sym.xmemdup -0x00025740 1 24 sym.xstrdup -0x00025758 14 436 sym.xstrtol_fatal -0x00025948 53 796 sym.xstrtoul -0x0003f98c 2 56 sym.imp.atexit -0x0003f998 1 8 sym.imp.exit -0x0003f9d4 1 8 sym.imp.fputs -0x0003f9e0 1 8 sym.imp.printf -0x0003f9ec 1 8 sym.imp.__flsbuf -0x0003f9f8 1 8 sym.imp.free -0x0003fa04 1 8 sym.imp.strncmp -0x0003fa28 1 8 sym.imp.strcmp -0x0003fa40 1 8 sym.imp..udiv -0x0003fa4c 1 8 sym.imp..umul -0x0003fa64 1 8 sym.imp.__assert_c99 -0x0003fa70 1 8 sym.imp.strlen -0x0003faa0 1 8 sym.imp.stat64 -0x0003fb00 1 8 sym.imp.fwrite -0x0003fb0c 1 8 sym.imp.memcpy -0x0003fb18 1 8 sym.imp.fflush -0x0003fb30 1 8 sym.imp.raise -0x0003fb3c 1 8 sym.imp.signal -0x0003fb60 1 8 sym.imp.abort -0x0003fb6c 1 8 sym.imp.fprintf -0x0003fb78 1 8 sym.imp.setlocale -0x0003fb84 1 8 sym.imp.getenv -0x0003fb90 1 8 sym.imp.ioctl -0x0003fb9c 1 8 sym.imp.opendir -0x0003fba8 1 8 sym.imp.fstat64 -0x0003fbb4 1 8 sym.imp.readdir64 -0x0003fbc0 1 8 sym.imp.closedir -0x0003fbcc 1 8 sym.imp.sigismember -0x0003fbd8 1 8 sym.imp.isatty -0x0003fbe4 1 8 sym.imp.strchr -0x0003fbf0 1 8 sym.imp.tcgetpgrp -0x0003fbfc 1 8 sym.imp.sigemptyset -0x0003fc08 1 8 sym.imp.sigaction -0x0003fc14 1 8 sym.imp.sigaddset -0x0003fc20 1 8 sym.imp.malloc -0x0003fc2c 1 8 sym.imp.acl_trivial +0x00012d9c 1 8 root.00012d9c +0x00020110 17 224 root.00020110 +0x0002b180 1 8 root.0002b180 +0x0002b538 1 8 root.0002b538 +0x0002b938 1 8 root.0002b938 +0x0002bca4 1 8 root.0002bca4 +0x0002c05c 1 8 root.0002c05c +0x0002c880 1 16 root.0002c880 +0x0003f9b0 1 8 root.0003f9b0 +0x0003f9bc 1 8 root.0003f9bc +0x0003f9c8 1 8 root.0003f9c8 EOF RUN @@ -584,7 +507,7 @@ EXPECT=< 24 fcn.8008a77a 0x8008a78c 1 4 fcn.8008a78c 0x8008a790 1 10 fcn.8008a790 +0xc0000000 4 28 fcn.c0000000 ;-- section..start_tc0: ;-- segment.LOAD6: / entry0(); diff --git a/test/db/asm/arm_64 b/test/db/asm/arm_64 index 3af310cd04c..257011ca942 100644 --- a/test/db/asm/arm_64 +++ b/test/db/asm/arm_64 @@ -538,8 +538,8 @@ d "ldr x1, [x2, 0x18]!" 418c41f8 0x0 (seq (set x1 (loadw 0 64 (+ (var x2) (bv 64 d "ldr x1, [x2, -0x18]!" 418c5ef8 0x0 (seq (set x1 (loadw 0 64 (- (var x2) (bv 64 0x18)))) (set x2 (- (var x2) (bv 64 0x18)))) d "ldr x1, [x2], 0x18" 418441f8 0x0 (seq (set x1 (loadw 0 64 (var x2))) (set x2 (+ (var x2) (bv 64 0x18)))) d "ldr x1, [x2], -0x18" 41845ef8 0x0 (seq (set x1 (loadw 0 64 (var x2))) (set x2 (- (var x2) (bv 64 0x18)))) -d "ldr x1, 0x1028" 41010058 0x1000 (set x1 (loadw 0 64 (bv 64 0x1028))) -d "ldr w1, 0x1044" 21020018 0x1000 (set x1 (cast 64 false (loadw 0 32 (bv 64 0x1044)))) +d "ldr x1, 0x1028" 41010058 0x1000 (set x1 (loadw 0 64 (+ (bv 64 0x0) (bv 64 0x1028)))) +d "ldr w1, 0x1044" 21020018 0x1000 (set x1 (cast 64 false (loadw 0 32 (+ (bv 64 0x0) (bv 64 0x1044))))) d "ldrb w1, [x2]" 41004039 0x0 (set x1 (cast 64 false (load 0 (var x2)))) d "ldrh w1, [x2]" 41004079 0x0 (set x1 (cast 64 false (loadw 0 16 (var x2)))) d "ldrb w1, [x2], 3" 41344038 0x0 (seq (set x1 (cast 64 false (load 0 (var x2)))) (set x2 (+ (var x2) (bv 64 0x3)))) diff --git a/test/db/asm/mips_64 b/test/db/asm/mips_64 index bd17db26021..3ea0576b52e 100644 --- a/test/db/asm/mips_64 +++ b/test/db/asm/mips_64 @@ -4,10 +4,10 @@ d "addiu zero, t0, -0x19" e7ff0025 0x4 d "addiu zero, t0, 0" 00000025 0x4 d "andi zero, zero, 0" 00000030 0x4 d "b 8" 00000010 0x4 -d "bc0f 8" 00000041 0x4 +dB "bc0f 8" 00000041 0x4 d "bc1f 8" 00000045 0x4 -d "bc2f 8" 00000049 0x4 -d "bc3f 8" 0000004d 0x4 +dB "bc2f 8" 00000049 0x4 +dB "bc3f 8" 0000004d 0x4 d "beq t0, s0, 0x444c" 11111011 0x4 d "beql sp, t8, 0x14008" 0050b853 0x4 d "beqz t0, 8" 00000011 0x4 @@ -24,48 +24,48 @@ d "bltzl s6, 0x118" 4400c206 0x4 d "bne t0, s0, 0x440c" 01111015 0x4 d "bnel s0, s0, -0xbff8" 00d01056 0x4 d "bnez zero, 8" 00000014 0x4 -d "cache 0, (zero)" 000000bc 0x4 +dB "cache 0, (zero)" 000000bc 0x4 d "daddi zero, zero, 0" 00000060 0x4 d "daddiu zero, zero, 0" 00000064 0x4 d "j 0" 00000008 0x4 d "jal 0" 0000000c 0x4 d "jalx 0" 00000074 0x4 d "jalx 4" 01000074 0x4 -d "lb zero, (zero)" 00000080 0x4 -d "lbu zero, (zero)" 00000090 0x4 -d "ldc1 f0, (zero)" 000000d4 0x4 -d "ldl zero, (zero)" 00000068 0x4 -d "ldr zero, (zero)" 0000006c 0x4 -d "lh zero, (zero)" 00000084 0x4 -d "lhu zero, (zero)" 00000094 0x4 -d "ll zero, (zero)" 000000c0 0x4 -d "lld zero, (zero)" 000000d0 0x4 +dB "lb zero, (zero)" 00000080 0x4 +dB "lbu zero, (zero)" 00000090 0x4 +dB "ldc1 f0, (zero)" 000000d4 0x4 +dB "ldl zero, (zero)" 00000068 0x4 +dB "ldr zero, (zero)" 0000006c 0x4 +dB "lh zero, (zero)" 00000084 0x4 +dB "lhu zero, (zero)" 00000094 0x4 +dB "ll zero, (zero)" 000000c0 0x4 +dB "lld zero, (zero)" 000000d0 0x4 d "lui zero, 0" 0000003c 0x4 -d "lw zero, (zero)" 0000008c 0x4 -d "lwc1 f0, (zero)" 000000c4 0x4 -d "lwl zero, (zero)" 00000088 0x4 -d "lwr zero, (zero)" 00000098 0x4 -d "lwu zero, (zero)" 0000009c 0x4 +dB "lw zero, (zero)" 0000008c 0x4 +dB "lwc1 f0, (zero)" 000000c4 0x4 +dB "lwl zero, (zero)" 00000088 0x4 +dB "lwr zero, (zero)" 00000098 0x4 +dB "lwu zero, (zero)" 0000009c 0x4 d "lwxc1 f0, zero(zero)" 0000004c 0x4 -d "mfc0 zero, zero, 0" 00000040 0x4 +dB "mfc0 zero, zero, 0" 00000040 0x4 d "mfc1 zero, f0" 00000044 0x4 -d "mfc2 zero, zero, 0" 00000048 0x4 +dB "mfc2 zero, zero, 0" 00000048 0x4 d "nop" 00000000 0x4 d "ori zero, t0, 0" 00000035 0x4 -d "sb zero, (zero)" 000000a0 0x4 -d "sc zero, (zero)" 000000e0 0x4 -d "scd zero, (zero)" 000000f0 0x4 -d "sd zero, (zero)" 000000fc 0x4 -d "sdc1 f0, (zero)" 000000f4 0x4 -d "sdl zero, (zero)" 000000b0 0x4 -d "sdr zero, (zero)" 000000b4 0x4 -d "sh zero, (zero)" 000000a4 0x4 +dB "sb zero, (zero)" 000000a0 0x4 +dB "sc zero, (zero)" 000000e0 0x4 +dB "scd zero, (zero)" 000000f0 0x4 +dB "sd zero, (zero)" 000000fc 0x4 +dB "sdc1 f0, (zero)" 000000f4 0x4 +dB "sdl zero, (zero)" 000000b0 0x4 +dB "sdr zero, (zero)" 000000b4 0x4 +dB "sh zero, (zero)" 000000a4 0x4 d "slti zero, zero, 0" 00000028 0x4 d "sltiu zero, zero, 0" 0000002c 0x4 -d "sw zero, (zero)" 000000ac 0x4 -d "swc1 f0, (zero)" 000000e4 0x4 -d "swl zero, (zero)" 000000a8 0x4 -d "swr zero, (zero)" 000000b8 0x4 +dB "sw zero, (zero)" 000000ac 0x4 +dB "swc1 f0, (zero)" 000000e4 0x4 +dB "swl zero, (zero)" 000000a8 0x4 +dB "swr zero, (zero)" 000000b8 0x4 d "xori zero, zero, 0" 00000038 0x4 dB "beqzl zero, 8" 00000050 0x4 dB "bnezl t0, 8" 00000055 0x4 diff --git a/test/db/asm/mips_v2_64 b/test/db/asm/mips_v2_64 index b274fc9d2e2..d8c1cb1c4a2 100644 --- a/test/db/asm/mips_v2_64 +++ b/test/db/asm/mips_v2_64 @@ -1,2 +1,2 @@ -d "lwc3 0, (zero)" 000000cc -d "swc3 0, (zero)" 000000ec \ No newline at end of file +dB "lwc3 0, (zero)" 000000cc +dB "swc3 0, (zero)" 000000ec diff --git a/test/db/asm/tricore b/test/db/asm/tricore index 10e01f1f193..dc6e189055d 100644 --- a/test/db/asm/tricore +++ b/test/db/asm/tricore @@ -265,16 +265,16 @@ d "caddn d1, d8, d4, #0xf0" ab042f18 0x000000 (seq (set condition (is_zero (var d "caddn d15, d14, d4, #-0x59" ab743afe 0x000000 (seq (set condition (is_zero (var d14))) (set result (ite (var condition) (+ (var d4) (bv 32 0xffffffa7)) (var d4))) (set d15 (var result)) (set overflow (|| (! (sle (var result) (bv 32 0x7fffffff))) (&& (sle (var result) (bv 32 0xfb3b4c00)) (! (== (var result) (bv 32 0xfb3b4c00)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (branch (&& (var condition) (var overflow)) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result) (bv 32 0x1f) false) (bv 32 0x1)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (branch (&& (var condition) (var advanced_overflow)) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop)) d "caddn d10, d12, d0, #0x26" ab6022ac 0x000000 (seq (set condition (is_zero (var d12))) (set result (ite (var condition) (+ (var d0) (bv 32 0x26)) (var d0))) (set d10 (var result)) (set overflow (|| (! (sle (var result) (bv 32 0x7fffffff))) (&& (sle (var result) (bv 32 0xfb3b4c00)) (! (== (var result) (bv 32 0xfb3b4c00)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (branch (&& (var condition) (var overflow)) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result) (bv 32 0x1f) false) (bv 32 0x1)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (branch (&& (var condition) (var advanced_overflow)) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop)) d "caddn d10, d15, #6" ca6a 0x000000 (seq (set condition (is_zero (var d15))) (set result (ite (var condition) (+ (var d10) (bv 32 0x6)) (var d10))) (set d10 (var result)) (set overflow (|| (! (sle (var result) (bv 32 0x7fffffff))) (&& (sle (var result) (bv 32 0xfb3b4c00)) (! (== (var result) (bv 32 0xfb3b4c00)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (branch (&& (var condition) (var overflow)) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result) (bv 32 0x1f) false) (bv 32 0x1)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (branch (&& (var condition) (var advanced_overflow)) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop)) -d "call #0" 5ccd 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0))))) -d "call #0" 5c97 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0))))) -d "call #0" 5cc4 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0))))) -d "call #0xffca2984" 6d65c214 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffca2984))))) -d "call #0x6f75c0" 6db7e0ba 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x6f75c0))))) -d "call #0x211d4e" 6d90a78e 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x211d4e))))) -d "call #0" 5c56 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0))))) -d "calla #0x3ee66" eda133f7 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x3ee66))))) -d "calla #0x66fee" ed23f737 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x66fee))))) -d "calla #0x1963c6" edece3b1 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x1963c6))))) +d "call #0xffffff9a" 5ccd 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffffff9a))))) +d "call #0xffffff2e" 5c97 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffffff2e))))) +d "call #0xffffff88" 5cc4 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffffff88))))) +d "call #0xca2984" 6d65c214 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xca2984))))) +d "call #0xff6f75c0" 6db7e0ba 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xff6f75c0))))) +d "call #0xff211d4e" 6d90a78e 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xff211d4e))))) +d "call #0xac" 5c56 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xac))))) +d "calla #0xa003ee66" eda133f7 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xa003ee66))))) +d "calla #0x20066fee" ed23f737 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x20066fee))))) +d "calla #0xe01963c6" edece3b1 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xe01963c6))))) d "calli a7" 2d070000 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (var a7))))) d "calli a5" 2d050000 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (var a5))))) d "calli a8" 2d080000 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (var a8))))) @@ -451,12 +451,12 @@ d "extr.u d11, d0, d1, #0x19" 570079b1 0x000000 (set d11 (& (>> (>> (var d0) (& d "extr.u d5, d10, d0, #0xf" 570a6f50 0x000000 (set d5 (& (>> (>> (var d10) (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1f)) false) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0xf)) false))) d "extr.u d7, d6, d4, #6" 57066674 0x000000 (set d7 (& (>> (>> (var d6) (& (>> (var d4) (bv 32 0x0) false) (bv 32 0x1f)) false) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x6)) false))) d "extr.u d6, d15, #0x18, #0x17" 37bf776c 0x000000 (set d6 (& (>> (>> (var d15) (bv 32 0x18) false) (bv 32 0x0) false) (bv 32 0x7fffff))) -d "fcall #0xffa5b39e" 6152cfd9 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xffa5b39e))) +d "fcall #0xa5b39e" 6152cfd9 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xa5b39e))) d "fcall #0x484984" 6124c224 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x484984))) -d "fcall #0xff9d43ba" 614edda1 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xff9d43ba))) +d "fcall #0x9d43ba" 614edda1 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x9d43ba))) d "fcalla #0x1b1386" e10dc389 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x1b1386))) -d "fcalla #0xb8ff0" e145f8c7 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xb8ff0))) -d "fcalla #0x293e0" e1b1f049 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x293e0))) +d "fcalla #0x400b8ff0" e145f8c7 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x400b8ff0))) +d "fcalla #0xb00293e0" e1b1f049 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xb00293e0))) d "fcalli a3" 2d031000 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (var a3))) d "fcalli a11" 2d0b1000 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (var a11))) d "fcalli a9" 2d091000 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (var a9))) @@ -563,9 +563,9 @@ d "j #0xff9ae1aa" 1dcdd570 0x000000 (jmp (bv 32 0xff9ae1aa)) d "j #0xff8a2c4c" 1dc52616 0x000000 (jmp (bv 32 0xff8a2c4c)) d "j #0xb2" 3c59 0x000000 (jmp (bv 32 0xb2)) d "j #0x86" 3c43 0x000000 (jmp (bv 32 0x86)) -d "ja #0x1c06e2" 9dce7103 0x000000 (jmp (bv 32 0x180dc4)) -d "ja #0xc099c" 9d56ce04 0x000000 (jmp (bv 32 0x181338)) -d "ja #0x168402" 9dcb0142 0x000000 (jmp (bv 32 0xd0804)) +d "ja #0xc01c06e2" 9dce7103 0x0 (jmp (bv 32 0x180dc4)) +d "ja #0x500c099c" 9d56ce04 0x0 (jmp (bv 32 0x181338)) +d "ja #0xc0168402" 9dcb0142 0x0 (jmp (bv 32 0xd0804)) d "jeq d15, d11, #0x38" bebc 0x000000 (branch (== (var d15) (var d11)) (jmp (bv 32 0x38)) nop) d "jeq d15, d12, #0x32" bec9 0x000000 (branch (== (var d15) (var d12)) (jmp (bv 32 0x32)) nop) d "jeq d15, d0, #0x38" be0c 0x000000 (branch (== (var d15) (var d0)) (jmp (bv 32 0x38)) nop) @@ -628,9 +628,9 @@ d "ji a11" 2d0b3000 0x000000 (jmp (& (var a11) (bv 32 0xfffffffe))) d "jl #0xff5172aa" 5da855b9 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0xff5172aa))) d "jl #0xaac39c" 5d55ce61 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0xaac39c))) d "jl #0xd88610" 5d6c0843 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0xd88610))) -d "jla #0xd0a9a" ddd64d85 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1a1534))) -d "jla #0xf287c" dd973e94 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1e50f8))) -d "jla #0x14a656" dd8a2b53 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x94cac))) +d "jla #0xd00d0a9a" ddd64d85 0x0 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1a1534))) +d "jla #0x900f287c" dd973e94 0x0 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1e50f8))) +d "jla #0x8014a656" dd8a2b53 0x0 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x94cac))) d "jlez d11, #2" 8eb1 0x000000 (branch (sle (var d11) (bv 32 0x0)) (jmp (bv 32 0x2)) nop) d "jlez d13, #0x1a" 8edd 0x000000 (branch (sle (var d13) (bv 32 0x0)) (jmp (bv 32 0x1a)) nop) d "jlez d10, #2" 8ea1 0x000000 (branch (sle (var d10) (bv 32 0x0)) (jmp (bv 32 0x2)) nop) @@ -903,14 +903,14 @@ d "lea a13, [a1]#-0xa8" 491d18da 0x000000 (seq (set EA (+ (var a1) (bv 32 0xffff d "loop a0, #0xfffffffc" fc0e 0x000000 (seq (set PC (ite (! (is_zero (var a0))) (bv 32 0xfffffffc) (bv 32 0x2))) (set a0 (- (var a0) (bv 32 0x1))) (jmp (var PC))) d "loop a7, #0xffffffe8" fc74 0x000000 (seq (set PC (ite (! (is_zero (var a7))) (bv 32 0xffffffe8) (bv 32 0x2))) (set a7 (- (var a7) (bv 32 0x1))) (jmp (var PC))) d "loop a5, #0xfffffff8" fc5c 0x000000 (seq (set PC (ite (! (is_zero (var a5))) (bv 32 0xfffffff8) (bv 32 0x2))) (set a5 (- (var a5) (bv 32 0x1))) (jmp (var PC))) -d "loop a0, #0xfffff0ea" fd007538 0x000000 (seq (set PC (ite (! (is_zero (var a0))) (bv 32 0xfffff0ea) (bv 32 0x4))) (set a0 (- (var a0) (bv 32 0x1))) (jmp (var PC))) -d "loop a5, #0xffffd610" fd50082b 0x000000 (seq (set PC (ite (! (is_zero (var a5))) (bv 32 0xffffd610) (bv 32 0x4))) (set a5 (- (var a5) (bv 32 0x1))) (jmp (var PC))) -d "loop a12, #0x11c4" fdc0e248 0x000000 (seq (set PC (ite (! (is_zero (var a12))) (bv 32 0x11c4) (bv 32 0x4))) (set a12 (- (var a12) (bv 32 0x1))) (jmp (var PC))) +d "loop a0, #0x70ea" fd007538 0x0 (seq (set PC (ite (! (is_zero (var a0))) (bv 32 0x70ea) (bv 32 0x4))) (set a0 (- (var a0) (bv 32 0x1))) (jmp (var PC))) +d "loop a5, #0x5610" fd50082b 0x0 (seq (set PC (ite (! (is_zero (var a5))) (bv 32 0x5610) (bv 32 0x4))) (set a5 (- (var a5) (bv 32 0x1))) (jmp (var PC))) +d "loop a12, #0xffff91c4" fdc0e248 0x0 (seq (set PC (ite (! (is_zero (var a12))) (bv 32 0xffff91c4) (bv 32 0x4))) (set a12 (- (var a12) (bv 32 0x1))) (jmp (var PC))) d "loop a4, #0xfffffff8" fc4c 0x000000 (seq (set PC (ite (! (is_zero (var a4))) (bv 32 0xfffffff8) (bv 32 0x2))) (set a4 (- (var a4) (bv 32 0x1))) (jmp (var PC))) d "loop a4, #0xffffffe6" fc43 0x000000 (seq (set PC (ite (! (is_zero (var a4))) (bv 32 0xffffffe6) (bv 32 0x2))) (set a4 (- (var a4) (bv 32 0x1))) (jmp (var PC))) d "loopu #0xffffcbe8" fd00f4e5 0x000000 (jmp (bv 32 0xffffcbe8)) -d "loopu #0xf0a" fd0085c7 0x000000 (jmp (bv 32 0xf0a)) -d "loopu #0xfffff714" fd008abb 0x000000 (jmp (bv 32 0xfffff714)) +d "loopu #0xffff8f0a" fd0085c7 0x0 (jmp (bv 32 0xffff8f0a)) +d "loopu #0x7714" fd008abb 0x0 (jmp (bv 32 0x7714)) d "lt d15, d12, d11" 7abc 0x000000 (set d15 (ite (&& (sle (var d12) (var d11)) (! (== (var d12) (var d11)))) (bv 32 0x1) (bv 32 0x0))) d "lt d15, d1, d1" 7a11 0x000000 (set d15 (ite (&& (sle (var d1) (var d1)) (! (== (var d1) (var d1)))) (bv 32 0x1) (bv 32 0x0))) d "lt d15, d7, d7" 7a77 0x000000 (set d15 (ite (&& (sle (var d7) (var d7)) (! (== (var d7) (var d7)))) (bv 32 0x1) (bv 32 0x0))) diff --git a/test/db/cmd/cmd_pd b/test/db/cmd/cmd_pd index 0d10715a96b..327b3b75104 100644 --- a/test/db/cmd/cmd_pd +++ b/test/db/cmd/cmd_pd @@ -2709,6 +2709,7 @@ EXPECT=<