index.json

[{"authors":["admin"],"categories":null,"content":"Hey there! I am a CPU Design Engineer at Qualcomm, India. Prior to this, I completed my undergraduate degree in Electronics and Communication Engineering from IIIT Delhi, where I spent an amazing time at AMS Lab, headed by Prof. Sujay Deb. My undergraduate research was also supervised by Prof. Lam Siew Kei during my amazing time at Nanyang Technological University, Singapore, working on hardware security algorithms for off-chip memories.\n","date":-62135596800,"expirydate":-62135596800,"kind":"taxonomy","lang":"en","lastmod":-62135596800,"objectID":"2525497d367e79493fd32b198b28f040","permalink":"/authors/admin/","publishdate":"0001-01-01T00:00:00Z","relpermalink":"/authors/admin/","section":"authors","summary":"Hey there! I am a CPU Design Engineer at Qualcomm, India. Prior to this, I completed my undergraduate degree in Electronics and Communication Engineering from IIIT Delhi, where I spent an amazing time at AMS Lab, headed by Prof. Sujay Deb. My undergraduate research was also supervised by Prof. Lam Siew Kei during my amazing time at Nanyang Technological University, Singapore, working on hardware security algorithms for off-chip memories.","tags":null,"title":"Rohan Juneja","type":"authors"},{"authors":["Saru Vig","Rohan Juneja","Guiyuan Jiang","Siew-Kei Lam","and Changhai Ou"],"categories":[],"content":"","date":1562087216,"expirydate":-62135596800,"kind":"page","lang":"en","lastmod":1567530416,"objectID":"6a932c732b287e2bf20a964721c0d106","permalink":"/publication/dynamic_skewed_tree/","publishdate":"2019-07-02T22:36:56+05:30","relpermalink":"/publication/dynamic_skewed_tree/","section":"publication","summary":"Integrity trees are widely used in computer systems to prevent replay, splicing, and spoofing attacks on memories. Such mechanisms incur excessive performance and energy overhead. We propose a memory authentication framework that combines architecture-specific optimizations of the integrity tree with mechanisms that enable it to restructure at runtime based on memory access patterns. The integrity tree structure is customized based on the cache configuration in order to minimize the performance and energy overhead through speculative authentication. At runtime, the tree nodes that are accessed more frequently will be dynamically shifted closer to the root such that fewer levels of the tree are accessed during authentication. The framework is simulated withMulti2Sim and compared with other existing mechanisms [i.e., tamper-evident counter (TEC) tree and ASSURE] to demonstrate its performance and energy benefits. Experimental results using benchmarks from SPEC-CPU2006, SPLASH-2, and PARSEC show that the proposed dynamic integrity tree leads to an average reduction in instruction per cycle of 13% and 10% over TEC tree and ASSURE, respectively. The corresponding average reduction in authentication time is 30% and 20%, respectively. We show that the proposed framework facilitates the selection of a processor with a smaller cache size such that the energy consumption is reduced without sacrificing performance.","tags":[],"title":"Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree","type":"publication"},{"authors":["Sidhartha Sankar Rout","Hemanta Kumar Mondal","Rohan Juneja","Sri Harsha Gade","Sujay Deb"],"categories":[],"content":"","date":1525971439,"expirydate":-62135596800,"kind":"page","lang":"en","lastmod":1567529839,"objectID":"8932eff55a584792b8a4c2bde11d91ad","permalink":"/publication/dynamic_noc_platform/","publishdate":"2018-05-10T22:27:19+05:30","relpermalink":"/publication/dynamic_noc_platform/","section":"publication","summary":"Many-core processing platforms are gaining significant interest for a wide range of applications, viz., Internet of Things (IoT), consumer electronics, single-chip cloud computers, supercomputers, defense applications etc. Networks-on-Chip (NoCs) are accepted as the communication backbone for these many-core platforms. However, energy consumption in NoC components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure. The usage of the routers and resources associated with it are application dependent and for most applications performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable system that can switch between both high performance and low power modes will be able to exploit the variable workload conditions provided by different applications. Among all the NoC components, Virtual Channels (VCs) are the most power hungry modules. This paper proposes a dynamic NoC platform (DNoC) that optimizes VC utilization for different applications using a smart router architecture. Power Management Controller (PMC) along with Utilization Computation Unit (UCU) controls and predicts the number of active VCs to achieve the required performance with minimum overhead. In our experiments the proposed solution provides 83.3% power benefit (best case scenario) with negligible throughput penalty compared to a baseline mesh router.","tags":[],"title":"Dynamic NoC Platform for Varied Application Needs","type":"publication"}]