diff --git a/src/inner/accessctrl/adc0.rs b/src/inner/accessctrl/adc0.rs
index 329075c..686c8c0 100644
--- a/src/inner/accessctrl/adc0.rs
+++ b/src/inner/accessctrl/adc0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<ADC0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, ADC0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<ADC0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<ADC0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, ADC0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<ADC0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<ADC0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<ADC0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<ADC0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<ADC0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/busctrl.rs b/src/inner/accessctrl/busctrl.rs
index e554ae4..3bd6244 100644
--- a/src/inner/accessctrl/busctrl.rs
+++ b/src/inner/accessctrl/busctrl.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<BUSCTRL_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<BUSCTRL_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<BUSCTRL_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, BUSCTRL can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<BUSCTRL_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<BUSCTRL_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<BUSCTRL_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<BUSCTRL_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<BUSCTRL_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/cfgreset.rs b/src/inner/accessctrl/cfgreset.rs
index 02040d6..f7ac1fb 100644
--- a/src/inner/accessctrl/cfgreset.rs
+++ b/src/inner/accessctrl/cfgreset.rs
@@ -7,7 +7,6 @@ pub type CFGRESET_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cfgreset(&mut self) -> CFGRESET_W<CFGRESET_SPEC> {
         CFGRESET_W::new(self, 0)
     }
diff --git a/src/inner/accessctrl/clocks.rs b/src/inner/accessctrl/clocks.rs
index 84f3dfa..3b0d51b 100644
--- a/src/inner/accessctrl/clocks.rs
+++ b/src/inner/accessctrl/clocks.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<CLOCKS_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<CLOCKS_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<CLOCKS_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, CLOCKS can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<CLOCKS_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<CLOCKS_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<CLOCKS_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<CLOCKS_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<CLOCKS_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/coresight_periph.rs b/src/inner/accessctrl/coresight_periph.rs
index 09c0528..411cc1c 100644
--- a/src/inner/accessctrl/coresight_periph.rs
+++ b/src/inner/accessctrl/coresight_periph.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<CORESIGHT_PERIPH_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<CORESIGHT_PERIPH_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<CORESIGHT_PERIPH_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<CORESIGHT_PERIPH_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<CORESIGHT_PERIPH_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<CORESIGHT_PERIPH_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<CORESIGHT_PERIPH_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<CORESIGHT_PERIPH_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/coresight_trace.rs b/src/inner/accessctrl/coresight_trace.rs
index 26aca72..d55a99f 100644
--- a/src/inner/accessctrl/coresight_trace.rs
+++ b/src/inner/accessctrl/coresight_trace.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<CORESIGHT_TRACE_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<CORESIGHT_TRACE_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<CORESIGHT_TRACE_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<CORESIGHT_TRACE_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<CORESIGHT_TRACE_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<CORESIGHT_TRACE_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<CORESIGHT_TRACE_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<CORESIGHT_TRACE_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/dma.rs b/src/inner/accessctrl/dma.rs
index f4456c1..89914e0 100644
--- a/src/inner/accessctrl/dma.rs
+++ b/src/inner/accessctrl/dma.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<DMA_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, DMA can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<DMA_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<DMA_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, DMA can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<DMA_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<DMA_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<DMA_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<DMA_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<DMA_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/force_core_ns.rs b/src/inner/accessctrl/force_core_ns.rs
index 4db7c48..c10bbd7 100644
--- a/src/inner/accessctrl/force_core_ns.rs
+++ b/src/inner/accessctrl/force_core_ns.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<FORCE_CORE_NS_SPEC> {
         CORE1_W::new(self, 1)
     }
diff --git a/src/inner/accessctrl/gpio_nsmask0.rs b/src/inner/accessctrl/gpio_nsmask0.rs
index 66eae62..6cd8628 100644
--- a/src/inner/accessctrl/gpio_nsmask0.rs
+++ b/src/inner/accessctrl/gpio_nsmask0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_nsmask0(&mut self) -> GPIO_NSMASK0_W<GPIO_NSMASK0_SPEC> {
         GPIO_NSMASK0_W::new(self, 0)
     }
diff --git a/src/inner/accessctrl/gpio_nsmask1.rs b/src/inner/accessctrl/gpio_nsmask1.rs
index 7f70333..d718fde 100644
--- a/src/inner/accessctrl/gpio_nsmask1.rs
+++ b/src/inner/accessctrl/gpio_nsmask1.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_NSMASK1_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_NSMASK1_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_NSMASK1_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_NSMASK1_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_NSMASK1_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_NSMASK1_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/accessctrl/hstx.rs b/src/inner/accessctrl/hstx.rs
index c7b2097..02fd611 100644
--- a/src/inner/accessctrl/hstx.rs
+++ b/src/inner/accessctrl/hstx.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<HSTX_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, HSTX can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<HSTX_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<HSTX_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, HSTX can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<HSTX_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<HSTX_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<HSTX_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<HSTX_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<HSTX_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/i2c0.rs b/src/inner/accessctrl/i2c0.rs
index 55deab7..fc88f2a 100644
--- a/src/inner/accessctrl/i2c0.rs
+++ b/src/inner/accessctrl/i2c0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<I2C0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, I2C0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<I2C0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<I2C0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, I2C0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<I2C0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<I2C0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<I2C0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<I2C0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<I2C0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/i2c1.rs b/src/inner/accessctrl/i2c1.rs
index 986f909..9c0d22b 100644
--- a/src/inner/accessctrl/i2c1.rs
+++ b/src/inner/accessctrl/i2c1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<I2C1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, I2C1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<I2C1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<I2C1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, I2C1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<I2C1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<I2C1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<I2C1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<I2C1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<I2C1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/io_bank0.rs b/src/inner/accessctrl/io_bank0.rs
index 56ac6c6..a5ad566 100644
--- a/src/inner/accessctrl/io_bank0.rs
+++ b/src/inner/accessctrl/io_bank0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<IO_BANK0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<IO_BANK0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<IO_BANK0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, IO_BANK0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<IO_BANK0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<IO_BANK0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<IO_BANK0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<IO_BANK0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<IO_BANK0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/io_bank1.rs b/src/inner/accessctrl/io_bank1.rs
index be32165..5b19594 100644
--- a/src/inner/accessctrl/io_bank1.rs
+++ b/src/inner/accessctrl/io_bank1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<IO_BANK1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<IO_BANK1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<IO_BANK1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, IO_BANK1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<IO_BANK1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<IO_BANK1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<IO_BANK1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<IO_BANK1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<IO_BANK1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/lock.rs b/src/inner/accessctrl/lock.rs
index a185f49..78acf2e 100644
--- a/src/inner/accessctrl/lock.rs
+++ b/src/inner/accessctrl/lock.rs
@@ -41,19 +41,16 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<LOCK_SPEC> {
         CORE0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<LOCK_SPEC> {
         CORE1_W::new(self, 1)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn debug(&mut self) -> DEBUG_W<LOCK_SPEC> {
         DEBUG_W::new(self, 3)
     }
diff --git a/src/inner/accessctrl/otp.rs b/src/inner/accessctrl/otp.rs
index 6490180..d6e92f6 100644
--- a/src/inner/accessctrl/otp.rs
+++ b/src/inner/accessctrl/otp.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<OTP_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, OTP can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<OTP_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<OTP_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, OTP can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<OTP_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<OTP_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<OTP_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<OTP_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<OTP_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pads_bank0.rs b/src/inner/accessctrl/pads_bank0.rs
index fb9c7d4..df81277 100644
--- a/src/inner/accessctrl/pads_bank0.rs
+++ b/src/inner/accessctrl/pads_bank0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PADS_BANK0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PADS_BANK0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PADS_BANK0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PADS_BANK0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PADS_BANK0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PADS_BANK0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PADS_BANK0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PADS_BANK0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pads_qspi.rs b/src/inner/accessctrl/pads_qspi.rs
index 6d922ad..764e413 100644
--- a/src/inner/accessctrl/pads_qspi.rs
+++ b/src/inner/accessctrl/pads_qspi.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PADS_QSPI_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PADS_QSPI_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PADS_QSPI_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PADS_QSPI can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PADS_QSPI_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PADS_QSPI_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PADS_QSPI_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PADS_QSPI_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PADS_QSPI_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pio0.rs b/src/inner/accessctrl/pio0.rs
index 5a7ab7b..ccd6d4a 100644
--- a/src/inner/accessctrl/pio0.rs
+++ b/src/inner/accessctrl/pio0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PIO0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PIO0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PIO0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PIO0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PIO0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PIO0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PIO0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PIO0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PIO0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PIO0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pio1.rs b/src/inner/accessctrl/pio1.rs
index eb44216..103f9c6 100644
--- a/src/inner/accessctrl/pio1.rs
+++ b/src/inner/accessctrl/pio1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PIO1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PIO1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PIO1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PIO1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PIO1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PIO1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PIO1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PIO1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PIO1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PIO1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pio2.rs b/src/inner/accessctrl/pio2.rs
index ccca80a..922266c 100644
--- a/src/inner/accessctrl/pio2.rs
+++ b/src/inner/accessctrl/pio2.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PIO2_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PIO2 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PIO2_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PIO2_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PIO2 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PIO2_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PIO2_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PIO2_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PIO2_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PIO2_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pll_sys.rs b/src/inner/accessctrl/pll_sys.rs
index 06fd222..41bd1ff 100644
--- a/src/inner/accessctrl/pll_sys.rs
+++ b/src/inner/accessctrl/pll_sys.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PLL_SYS_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PLL_SYS_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PLL_SYS_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PLL_SYS can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PLL_SYS_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PLL_SYS_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PLL_SYS_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PLL_SYS_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PLL_SYS_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pll_usb.rs b/src/inner/accessctrl/pll_usb.rs
index 4fda9ea..3047d13 100644
--- a/src/inner/accessctrl/pll_usb.rs
+++ b/src/inner/accessctrl/pll_usb.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PLL_USB_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PLL_USB can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PLL_USB_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PLL_USB_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PLL_USB can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PLL_USB_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PLL_USB_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PLL_USB_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PLL_USB_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PLL_USB_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/powman.rs b/src/inner/accessctrl/powman.rs
index 3c25735..384cbb9 100644
--- a/src/inner/accessctrl/powman.rs
+++ b/src/inner/accessctrl/powman.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<POWMAN_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, POWMAN can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<POWMAN_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<POWMAN_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, POWMAN can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<POWMAN_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<POWMAN_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<POWMAN_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<POWMAN_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<POWMAN_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/pwm.rs b/src/inner/accessctrl/pwm.rs
index 71f9c5f..829f966 100644
--- a/src/inner/accessctrl/pwm.rs
+++ b/src/inner/accessctrl/pwm.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<PWM_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, PWM can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<PWM_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<PWM_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, PWM can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<PWM_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<PWM_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<PWM_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<PWM_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<PWM_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/resets.rs b/src/inner/accessctrl/resets.rs
index 26a3e39..e9a280e 100644
--- a/src/inner/accessctrl/resets.rs
+++ b/src/inner/accessctrl/resets.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<RESETS_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, RESETS can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<RESETS_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<RESETS_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, RESETS can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<RESETS_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<RESETS_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<RESETS_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<RESETS_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<RESETS_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/rom.rs b/src/inner/accessctrl/rom.rs
index 9aa0dae..8b02776 100644
--- a/src/inner/accessctrl/rom.rs
+++ b/src/inner/accessctrl/rom.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<ROM_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, ROM can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<ROM_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<ROM_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, ROM can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<ROM_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<ROM_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<ROM_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<ROM_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<ROM_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/rosc.rs b/src/inner/accessctrl/rosc.rs
index f13955b..f4b683e 100644
--- a/src/inner/accessctrl/rosc.rs
+++ b/src/inner/accessctrl/rosc.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<ROSC_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, ROSC can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<ROSC_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<ROSC_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, ROSC can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<ROSC_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<ROSC_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<ROSC_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<ROSC_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<ROSC_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/rsm.rs b/src/inner/accessctrl/rsm.rs
index 9f70dd3..efe98c1 100644
--- a/src/inner/accessctrl/rsm.rs
+++ b/src/inner/accessctrl/rsm.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<RSM_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, RSM can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<RSM_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<RSM_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, RSM can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<RSM_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<RSM_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<RSM_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<RSM_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<RSM_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sha256.rs b/src/inner/accessctrl/sha256.rs
index c390ce6..63f454c 100644
--- a/src/inner/accessctrl/sha256.rs
+++ b/src/inner/accessctrl/sha256.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SHA256_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SHA256 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SHA256_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SHA256_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SHA256 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SHA256_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SHA256_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SHA256_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SHA256_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SHA256_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/spi0.rs b/src/inner/accessctrl/spi0.rs
index 3571012..c23b9c2 100644
--- a/src/inner/accessctrl/spi0.rs
+++ b/src/inner/accessctrl/spi0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SPI0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SPI0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SPI0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SPI0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SPI0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SPI0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SPI0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SPI0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SPI0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SPI0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/spi1.rs b/src/inner/accessctrl/spi1.rs
index a5d0b8c..01ecf37 100644
--- a/src/inner/accessctrl/spi1.rs
+++ b/src/inner/accessctrl/spi1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SPI1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SPI1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SPI1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SPI1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SPI1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SPI1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SPI1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SPI1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SPI1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SPI1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram0.rs b/src/inner/accessctrl/sram0.rs
index 305eb1b..034e924 100644
--- a/src/inner/accessctrl/sram0.rs
+++ b/src/inner/accessctrl/sram0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram1.rs b/src/inner/accessctrl/sram1.rs
index d840f02..5fdbd9b 100644
--- a/src/inner/accessctrl/sram1.rs
+++ b/src/inner/accessctrl/sram1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram2.rs b/src/inner/accessctrl/sram2.rs
index 8597fed..db4f454 100644
--- a/src/inner/accessctrl/sram2.rs
+++ b/src/inner/accessctrl/sram2.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM2_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM2 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM2_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM2_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM2 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM2_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM2_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM2_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM2_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM2_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram3.rs b/src/inner/accessctrl/sram3.rs
index c4ff6f3..d966e07 100644
--- a/src/inner/accessctrl/sram3.rs
+++ b/src/inner/accessctrl/sram3.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM3_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM3 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM3_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM3_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM3 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM3_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM3_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM3_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM3_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM3_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram4.rs b/src/inner/accessctrl/sram4.rs
index c222ed2..3aabb5c 100644
--- a/src/inner/accessctrl/sram4.rs
+++ b/src/inner/accessctrl/sram4.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM4_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM4 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM4_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM4_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM4 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM4_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM4_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM4_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM4_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM4_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram5.rs b/src/inner/accessctrl/sram5.rs
index b5ff7a1..b593d59 100644
--- a/src/inner/accessctrl/sram5.rs
+++ b/src/inner/accessctrl/sram5.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM5_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM5 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM5_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM5_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM5 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM5_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM5_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM5_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM5_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM5_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram6.rs b/src/inner/accessctrl/sram6.rs
index e03e7b5..2c9a676 100644
--- a/src/inner/accessctrl/sram6.rs
+++ b/src/inner/accessctrl/sram6.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM6_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM6 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM6_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM6_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM6 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM6_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM6_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM6_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM6_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM6_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram7.rs b/src/inner/accessctrl/sram7.rs
index 4edcad8..66e8b82 100644
--- a/src/inner/accessctrl/sram7.rs
+++ b/src/inner/accessctrl/sram7.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM7_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM7 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM7_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM7_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM7 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM7_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM7_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM7_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM7_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM7_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram8.rs b/src/inner/accessctrl/sram8.rs
index c7aba32..c965d45 100644
--- a/src/inner/accessctrl/sram8.rs
+++ b/src/inner/accessctrl/sram8.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM8_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM8 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM8_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM8_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM8 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM8_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM8_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM8_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM8_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM8_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sram9.rs b/src/inner/accessctrl/sram9.rs
index e2eead6..cf57351 100644
--- a/src/inner/accessctrl/sram9.rs
+++ b/src/inner/accessctrl/sram9.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SRAM9_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SRAM9 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SRAM9_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SRAM9_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SRAM9 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SRAM9_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SRAM9_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SRAM9_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SRAM9_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SRAM9_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/syscfg.rs b/src/inner/accessctrl/syscfg.rs
index 28e67c7..dbf42fe 100644
--- a/src/inner/accessctrl/syscfg.rs
+++ b/src/inner/accessctrl/syscfg.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SYSCFG_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SYSCFG can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SYSCFG_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SYSCFG_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SYSCFG can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SYSCFG_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SYSCFG_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SYSCFG_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SYSCFG_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SYSCFG_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/sysinfo.rs b/src/inner/accessctrl/sysinfo.rs
index 1bdd2e3..5d5549a 100644
--- a/src/inner/accessctrl/sysinfo.rs
+++ b/src/inner/accessctrl/sysinfo.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<SYSINFO_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, SYSINFO can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<SYSINFO_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<SYSINFO_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, SYSINFO can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<SYSINFO_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<SYSINFO_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<SYSINFO_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<SYSINFO_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<SYSINFO_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/tbman.rs b/src/inner/accessctrl/tbman.rs
index 13e4b7c..ef8d048 100644
--- a/src/inner/accessctrl/tbman.rs
+++ b/src/inner/accessctrl/tbman.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<TBMAN_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, TBMAN can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<TBMAN_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<TBMAN_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, TBMAN can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<TBMAN_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<TBMAN_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<TBMAN_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<TBMAN_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<TBMAN_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/ticks.rs b/src/inner/accessctrl/ticks.rs
index 5383bd8..ec8356f 100644
--- a/src/inner/accessctrl/ticks.rs
+++ b/src/inner/accessctrl/ticks.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<TICKS_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, TICKS can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<TICKS_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<TICKS_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, TICKS can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<TICKS_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<TICKS_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<TICKS_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<TICKS_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<TICKS_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/timer0.rs b/src/inner/accessctrl/timer0.rs
index 8be8e7b..2d9f021 100644
--- a/src/inner/accessctrl/timer0.rs
+++ b/src/inner/accessctrl/timer0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<TIMER0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, TIMER0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<TIMER0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<TIMER0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, TIMER0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<TIMER0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<TIMER0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<TIMER0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<TIMER0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<TIMER0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/timer1.rs b/src/inner/accessctrl/timer1.rs
index cc65ee6..3b35f9e 100644
--- a/src/inner/accessctrl/timer1.rs
+++ b/src/inner/accessctrl/timer1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<TIMER1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, TIMER1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<TIMER1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<TIMER1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, TIMER1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<TIMER1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<TIMER1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<TIMER1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<TIMER1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<TIMER1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/trng.rs b/src/inner/accessctrl/trng.rs
index 361bc67..77f3f87 100644
--- a/src/inner/accessctrl/trng.rs
+++ b/src/inner/accessctrl/trng.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<TRNG_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, TRNG can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<TRNG_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<TRNG_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, TRNG can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<TRNG_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<TRNG_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<TRNG_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<TRNG_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<TRNG_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/uart0.rs b/src/inner/accessctrl/uart0.rs
index 1572293..4347849 100644
--- a/src/inner/accessctrl/uart0.rs
+++ b/src/inner/accessctrl/uart0.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<UART0_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, UART0 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<UART0_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<UART0_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, UART0 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<UART0_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<UART0_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<UART0_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<UART0_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<UART0_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/uart1.rs b/src/inner/accessctrl/uart1.rs
index 3df7fce..c7fc20f 100644
--- a/src/inner/accessctrl/uart1.rs
+++ b/src/inner/accessctrl/uart1.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<UART1_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, UART1 can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<UART1_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<UART1_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, UART1 can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<UART1_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<UART1_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<UART1_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<UART1_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<UART1_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/usbctrl.rs b/src/inner/accessctrl/usbctrl.rs
index 4122987..837f5aa 100644
--- a/src/inner/accessctrl/usbctrl.rs
+++ b/src/inner/accessctrl/usbctrl.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<USBCTRL_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, USBCTRL can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<USBCTRL_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<USBCTRL_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, USBCTRL can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<USBCTRL_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<USBCTRL_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<USBCTRL_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<USBCTRL_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<USBCTRL_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/watchdog.rs b/src/inner/accessctrl/watchdog.rs
index 9d45352..c7fdbae 100644
--- a/src/inner/accessctrl/watchdog.rs
+++ b/src/inner/accessctrl/watchdog.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<WATCHDOG_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<WATCHDOG_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<WATCHDOG_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, WATCHDOG can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<WATCHDOG_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<WATCHDOG_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<WATCHDOG_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<WATCHDOG_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<WATCHDOG_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/xip_aux.rs b/src/inner/accessctrl/xip_aux.rs
index c8546ae..a643554 100644
--- a/src/inner/accessctrl/xip_aux.rs
+++ b/src/inner/accessctrl/xip_aux.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<XIP_AUX_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<XIP_AUX_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<XIP_AUX_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, XIP_AUX can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<XIP_AUX_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<XIP_AUX_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<XIP_AUX_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<XIP_AUX_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<XIP_AUX_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/xip_ctrl.rs b/src/inner/accessctrl/xip_ctrl.rs
index 8850ea0..f51a02c 100644
--- a/src/inner/accessctrl/xip_ctrl.rs
+++ b/src/inner/accessctrl/xip_ctrl.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<XIP_CTRL_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<XIP_CTRL_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<XIP_CTRL_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, XIP_CTRL can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<XIP_CTRL_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<XIP_CTRL_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<XIP_CTRL_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<XIP_CTRL_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<XIP_CTRL_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/xip_main.rs b/src/inner/accessctrl/xip_main.rs
index deb61b4..8515b67 100644
--- a/src/inner/accessctrl/xip_main.rs
+++ b/src/inner/accessctrl/xip_main.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<XIP_MAIN_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<XIP_MAIN_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<XIP_MAIN_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, XIP_MAIN can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<XIP_MAIN_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<XIP_MAIN_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<XIP_MAIN_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<XIP_MAIN_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<XIP_MAIN_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/xip_qmi.rs b/src/inner/accessctrl/xip_qmi.rs
index f90378a..70e2911 100644
--- a/src/inner/accessctrl/xip_qmi.rs
+++ b/src/inner/accessctrl/xip_qmi.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<XIP_QMI_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<XIP_QMI_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<XIP_QMI_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, XIP_QMI can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<XIP_QMI_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<XIP_QMI_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<XIP_QMI_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<XIP_QMI_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<XIP_QMI_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/accessctrl/xosc.rs b/src/inner/accessctrl/xosc.rs
index 1f9a2ac..b691743 100644
--- a/src/inner/accessctrl/xosc.rs
+++ b/src/inner/accessctrl/xosc.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."]
     #[inline(always)]
-    #[must_use]
     pub fn nsu(&mut self) -> NSU_W<XOSC_SPEC> {
         NSU_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, XOSC can be accessed from a Non-secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn nsp(&mut self) -> NSP_W<XOSC_SPEC> {
         NSP_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn su(&mut self) -> SU_W<XOSC_SPEC> {
         SU_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, XOSC can be accessed from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn sp(&mut self) -> SP_W<XOSC_SPEC> {
         SP_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<XOSC_SPEC> {
         CORE0_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<XOSC_SPEC> {
         CORE1_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<XOSC_SPEC> {
         DMA_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."]
     #[inline(always)]
-    #[must_use]
     pub fn dbg(&mut self) -> DBG_W<XOSC_SPEC> {
         DBG_W::new(self, 7)
     }
diff --git a/src/inner/adc.rs b/src/inner/adc.rs
index 5cdc8e9..79b666c 100644
--- a/src/inner/adc.rs
+++ b/src/inner/adc.rs
@@ -52,7 +52,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0x20 - Interrupt status after masking &amp; forcing"]
+    #[doc = "0x20 - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -130,12 +130,12 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
diff --git a/src/inner/adc/cs.rs b/src/inner/adc/cs.rs
index 47be8b5..fcaabfe 100644
--- a/src/inner/adc/cs.rs
+++ b/src/inner/adc/cs.rs
@@ -77,43 +77,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CS_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn ts_en(&mut self) -> TS_EN_W<CS_SPEC> {
         TS_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
     #[inline(always)]
-    #[must_use]
     pub fn start_once(&mut self) -> START_ONCE_W<CS_SPEC> {
         START_ONCE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
     #[inline(always)]
-    #[must_use]
     pub fn start_many(&mut self) -> START_MANY_W<CS_SPEC> {
         START_MANY_W::new(self, 3)
     }
     #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn err_sticky(&mut self) -> ERR_STICKY_W<CS_SPEC> {
         ERR_STICKY_W::new(self, 10)
     }
     #[doc = "Bits 12:15 - Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"]
     #[inline(always)]
-    #[must_use]
     pub fn ainsel(&mut self) -> AINSEL_W<CS_SPEC> {
         AINSEL_W::new(self, 12)
     }
     #[doc = "Bits 16:24 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."]
     #[inline(always)]
-    #[must_use]
     pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC> {
         RROBIN_W::new(self, 16)
     }
diff --git a/src/inner/adc/div.rs b/src/inner/adc/div.rs
index aae471b..32f3a2e 100644
--- a/src/inner/adc/div.rs
+++ b/src/inner/adc/div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 8:23 - Integer part of clock divisor."]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<DIV_SPEC> {
         INT_W::new(self, 8)
     }
diff --git a/src/inner/adc/fcs.rs b/src/inner/adc/fcs.rs
index 1493fbc..256e326 100644
--- a/src/inner/adc/fcs.rs
+++ b/src/inner/adc/fcs.rs
@@ -91,43 +91,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<FCS_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<FCS_SPEC> {
         SHIFT_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result"]
     #[inline(always)]
-    #[must_use]
     pub fn err(&mut self) -> ERR_W<FCS_SPEC> {
         ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1: assert DMA requests when FIFO contains data"]
     #[inline(always)]
-    #[must_use]
     pub fn dreq_en(&mut self) -> DREQ_EN_W<FCS_SPEC> {
         DREQ_EN_W::new(self, 3)
     }
     #[doc = "Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn under(&mut self) -> UNDER_W<FCS_SPEC> {
         UNDER_W::new(self, 10)
     }
     #[doc = "Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn over(&mut self) -> OVER_W<FCS_SPEC> {
         OVER_W::new(self, 11)
     }
     #[doc = "Bits 24:27 - DREQ/IRQ asserted when level >= threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn thresh(&mut self) -> THRESH_W<FCS_SPEC> {
         THRESH_W::new(self, 24)
     }
diff --git a/src/inner/adc/inte.rs b/src/inner/adc/inte.rs
index 4691dda..9da6929 100644
--- a/src/inner/adc/inte.rs
+++ b/src/inner/adc/inte.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo(&mut self) -> FIFO_W<INTE_SPEC> {
         FIFO_W::new(self, 0)
     }
diff --git a/src/inner/adc/intf.rs b/src/inner/adc/intf.rs
index 6296a0e..705db9f 100644
--- a/src/inner/adc/intf.rs
+++ b/src/inner/adc/intf.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."]
     #[inline(always)]
-    #[must_use]
     pub fn fifo(&mut self) -> FIFO_W<INTF_SPEC> {
         FIFO_W::new(self, 0)
     }
diff --git a/src/inner/adc/ints.rs b/src/inner/adc/ints.rs
index 11a49b4..1148f93 100644
--- a/src/inner/adc/ints.rs
+++ b/src/inner/adc/ints.rs
@@ -12,7 +12,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/bootram.rs b/src/inner/bootram.rs
index de40029..74f4509 100644
--- a/src/inner/bootram.rs
+++ b/src/inner/bootram.rs
@@ -30,42 +30,42 @@ impl RegisterBlock {
     pub const fn bootlock_stat(&self) -> &BOOTLOCK_STAT {
         &self.bootlock_stat
     }
-    #[doc = "0x80c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x80c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock0(&self) -> &BOOTLOCK0 {
         &self.bootlock0
     }
-    #[doc = "0x810 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x810 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock1(&self) -> &BOOTLOCK1 {
         &self.bootlock1
     }
-    #[doc = "0x814 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x814 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock2(&self) -> &BOOTLOCK2 {
         &self.bootlock2
     }
-    #[doc = "0x818 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x818 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock3(&self) -> &BOOTLOCK3 {
         &self.bootlock3
     }
-    #[doc = "0x81c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x81c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock4(&self) -> &BOOTLOCK4 {
         &self.bootlock4
     }
-    #[doc = "0x820 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x820 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock5(&self) -> &BOOTLOCK5 {
         &self.bootlock5
     }
-    #[doc = "0x824 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x824 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock6(&self) -> &BOOTLOCK6 {
         &self.bootlock6
     }
-    #[doc = "0x828 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+    #[doc = "0x828 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
     #[inline(always)]
     pub const fn bootlock7(&self) -> &BOOTLOCK7 {
         &self.bootlock7
@@ -98,75 +98,75 @@ module"]
 pub type BOOTLOCK_STAT = crate::Reg<bootlock_stat::BOOTLOCK_STAT_SPEC>;
 #[doc = "Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use."]
 pub mod bootlock_stat;
-#[doc = "BOOTLOCK0 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK0 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock0`]
 module"]
 pub type BOOTLOCK0 = crate::Reg<bootlock0::BOOTLOCK0_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock0;
-#[doc = "BOOTLOCK1 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK1 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock1`]
 module"]
 pub type BOOTLOCK1 = crate::Reg<bootlock1::BOOTLOCK1_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock1;
-#[doc = "BOOTLOCK2 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK2 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock2`]
 module"]
 pub type BOOTLOCK2 = crate::Reg<bootlock2::BOOTLOCK2_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock2;
-#[doc = "BOOTLOCK3 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK3 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock3`]
 module"]
 pub type BOOTLOCK3 = crate::Reg<bootlock3::BOOTLOCK3_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock3;
-#[doc = "BOOTLOCK4 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK4 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock4`]
 module"]
 pub type BOOTLOCK4 = crate::Reg<bootlock4::BOOTLOCK4_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock4;
-#[doc = "BOOTLOCK5 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK5 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock5`]
 module"]
 pub type BOOTLOCK5 = crate::Reg<bootlock5::BOOTLOCK5_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock5;
-#[doc = "BOOTLOCK6 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK6 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock6`]
 module"]
 pub type BOOTLOCK6 = crate::Reg<bootlock6::BOOTLOCK6_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock6;
-#[doc = "BOOTLOCK7 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "BOOTLOCK7 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@bootlock7`]
 module"]
 pub type BOOTLOCK7 = crate::Reg<bootlock7::BOOTLOCK7_SPEC>;
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero."]
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."]
 pub mod bootlock7;
diff --git a/src/inner/bootram/bootlock0.rs b/src/inner/bootram/bootlock0.rs
index 77a87fc..1e3e70a 100644
--- a/src/inner/bootram/bootlock0.rs
+++ b/src/inner/bootram/bootlock0.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock0(&mut self) -> BOOTLOCK0_W<BOOTLOCK0_SPEC> {
         BOOTLOCK0_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK0_SPEC;
diff --git a/src/inner/bootram/bootlock1.rs b/src/inner/bootram/bootlock1.rs
index 1e28778..0c5cbfb 100644
--- a/src/inner/bootram/bootlock1.rs
+++ b/src/inner/bootram/bootlock1.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock1(&mut self) -> BOOTLOCK1_W<BOOTLOCK1_SPEC> {
         BOOTLOCK1_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK1_SPEC;
diff --git a/src/inner/bootram/bootlock2.rs b/src/inner/bootram/bootlock2.rs
index cb8abab..85d0149 100644
--- a/src/inner/bootram/bootlock2.rs
+++ b/src/inner/bootram/bootlock2.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock2(&mut self) -> BOOTLOCK2_W<BOOTLOCK2_SPEC> {
         BOOTLOCK2_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK2_SPEC;
diff --git a/src/inner/bootram/bootlock3.rs b/src/inner/bootram/bootlock3.rs
index 262a574..8955296 100644
--- a/src/inner/bootram/bootlock3.rs
+++ b/src/inner/bootram/bootlock3.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock3(&mut self) -> BOOTLOCK3_W<BOOTLOCK3_SPEC> {
         BOOTLOCK3_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK3_SPEC;
diff --git a/src/inner/bootram/bootlock4.rs b/src/inner/bootram/bootlock4.rs
index 06ae0dc..e2815ee 100644
--- a/src/inner/bootram/bootlock4.rs
+++ b/src/inner/bootram/bootlock4.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock4(&mut self) -> BOOTLOCK4_W<BOOTLOCK4_SPEC> {
         BOOTLOCK4_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK4_SPEC;
diff --git a/src/inner/bootram/bootlock5.rs b/src/inner/bootram/bootlock5.rs
index 29475b8..e00c054 100644
--- a/src/inner/bootram/bootlock5.rs
+++ b/src/inner/bootram/bootlock5.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock5(&mut self) -> BOOTLOCK5_W<BOOTLOCK5_SPEC> {
         BOOTLOCK5_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK5_SPEC;
diff --git a/src/inner/bootram/bootlock6.rs b/src/inner/bootram/bootlock6.rs
index 4e05cc5..2fafa44 100644
--- a/src/inner/bootram/bootlock6.rs
+++ b/src/inner/bootram/bootlock6.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock6(&mut self) -> BOOTLOCK6_W<BOOTLOCK6_SPEC> {
         BOOTLOCK6_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK6_SPEC;
diff --git a/src/inner/bootram/bootlock7.rs b/src/inner/bootram/bootlock7.rs
index c07bd16..a0d50f0 100644
--- a/src/inner/bootram/bootlock7.rs
+++ b/src/inner/bootram/bootlock7.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock7(&mut self) -> BOOTLOCK7_W<BOOTLOCK7_SPEC> {
         BOOTLOCK7_W::new(self, 0)
     }
 }
-#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 &lt;&lt; n, and on failed claim is zero.  
+#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero.  
 
 You can [`read`](crate::Reg::read) this register and get [`bootlock7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct BOOTLOCK7_SPEC;
diff --git a/src/inner/bootram/bootlock_stat.rs b/src/inner/bootram/bootlock_stat.rs
index b7190c7..44d46ac 100644
--- a/src/inner/bootram/bootlock_stat.rs
+++ b/src/inner/bootram/bootlock_stat.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn bootlock_stat(&mut self) -> BOOTLOCK_STAT_W<BOOTLOCK_STAT_SPEC> {
         BOOTLOCK_STAT_W::new(self, 0)
     }
diff --git a/src/inner/bootram/write_once0.rs b/src/inner/bootram/write_once0.rs
index c2ad748..7ff446b 100644
--- a/src/inner/bootram/write_once0.rs
+++ b/src/inner/bootram/write_once0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn write_once0(&mut self) -> WRITE_ONCE0_W<WRITE_ONCE0_SPEC> {
         WRITE_ONCE0_W::new(self, 0)
     }
diff --git a/src/inner/bootram/write_once1.rs b/src/inner/bootram/write_once1.rs
index 33d521f..d3d3b2f 100644
--- a/src/inner/bootram/write_once1.rs
+++ b/src/inner/bootram/write_once1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn write_once1(&mut self) -> WRITE_ONCE1_W<WRITE_ONCE1_SPEC> {
         WRITE_ONCE1_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/bus_priority.rs b/src/inner/busctrl/bus_priority.rs
index d18f165..cf87676 100644
--- a/src/inner/busctrl/bus_priority.rs
+++ b/src/inner/busctrl/bus_priority.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - 0 - low priority, 1 - high priority"]
     #[inline(always)]
-    #[must_use]
     pub fn proc0(&mut self) -> PROC0_W<BUS_PRIORITY_SPEC> {
         PROC0_W::new(self, 0)
     }
     #[doc = "Bit 4 - 0 - low priority, 1 - high priority"]
     #[inline(always)]
-    #[must_use]
     pub fn proc1(&mut self) -> PROC1_W<BUS_PRIORITY_SPEC> {
         PROC1_W::new(self, 4)
     }
     #[doc = "Bit 8 - 0 - low priority, 1 - high priority"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_r(&mut self) -> DMA_R_W<BUS_PRIORITY_SPEC> {
         DMA_R_W::new(self, 8)
     }
     #[doc = "Bit 12 - 0 - low priority, 1 - high priority"]
     #[inline(always)]
-    #[must_use]
     pub fn dma_w(&mut self) -> DMA_W_W<BUS_PRIORITY_SPEC> {
         DMA_W_W::new(self, 12)
     }
diff --git a/src/inner/busctrl/perfctr0.rs b/src/inner/busctrl/perfctr0.rs
index 5f6c224..f806d36 100644
--- a/src/inner/busctrl/perfctr0.rs
+++ b/src/inner/busctrl/perfctr0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL0"]
     #[inline(always)]
-    #[must_use]
     pub fn perfctr0(&mut self) -> PERFCTR0_W<PERFCTR0_SPEC> {
         PERFCTR0_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfctr1.rs b/src/inner/busctrl/perfctr1.rs
index 75c7ee0..d9ed9b2 100644
--- a/src/inner/busctrl/perfctr1.rs
+++ b/src/inner/busctrl/perfctr1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"]
     #[inline(always)]
-    #[must_use]
     pub fn perfctr1(&mut self) -> PERFCTR1_W<PERFCTR1_SPEC> {
         PERFCTR1_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfctr2.rs b/src/inner/busctrl/perfctr2.rs
index f487b53..f4ad1ee 100644
--- a/src/inner/busctrl/perfctr2.rs
+++ b/src/inner/busctrl/perfctr2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"]
     #[inline(always)]
-    #[must_use]
     pub fn perfctr2(&mut self) -> PERFCTR2_W<PERFCTR2_SPEC> {
         PERFCTR2_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfctr3.rs b/src/inner/busctrl/perfctr3.rs
index b8fbe85..b88ec85 100644
--- a/src/inner/busctrl/perfctr3.rs
+++ b/src/inner/busctrl/perfctr3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"]
     #[inline(always)]
-    #[must_use]
     pub fn perfctr3(&mut self) -> PERFCTR3_W<PERFCTR3_SPEC> {
         PERFCTR3_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfctr_en.rs b/src/inner/busctrl/perfctr_en.rs
index 562179b..dcfdbe3 100644
--- a/src/inner/busctrl/perfctr_en.rs
+++ b/src/inner/busctrl/perfctr_en.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn perfctr_en(&mut self) -> PERFCTR_EN_W<PERFCTR_EN_SPEC> {
         PERFCTR_EN_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfsel0.rs b/src/inner/busctrl/perfsel0.rs
index f2ec053..2572ef2 100644
--- a/src/inner/busctrl/perfsel0.rs
+++ b/src/inner/busctrl/perfsel0.rs
@@ -932,7 +932,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."]
     #[inline(always)]
-    #[must_use]
     pub fn perfsel0(&mut self) -> PERFSEL0_W<PERFSEL0_SPEC> {
         PERFSEL0_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfsel1.rs b/src/inner/busctrl/perfsel1.rs
index be789c9..3443e33 100644
--- a/src/inner/busctrl/perfsel1.rs
+++ b/src/inner/busctrl/perfsel1.rs
@@ -932,7 +932,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."]
     #[inline(always)]
-    #[must_use]
     pub fn perfsel1(&mut self) -> PERFSEL1_W<PERFSEL1_SPEC> {
         PERFSEL1_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfsel2.rs b/src/inner/busctrl/perfsel2.rs
index 354c566..642600b 100644
--- a/src/inner/busctrl/perfsel2.rs
+++ b/src/inner/busctrl/perfsel2.rs
@@ -932,7 +932,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."]
     #[inline(always)]
-    #[must_use]
     pub fn perfsel2(&mut self) -> PERFSEL2_W<PERFSEL2_SPEC> {
         PERFSEL2_W::new(self, 0)
     }
diff --git a/src/inner/busctrl/perfsel3.rs b/src/inner/busctrl/perfsel3.rs
index afb1fa2..583aee9 100644
--- a/src/inner/busctrl/perfsel3.rs
+++ b/src/inner/busctrl/perfsel3.rs
@@ -932,7 +932,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."]
     #[inline(always)]
-    #[must_use]
     pub fn perfsel3(&mut self) -> PERFSEL3_W<PERFSEL3_SPEC> {
         PERFSEL3_W::new(self, 0)
     }
diff --git a/src/inner/clocks.rs b/src/inner/clocks.rs
index 6bd34b5..478ba2c 100644
--- a/src/inner/clocks.rs
+++ b/src/inner/clocks.rs
@@ -316,7 +316,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0xd0 - Interrupt status after masking &amp; forcing"]
+    #[doc = "0xd0 - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -790,12 +790,12 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
diff --git a/src/inner/clocks/clk_adc_ctrl.rs b/src/inner/clocks/clk_adc_ctrl.rs
index 805b6cb..9de5e7f 100644
--- a/src/inner/clocks/clk_adc_ctrl.rs
+++ b/src/inner/clocks/clk_adc_ctrl.rs
@@ -169,31 +169,26 @@ impl R {
 impl W {
     #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_ADC_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_ADC_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_ADC_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_ADC_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_ADC_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_adc_div.rs b/src/inner/clocks/clk_adc_div.rs
index 8ad6a9b..7790aae 100644
--- a/src/inner/clocks/clk_adc_div.rs
+++ b/src/inner/clocks/clk_adc_div.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 16:19 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_ADC_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_gpout0_ctrl.rs b/src/inner/clocks/clk_gpout0_ctrl.rs
index 2cd020d..ac42411 100644
--- a/src/inner/clocks/clk_gpout0_ctrl.rs
+++ b/src/inner/clocks/clk_gpout0_ctrl.rs
@@ -295,37 +295,31 @@ impl R {
 impl W {
     #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_GPOUT0_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_GPOUT0_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_GPOUT0_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn dc50(&mut self) -> DC50_W<CLK_GPOUT0_CTRL_SPEC> {
         DC50_W::new(self, 12)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_GPOUT0_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_GPOUT0_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_gpout0_div.rs b/src/inner/clocks/clk_gpout0_div.rs
index d5a98a7..b9cd4e8 100644
--- a/src/inner/clocks/clk_gpout0_div.rs
+++ b/src/inner/clocks/clk_gpout0_div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<CLK_GPOUT0_DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_GPOUT0_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_gpout1_ctrl.rs b/src/inner/clocks/clk_gpout1_ctrl.rs
index ca3b14c..ac27565 100644
--- a/src/inner/clocks/clk_gpout1_ctrl.rs
+++ b/src/inner/clocks/clk_gpout1_ctrl.rs
@@ -295,37 +295,31 @@ impl R {
 impl W {
     #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_GPOUT1_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_GPOUT1_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_GPOUT1_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn dc50(&mut self) -> DC50_W<CLK_GPOUT1_CTRL_SPEC> {
         DC50_W::new(self, 12)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_GPOUT1_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_GPOUT1_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_gpout1_div.rs b/src/inner/clocks/clk_gpout1_div.rs
index cd25048..4ebe7a3 100644
--- a/src/inner/clocks/clk_gpout1_div.rs
+++ b/src/inner/clocks/clk_gpout1_div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<CLK_GPOUT1_DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_GPOUT1_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_gpout2_ctrl.rs b/src/inner/clocks/clk_gpout2_ctrl.rs
index 4c00195..62bd7a0 100644
--- a/src/inner/clocks/clk_gpout2_ctrl.rs
+++ b/src/inner/clocks/clk_gpout2_ctrl.rs
@@ -295,37 +295,31 @@ impl R {
 impl W {
     #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_GPOUT2_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_GPOUT2_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_GPOUT2_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn dc50(&mut self) -> DC50_W<CLK_GPOUT2_CTRL_SPEC> {
         DC50_W::new(self, 12)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_GPOUT2_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_GPOUT2_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_gpout2_div.rs b/src/inner/clocks/clk_gpout2_div.rs
index 6b3fce6..83e0fff 100644
--- a/src/inner/clocks/clk_gpout2_div.rs
+++ b/src/inner/clocks/clk_gpout2_div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<CLK_GPOUT2_DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_GPOUT2_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_gpout3_ctrl.rs b/src/inner/clocks/clk_gpout3_ctrl.rs
index 7f32aa4..857414c 100644
--- a/src/inner/clocks/clk_gpout3_ctrl.rs
+++ b/src/inner/clocks/clk_gpout3_ctrl.rs
@@ -295,37 +295,31 @@ impl R {
 impl W {
     #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_GPOUT3_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_GPOUT3_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_GPOUT3_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn dc50(&mut self) -> DC50_W<CLK_GPOUT3_CTRL_SPEC> {
         DC50_W::new(self, 12)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_GPOUT3_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_GPOUT3_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_gpout3_div.rs b/src/inner/clocks/clk_gpout3_div.rs
index a9c8512..b64a010 100644
--- a/src/inner/clocks/clk_gpout3_div.rs
+++ b/src/inner/clocks/clk_gpout3_div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<CLK_GPOUT3_DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_GPOUT3_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_hstx_ctrl.rs b/src/inner/clocks/clk_hstx_ctrl.rs
index bebbfba..469d7af 100644
--- a/src/inner/clocks/clk_hstx_ctrl.rs
+++ b/src/inner/clocks/clk_hstx_ctrl.rs
@@ -156,31 +156,26 @@ impl R {
 impl W {
     #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_HSTX_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_HSTX_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_HSTX_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_HSTX_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_HSTX_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_hstx_div.rs b/src/inner/clocks/clk_hstx_div.rs
index 7cacf8b..2503502 100644
--- a/src/inner/clocks/clk_hstx_div.rs
+++ b/src/inner/clocks/clk_hstx_div.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 16:17 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_HSTX_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_peri_ctrl.rs b/src/inner/clocks/clk_peri_ctrl.rs
index c4480b6..255812e 100644
--- a/src/inner/clocks/clk_peri_ctrl.rs
+++ b/src/inner/clocks/clk_peri_ctrl.rs
@@ -164,19 +164,16 @@ impl R {
 impl W {
     #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_PERI_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_PERI_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_PERI_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
diff --git a/src/inner/clocks/clk_peri_div.rs b/src/inner/clocks/clk_peri_div.rs
index 470e507..6a2671f 100644
--- a/src/inner/clocks/clk_peri_div.rs
+++ b/src/inner/clocks/clk_peri_div.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 16:17 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_PERI_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_ref_ctrl.rs b/src/inner/clocks/clk_ref_ctrl.rs
index da65ef4..f76e15d 100644
--- a/src/inner/clocks/clk_ref_ctrl.rs
+++ b/src/inner/clocks/clk_ref_ctrl.rs
@@ -193,13 +193,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn src(&mut self) -> SRC_W<CLK_REF_CTRL_SPEC> {
         SRC_W::new(self, 0)
     }
     #[doc = "Bits 5:6 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_REF_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
diff --git a/src/inner/clocks/clk_ref_div.rs b/src/inner/clocks/clk_ref_div.rs
index ba2bcfd..a4a1761 100644
--- a/src/inner/clocks/clk_ref_div.rs
+++ b/src/inner/clocks/clk_ref_div.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 16:23 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_REF_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_sys_ctrl.rs b/src/inner/clocks/clk_sys_ctrl.rs
index 07a9211..991e912 100644
--- a/src/inner/clocks/clk_sys_ctrl.rs
+++ b/src/inner/clocks/clk_sys_ctrl.rs
@@ -186,13 +186,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn src(&mut self) -> SRC_W<CLK_SYS_CTRL_SPEC> {
         SRC_W::new(self, 0)
     }
     #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_SYS_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
diff --git a/src/inner/clocks/clk_sys_div.rs b/src/inner/clocks/clk_sys_div.rs
index f5c162c..10fb3cd 100644
--- a/src/inner/clocks/clk_sys_div.rs
+++ b/src/inner/clocks/clk_sys_div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<CLK_SYS_DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_SYS_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_sys_resus_ctrl.rs b/src/inner/clocks/clk_sys_resus_ctrl.rs
index fb0a303..1968ec4 100644
--- a/src/inner/clocks/clk_sys_resus_ctrl.rs
+++ b/src/inner/clocks/clk_sys_resus_ctrl.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"]
     #[inline(always)]
-    #[must_use]
     pub fn timeout(&mut self) -> TIMEOUT_W<CLK_SYS_RESUS_CTRL_SPEC> {
         TIMEOUT_W::new(self, 0)
     }
     #[doc = "Bit 8 - Enable resus"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_SYS_RESUS_CTRL_SPEC> {
         ENABLE_W::new(self, 8)
     }
     #[doc = "Bit 12 - Force a resus, for test purposes only"]
     #[inline(always)]
-    #[must_use]
     pub fn frce(&mut self) -> FRCE_W<CLK_SYS_RESUS_CTRL_SPEC> {
         FRCE_W::new(self, 12)
     }
     #[doc = "Bit 16 - For clearing the resus after the fault that triggered it has been corrected"]
     #[inline(always)]
-    #[must_use]
     pub fn clear(&mut self) -> CLEAR_W<CLK_SYS_RESUS_CTRL_SPEC> {
         CLEAR_W::new(self, 16)
     }
diff --git a/src/inner/clocks/clk_usb_ctrl.rs b/src/inner/clocks/clk_usb_ctrl.rs
index 98086fa..9155e7d 100644
--- a/src/inner/clocks/clk_usb_ctrl.rs
+++ b/src/inner/clocks/clk_usb_ctrl.rs
@@ -169,31 +169,26 @@ impl R {
 impl W {
     #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"]
     #[inline(always)]
-    #[must_use]
     pub fn auxsrc(&mut self) -> AUXSRC_W<CLK_USB_CTRL_SPEC> {
         AUXSRC_W::new(self, 5)
     }
     #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"]
     #[inline(always)]
-    #[must_use]
     pub fn kill(&mut self) -> KILL_W<CLK_USB_CTRL_SPEC> {
         KILL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Starts and stops the clock generator cleanly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CLK_USB_CTRL_SPEC> {
         ENABLE_W::new(self, 11)
     }
     #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"]
     #[inline(always)]
-    #[must_use]
     pub fn phase(&mut self) -> PHASE_W<CLK_USB_CTRL_SPEC> {
         PHASE_W::new(self, 16)
     }
     #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"]
     #[inline(always)]
-    #[must_use]
     pub fn nudge(&mut self) -> NUDGE_W<CLK_USB_CTRL_SPEC> {
         NUDGE_W::new(self, 20)
     }
diff --git a/src/inner/clocks/clk_usb_div.rs b/src/inner/clocks/clk_usb_div.rs
index 16f83e1..fcf7beb 100644
--- a/src/inner/clocks/clk_usb_div.rs
+++ b/src/inner/clocks/clk_usb_div.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 16:19 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<CLK_USB_DIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/clocks/dftclk_lposc_ctrl.rs b/src/inner/clocks/dftclk_lposc_ctrl.rs
index c9523f0..a538715 100644
--- a/src/inner/clocks/dftclk_lposc_ctrl.rs
+++ b/src/inner/clocks/dftclk_lposc_ctrl.rs
@@ -87,7 +87,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn src(&mut self) -> SRC_W<DFTCLK_LPOSC_CTRL_SPEC> {
         SRC_W::new(self, 0)
     }
diff --git a/src/inner/clocks/dftclk_rosc_ctrl.rs b/src/inner/clocks/dftclk_rosc_ctrl.rs
index 083b141..2283a9b 100644
--- a/src/inner/clocks/dftclk_rosc_ctrl.rs
+++ b/src/inner/clocks/dftclk_rosc_ctrl.rs
@@ -87,7 +87,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn src(&mut self) -> SRC_W<DFTCLK_ROSC_CTRL_SPEC> {
         SRC_W::new(self, 0)
     }
diff --git a/src/inner/clocks/dftclk_xosc_ctrl.rs b/src/inner/clocks/dftclk_xosc_ctrl.rs
index 7db8f8d..3825149 100644
--- a/src/inner/clocks/dftclk_xosc_ctrl.rs
+++ b/src/inner/clocks/dftclk_xosc_ctrl.rs
@@ -87,7 +87,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn src(&mut self) -> SRC_W<DFTCLK_XOSC_CTRL_SPEC> {
         SRC_W::new(self, 0)
     }
diff --git a/src/inner/clocks/fc0_delay.rs b/src/inner/clocks/fc0_delay.rs
index d787ddd..bc28fa4 100644
--- a/src/inner/clocks/fc0_delay.rs
+++ b/src/inner/clocks/fc0_delay.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:2"]
     #[inline(always)]
-    #[must_use]
     pub fn fc0_delay(&mut self) -> FC0_DELAY_W<FC0_DELAY_SPEC> {
         FC0_DELAY_W::new(self, 0)
     }
diff --git a/src/inner/clocks/fc0_interval.rs b/src/inner/clocks/fc0_interval.rs
index ef7ad59..c29ff8c 100644
--- a/src/inner/clocks/fc0_interval.rs
+++ b/src/inner/clocks/fc0_interval.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn fc0_interval(&mut self) -> FC0_INTERVAL_W<FC0_INTERVAL_SPEC> {
         FC0_INTERVAL_W::new(self, 0)
     }
diff --git a/src/inner/clocks/fc0_max_khz.rs b/src/inner/clocks/fc0_max_khz.rs
index 73cb959..6992f34 100644
--- a/src/inner/clocks/fc0_max_khz.rs
+++ b/src/inner/clocks/fc0_max_khz.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:24"]
     #[inline(always)]
-    #[must_use]
     pub fn fc0_max_khz(&mut self) -> FC0_MAX_KHZ_W<FC0_MAX_KHZ_SPEC> {
         FC0_MAX_KHZ_W::new(self, 0)
     }
diff --git a/src/inner/clocks/fc0_min_khz.rs b/src/inner/clocks/fc0_min_khz.rs
index 55d4d49..8dea7bb 100644
--- a/src/inner/clocks/fc0_min_khz.rs
+++ b/src/inner/clocks/fc0_min_khz.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:24"]
     #[inline(always)]
-    #[must_use]
     pub fn fc0_min_khz(&mut self) -> FC0_MIN_KHZ_W<FC0_MIN_KHZ_SPEC> {
         FC0_MIN_KHZ_W::new(self, 0)
     }
diff --git a/src/inner/clocks/fc0_ref_khz.rs b/src/inner/clocks/fc0_ref_khz.rs
index 2390238..5f69ea0 100644
--- a/src/inner/clocks/fc0_ref_khz.rs
+++ b/src/inner/clocks/fc0_ref_khz.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn fc0_ref_khz(&mut self) -> FC0_REF_KHZ_W<FC0_REF_KHZ_SPEC> {
         FC0_REF_KHZ_W::new(self, 0)
     }
diff --git a/src/inner/clocks/fc0_src.rs b/src/inner/clocks/fc0_src.rs
index 324304f..83e1355 100644
--- a/src/inner/clocks/fc0_src.rs
+++ b/src/inner/clocks/fc0_src.rs
@@ -269,7 +269,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn fc0_src(&mut self) -> FC0_SRC_W<FC0_SRC_SPEC> {
         FC0_SRC_W::new(self, 0)
     }
diff --git a/src/inner/clocks/inte.rs b/src/inner/clocks/inte.rs
index 9338abd..f3de628 100644
--- a/src/inner/clocks/inte.rs
+++ b/src/inner/clocks/inte.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W<INTE_SPEC> {
         CLK_SYS_RESUS_W::new(self, 0)
     }
diff --git a/src/inner/clocks/intf.rs b/src/inner/clocks/intf.rs
index 662ebd8..18d717d 100644
--- a/src/inner/clocks/intf.rs
+++ b/src/inner/clocks/intf.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W<INTF_SPEC> {
         CLK_SYS_RESUS_W::new(self, 0)
     }
diff --git a/src/inner/clocks/ints.rs b/src/inner/clocks/ints.rs
index 3a6adbf..6ebced1 100644
--- a/src/inner/clocks/ints.rs
+++ b/src/inner/clocks/ints.rs
@@ -12,7 +12,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/clocks/sleep_en0.rs b/src/inner/clocks/sleep_en0.rs
index af11094..36aab83 100644
--- a/src/inner/clocks/sleep_en0.rs
+++ b/src/inner/clocks/sleep_en0.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<SLEEP_EN0_SPEC> {
         CLK_SYS_CLOCKS_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_accessctrl(&mut self) -> CLK_SYS_ACCESSCTRL_W<SLEEP_EN0_SPEC> {
         CLK_SYS_ACCESSCTRL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_adc(&mut self) -> CLK_ADC_W<SLEEP_EN0_SPEC> {
         CLK_ADC_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<SLEEP_EN0_SPEC> {
         CLK_SYS_ADC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_bootram(&mut self) -> CLK_SYS_BOOTRAM_W<SLEEP_EN0_SPEC> {
         CLK_SYS_BOOTRAM_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<SLEEP_EN0_SPEC> {
         CLK_SYS_BUSCTRL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<SLEEP_EN0_SPEC> {
         CLK_SYS_BUSFABRIC_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<SLEEP_EN0_SPEC> {
         CLK_SYS_DMA_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_glitch_detector(&mut self) -> CLK_SYS_GLITCH_DETECTOR_W<SLEEP_EN0_SPEC> {
         CLK_SYS_GLITCH_DETECTOR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_hstx(&mut self) -> CLK_HSTX_W<SLEEP_EN0_SPEC> {
         CLK_HSTX_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_hstx(&mut self) -> CLK_SYS_HSTX_W<SLEEP_EN0_SPEC> {
         CLK_SYS_HSTX_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<SLEEP_EN0_SPEC> {
         CLK_SYS_I2C0_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<SLEEP_EN0_SPEC> {
         CLK_SYS_I2C1_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<SLEEP_EN0_SPEC> {
         CLK_SYS_IO_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<SLEEP_EN0_SPEC> {
         CLK_SYS_JTAG_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_ref_otp(&mut self) -> CLK_REF_OTP_W<SLEEP_EN0_SPEC> {
         CLK_REF_OTP_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_otp(&mut self) -> CLK_SYS_OTP_W<SLEEP_EN0_SPEC> {
         CLK_SYS_OTP_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PADS_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PIO0_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PIO1_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pio2(&mut self) -> CLK_SYS_PIO2_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PIO2_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PLL_SYS_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PLL_USB_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_ref_powman(&mut self) -> CLK_REF_POWMAN_W<SLEEP_EN0_SPEC> {
         CLK_REF_POWMAN_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_powman(&mut self) -> CLK_SYS_POWMAN_W<SLEEP_EN0_SPEC> {
         CLK_SYS_POWMAN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PWM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<SLEEP_EN0_SPEC> {
         CLK_SYS_RESETS_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<SLEEP_EN0_SPEC> {
         CLK_SYS_ROM_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<SLEEP_EN0_SPEC> {
         CLK_SYS_ROSC_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<SLEEP_EN0_SPEC> {
         CLK_SYS_PSM_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sha256(&mut self) -> CLK_SYS_SHA256_W<SLEEP_EN0_SPEC> {
         CLK_SYS_SHA256_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<SLEEP_EN0_SPEC> {
         CLK_SYS_SIO_W::new(self, 31)
     }
diff --git a/src/inner/clocks/sleep_en1.rs b/src/inner/clocks/sleep_en1.rs
index 6069492..ac40849 100644
--- a/src/inner/clocks/sleep_en1.rs
+++ b/src/inner/clocks/sleep_en1.rs
@@ -286,187 +286,156 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<SLEEP_EN1_SPEC> {
         CLK_PERI_SPI0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SPI0_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<SLEEP_EN1_SPEC> {
         CLK_PERI_SPI1_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SPI1_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM2_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM3_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM4_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM5_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram6(&mut self) -> CLK_SYS_SRAM6_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM6_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram7(&mut self) -> CLK_SYS_SRAM7_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM7_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram8(&mut self) -> CLK_SYS_SRAM8_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM8_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram9(&mut self) -> CLK_SYS_SRAM9_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SRAM9_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SYSCFG_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<SLEEP_EN1_SPEC> {
         CLK_SYS_SYSINFO_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<SLEEP_EN1_SPEC> {
         CLK_SYS_TBMAN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_ref_ticks(&mut self) -> CLK_REF_TICKS_W<SLEEP_EN1_SPEC> {
         CLK_REF_TICKS_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_ticks(&mut self) -> CLK_SYS_TICKS_W<SLEEP_EN1_SPEC> {
         CLK_SYS_TICKS_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_timer0(&mut self) -> CLK_SYS_TIMER0_W<SLEEP_EN1_SPEC> {
         CLK_SYS_TIMER0_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_timer1(&mut self) -> CLK_SYS_TIMER1_W<SLEEP_EN1_SPEC> {
         CLK_SYS_TIMER1_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_trng(&mut self) -> CLK_SYS_TRNG_W<SLEEP_EN1_SPEC> {
         CLK_SYS_TRNG_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<SLEEP_EN1_SPEC> {
         CLK_PERI_UART0_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<SLEEP_EN1_SPEC> {
         CLK_SYS_UART0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<SLEEP_EN1_SPEC> {
         CLK_PERI_UART1_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<SLEEP_EN1_SPEC> {
         CLK_SYS_UART1_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<SLEEP_EN1_SPEC> {
         CLK_SYS_USBCTRL_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_usb(&mut self) -> CLK_USB_W<SLEEP_EN1_SPEC> {
         CLK_USB_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<SLEEP_EN1_SPEC> {
         CLK_SYS_WATCHDOG_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<SLEEP_EN1_SPEC> {
         CLK_SYS_XIP_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<SLEEP_EN1_SPEC> {
         CLK_SYS_XOSC_W::new(self, 30)
     }
diff --git a/src/inner/clocks/wake_en0.rs b/src/inner/clocks/wake_en0.rs
index ed197bf..1bb9075 100644
--- a/src/inner/clocks/wake_en0.rs
+++ b/src/inner/clocks/wake_en0.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W<WAKE_EN0_SPEC> {
         CLK_SYS_CLOCKS_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_accessctrl(&mut self) -> CLK_SYS_ACCESSCTRL_W<WAKE_EN0_SPEC> {
         CLK_SYS_ACCESSCTRL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_adc(&mut self) -> CLK_ADC_W<WAKE_EN0_SPEC> {
         CLK_ADC_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W<WAKE_EN0_SPEC> {
         CLK_SYS_ADC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_bootram(&mut self) -> CLK_SYS_BOOTRAM_W<WAKE_EN0_SPEC> {
         CLK_SYS_BOOTRAM_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W<WAKE_EN0_SPEC> {
         CLK_SYS_BUSCTRL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W<WAKE_EN0_SPEC> {
         CLK_SYS_BUSFABRIC_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W<WAKE_EN0_SPEC> {
         CLK_SYS_DMA_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_glitch_detector(&mut self) -> CLK_SYS_GLITCH_DETECTOR_W<WAKE_EN0_SPEC> {
         CLK_SYS_GLITCH_DETECTOR_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_hstx(&mut self) -> CLK_HSTX_W<WAKE_EN0_SPEC> {
         CLK_HSTX_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_hstx(&mut self) -> CLK_SYS_HSTX_W<WAKE_EN0_SPEC> {
         CLK_SYS_HSTX_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W<WAKE_EN0_SPEC> {
         CLK_SYS_I2C0_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W<WAKE_EN0_SPEC> {
         CLK_SYS_I2C1_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W<WAKE_EN0_SPEC> {
         CLK_SYS_IO_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W<WAKE_EN0_SPEC> {
         CLK_SYS_JTAG_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_ref_otp(&mut self) -> CLK_REF_OTP_W<WAKE_EN0_SPEC> {
         CLK_REF_OTP_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_otp(&mut self) -> CLK_SYS_OTP_W<WAKE_EN0_SPEC> {
         CLK_SYS_OTP_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W<WAKE_EN0_SPEC> {
         CLK_SYS_PADS_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W<WAKE_EN0_SPEC> {
         CLK_SYS_PIO0_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W<WAKE_EN0_SPEC> {
         CLK_SYS_PIO1_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pio2(&mut self) -> CLK_SYS_PIO2_W<WAKE_EN0_SPEC> {
         CLK_SYS_PIO2_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W<WAKE_EN0_SPEC> {
         CLK_SYS_PLL_SYS_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W<WAKE_EN0_SPEC> {
         CLK_SYS_PLL_USB_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_ref_powman(&mut self) -> CLK_REF_POWMAN_W<WAKE_EN0_SPEC> {
         CLK_REF_POWMAN_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_powman(&mut self) -> CLK_SYS_POWMAN_W<WAKE_EN0_SPEC> {
         CLK_SYS_POWMAN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W<WAKE_EN0_SPEC> {
         CLK_SYS_PWM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W<WAKE_EN0_SPEC> {
         CLK_SYS_RESETS_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W<WAKE_EN0_SPEC> {
         CLK_SYS_ROM_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W<WAKE_EN0_SPEC> {
         CLK_SYS_ROSC_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W<WAKE_EN0_SPEC> {
         CLK_SYS_PSM_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sha256(&mut self) -> CLK_SYS_SHA256_W<WAKE_EN0_SPEC> {
         CLK_SYS_SHA256_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W<WAKE_EN0_SPEC> {
         CLK_SYS_SIO_W::new(self, 31)
     }
diff --git a/src/inner/clocks/wake_en1.rs b/src/inner/clocks/wake_en1.rs
index 71bb712..57d1a9f 100644
--- a/src/inner/clocks/wake_en1.rs
+++ b/src/inner/clocks/wake_en1.rs
@@ -286,187 +286,156 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W<WAKE_EN1_SPEC> {
         CLK_PERI_SPI0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W<WAKE_EN1_SPEC> {
         CLK_SYS_SPI0_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W<WAKE_EN1_SPEC> {
         CLK_PERI_SPI1_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W<WAKE_EN1_SPEC> {
         CLK_SYS_SPI1_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM2_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM3_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM4_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM5_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram6(&mut self) -> CLK_SYS_SRAM6_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM6_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram7(&mut self) -> CLK_SYS_SRAM7_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM7_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram8(&mut self) -> CLK_SYS_SRAM8_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM8_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sram9(&mut self) -> CLK_SYS_SRAM9_W<WAKE_EN1_SPEC> {
         CLK_SYS_SRAM9_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W<WAKE_EN1_SPEC> {
         CLK_SYS_SYSCFG_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W<WAKE_EN1_SPEC> {
         CLK_SYS_SYSINFO_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W<WAKE_EN1_SPEC> {
         CLK_SYS_TBMAN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_ref_ticks(&mut self) -> CLK_REF_TICKS_W<WAKE_EN1_SPEC> {
         CLK_REF_TICKS_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_ticks(&mut self) -> CLK_SYS_TICKS_W<WAKE_EN1_SPEC> {
         CLK_SYS_TICKS_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_timer0(&mut self) -> CLK_SYS_TIMER0_W<WAKE_EN1_SPEC> {
         CLK_SYS_TIMER0_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_timer1(&mut self) -> CLK_SYS_TIMER1_W<WAKE_EN1_SPEC> {
         CLK_SYS_TIMER1_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_trng(&mut self) -> CLK_SYS_TRNG_W<WAKE_EN1_SPEC> {
         CLK_SYS_TRNG_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W<WAKE_EN1_SPEC> {
         CLK_PERI_UART0_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W<WAKE_EN1_SPEC> {
         CLK_SYS_UART0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W<WAKE_EN1_SPEC> {
         CLK_PERI_UART1_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W<WAKE_EN1_SPEC> {
         CLK_SYS_UART1_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W<WAKE_EN1_SPEC> {
         CLK_SYS_USBCTRL_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_usb(&mut self) -> CLK_USB_W<WAKE_EN1_SPEC> {
         CLK_USB_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W<WAKE_EN1_SPEC> {
         CLK_SYS_WATCHDOG_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W<WAKE_EN1_SPEC> {
         CLK_SYS_XIP_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W<WAKE_EN1_SPEC> {
         CLK_SYS_XOSC_W::new(self, 30)
     }
diff --git a/src/inner/coresight_trace/ctrl_status.rs b/src/inner/coresight_trace/ctrl_status.rs
index a87941c..058b5fd 100644
--- a/src/inner/coresight_trace/ctrl_status.rs
+++ b/src/inner/coresight_trace/ctrl_status.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."]
     #[inline(always)]
-    #[must_use]
     pub fn trace_capture_fifo_flush(&mut self) -> TRACE_CAPTURE_FIFO_FLUSH_W<CTRL_STATUS_SPEC> {
         TRACE_CAPTURE_FIFO_FLUSH_W::new(self, 0)
     }
     #[doc = "Bit 1 - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."]
     #[inline(always)]
-    #[must_use]
     pub fn trace_capture_fifo_overflow(
         &mut self,
     ) -> TRACE_CAPTURE_FIFO_OVERFLOW_W<CTRL_STATUS_SPEC> {
diff --git a/src/inner/dma/ch/ch_al1_ctrl.rs b/src/inner/dma/ch/ch_al1_ctrl.rs
index 419b577..d8a9aee 100644
--- a/src/inner/dma/ch/ch_al1_ctrl.rs
+++ b/src/inner/dma/ch/ch_al1_ctrl.rs
@@ -101,7 +101,7 @@ pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type INCR_WRITE_REV_R = crate::BitReader;
 #[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
 pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
+#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -120,7 +120,7 @@ impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for RING_SIZE_A {}
-#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_R = crate::FieldReader<RING_SIZE_A>;
 impl RING_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -137,7 +137,7 @@ impl RING_SIZE_R {
         *self == RING_SIZE_A::RING_NONE
     }
 }
-#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>;
 impl<'a, REG> RING_SIZE_W<'a, REG>
 where
@@ -150,9 +150,9 @@ where
         self.variant(RING_SIZE_A::RING_NONE)
     }
 }
-#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_R = crate::BitReader;
-#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
@@ -1036,12 +1036,12 @@ impl R {
     pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R {
         INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
     pub fn ring_size(&self) -> RING_SIZE_R {
         RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
     pub fn ring_sel(&self) -> RING_SEL_R {
         RING_SEL_R::new(((self.bits >> 12) & 1) != 0)
@@ -1096,98 +1096,82 @@ impl R {
 impl W {
     #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CH_AL1_CTRL_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
     #[inline(always)]
-    #[must_use]
     pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<CH_AL1_CTRL_SPEC> {
         HIGH_PRIORITY_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn data_size(&mut self) -> DATA_SIZE_W<CH_AL1_CTRL_SPEC> {
         DATA_SIZE_W::new(self, 2)
     }
     #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read(&mut self) -> INCR_READ_W<CH_AL1_CTRL_SPEC> {
         INCR_READ_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W<CH_AL1_CTRL_SPEC> {
         INCR_READ_REV_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write(&mut self) -> INCR_WRITE_W<CH_AL1_CTRL_SPEC> {
         INCR_WRITE_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W<CH_AL1_CTRL_SPEC> {
         INCR_WRITE_REV_W::new(self, 7)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_size(&mut self) -> RING_SIZE_W<CH_AL1_CTRL_SPEC> {
         RING_SIZE_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_sel(&mut self) -> RING_SEL_W<CH_AL1_CTRL_SPEC> {
         RING_SEL_W::new(self, 12)
     }
     #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
     #[inline(always)]
-    #[must_use]
     pub fn chain_to(&mut self) -> CHAIN_TO_W<CH_AL1_CTRL_SPEC> {
         CHAIN_TO_W::new(self, 13)
     }
     #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn treq_sel(&mut self) -> TREQ_SEL_W<CH_AL1_CTRL_SPEC> {
         TREQ_SEL_W::new(self, 17)
     }
     #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<CH_AL1_CTRL_SPEC> {
         IRQ_QUIET_W::new(self, 23)
     }
     #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
     #[inline(always)]
-    #[must_use]
     pub fn bswap(&mut self) -> BSWAP_W<CH_AL1_CTRL_SPEC> {
         BSWAP_W::new(self, 24)
     }
     #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_en(&mut self) -> SNIFF_EN_W<CH_AL1_CTRL_SPEC> {
         SNIFF_EN_W::new(self, 25)
     }
     #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn write_error(&mut self) -> WRITE_ERROR_W<CH_AL1_CTRL_SPEC> {
         WRITE_ERROR_W::new(self, 29)
     }
     #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn read_error(&mut self) -> READ_ERROR_W<CH_AL1_CTRL_SPEC> {
         READ_ERROR_W::new(self, 30)
     }
diff --git a/src/inner/dma/ch/ch_al1_read_addr.rs b/src/inner/dma/ch/ch_al1_read_addr.rs
index 01a06a3..6009d37 100644
--- a/src/inner/dma/ch/ch_al1_read_addr.rs
+++ b/src/inner/dma/ch/ch_al1_read_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al1_read_addr(&mut self) -> CH0_AL1_READ_ADDR_W<CH_AL1_READ_ADDR_SPEC> {
         CH0_AL1_READ_ADDR_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_al1_trans_count_trig.rs b/src/inner/dma/ch/ch_al1_trans_count_trig.rs
index 7d59da5..c9ba39b 100644
--- a/src/inner/dma/ch/ch_al1_trans_count_trig.rs
+++ b/src/inner/dma/ch/ch_al1_trans_count_trig.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al1_trans_count_trig(
         &mut self,
     ) -> CH0_AL1_TRANS_COUNT_TRIG_W<CH_AL1_TRANS_COUNT_TRIG_SPEC> {
diff --git a/src/inner/dma/ch/ch_al1_write_addr.rs b/src/inner/dma/ch/ch_al1_write_addr.rs
index 44dc491..b8788c6 100644
--- a/src/inner/dma/ch/ch_al1_write_addr.rs
+++ b/src/inner/dma/ch/ch_al1_write_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al1_write_addr(&mut self) -> CH0_AL1_WRITE_ADDR_W<CH_AL1_WRITE_ADDR_SPEC> {
         CH0_AL1_WRITE_ADDR_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_al2_ctrl.rs b/src/inner/dma/ch/ch_al2_ctrl.rs
index e14357d..df18476 100644
--- a/src/inner/dma/ch/ch_al2_ctrl.rs
+++ b/src/inner/dma/ch/ch_al2_ctrl.rs
@@ -101,7 +101,7 @@ pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type INCR_WRITE_REV_R = crate::BitReader;
 #[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
 pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
+#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -120,7 +120,7 @@ impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for RING_SIZE_A {}
-#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_R = crate::FieldReader<RING_SIZE_A>;
 impl RING_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -137,7 +137,7 @@ impl RING_SIZE_R {
         *self == RING_SIZE_A::RING_NONE
     }
 }
-#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>;
 impl<'a, REG> RING_SIZE_W<'a, REG>
 where
@@ -150,9 +150,9 @@ where
         self.variant(RING_SIZE_A::RING_NONE)
     }
 }
-#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_R = crate::BitReader;
-#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
@@ -1036,12 +1036,12 @@ impl R {
     pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R {
         INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
     pub fn ring_size(&self) -> RING_SIZE_R {
         RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
     pub fn ring_sel(&self) -> RING_SEL_R {
         RING_SEL_R::new(((self.bits >> 12) & 1) != 0)
@@ -1096,98 +1096,82 @@ impl R {
 impl W {
     #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CH_AL2_CTRL_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
     #[inline(always)]
-    #[must_use]
     pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<CH_AL2_CTRL_SPEC> {
         HIGH_PRIORITY_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn data_size(&mut self) -> DATA_SIZE_W<CH_AL2_CTRL_SPEC> {
         DATA_SIZE_W::new(self, 2)
     }
     #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read(&mut self) -> INCR_READ_W<CH_AL2_CTRL_SPEC> {
         INCR_READ_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W<CH_AL2_CTRL_SPEC> {
         INCR_READ_REV_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write(&mut self) -> INCR_WRITE_W<CH_AL2_CTRL_SPEC> {
         INCR_WRITE_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W<CH_AL2_CTRL_SPEC> {
         INCR_WRITE_REV_W::new(self, 7)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_size(&mut self) -> RING_SIZE_W<CH_AL2_CTRL_SPEC> {
         RING_SIZE_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_sel(&mut self) -> RING_SEL_W<CH_AL2_CTRL_SPEC> {
         RING_SEL_W::new(self, 12)
     }
     #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
     #[inline(always)]
-    #[must_use]
     pub fn chain_to(&mut self) -> CHAIN_TO_W<CH_AL2_CTRL_SPEC> {
         CHAIN_TO_W::new(self, 13)
     }
     #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn treq_sel(&mut self) -> TREQ_SEL_W<CH_AL2_CTRL_SPEC> {
         TREQ_SEL_W::new(self, 17)
     }
     #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<CH_AL2_CTRL_SPEC> {
         IRQ_QUIET_W::new(self, 23)
     }
     #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
     #[inline(always)]
-    #[must_use]
     pub fn bswap(&mut self) -> BSWAP_W<CH_AL2_CTRL_SPEC> {
         BSWAP_W::new(self, 24)
     }
     #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_en(&mut self) -> SNIFF_EN_W<CH_AL2_CTRL_SPEC> {
         SNIFF_EN_W::new(self, 25)
     }
     #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn write_error(&mut self) -> WRITE_ERROR_W<CH_AL2_CTRL_SPEC> {
         WRITE_ERROR_W::new(self, 29)
     }
     #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn read_error(&mut self) -> READ_ERROR_W<CH_AL2_CTRL_SPEC> {
         READ_ERROR_W::new(self, 30)
     }
diff --git a/src/inner/dma/ch/ch_al2_read_addr.rs b/src/inner/dma/ch/ch_al2_read_addr.rs
index 91cbafd..a4da6b0 100644
--- a/src/inner/dma/ch/ch_al2_read_addr.rs
+++ b/src/inner/dma/ch/ch_al2_read_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al2_read_addr(&mut self) -> CH0_AL2_READ_ADDR_W<CH_AL2_READ_ADDR_SPEC> {
         CH0_AL2_READ_ADDR_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_al2_trans_count.rs b/src/inner/dma/ch/ch_al2_trans_count.rs
index e1a4d0f..7075833 100644
--- a/src/inner/dma/ch/ch_al2_trans_count.rs
+++ b/src/inner/dma/ch/ch_al2_trans_count.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al2_trans_count(&mut self) -> CH0_AL2_TRANS_COUNT_W<CH_AL2_TRANS_COUNT_SPEC> {
         CH0_AL2_TRANS_COUNT_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_al2_write_addr_trig.rs b/src/inner/dma/ch/ch_al2_write_addr_trig.rs
index c50411c..7fe73a3 100644
--- a/src/inner/dma/ch/ch_al2_write_addr_trig.rs
+++ b/src/inner/dma/ch/ch_al2_write_addr_trig.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al2_write_addr_trig(
         &mut self,
     ) -> CH0_AL2_WRITE_ADDR_TRIG_W<CH_AL2_WRITE_ADDR_TRIG_SPEC> {
diff --git a/src/inner/dma/ch/ch_al3_ctrl.rs b/src/inner/dma/ch/ch_al3_ctrl.rs
index c84fdb9..75718dc 100644
--- a/src/inner/dma/ch/ch_al3_ctrl.rs
+++ b/src/inner/dma/ch/ch_al3_ctrl.rs
@@ -101,7 +101,7 @@ pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type INCR_WRITE_REV_R = crate::BitReader;
 #[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
 pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
+#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -120,7 +120,7 @@ impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for RING_SIZE_A {}
-#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_R = crate::FieldReader<RING_SIZE_A>;
 impl RING_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -137,7 +137,7 @@ impl RING_SIZE_R {
         *self == RING_SIZE_A::RING_NONE
     }
 }
-#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>;
 impl<'a, REG> RING_SIZE_W<'a, REG>
 where
@@ -150,9 +150,9 @@ where
         self.variant(RING_SIZE_A::RING_NONE)
     }
 }
-#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_R = crate::BitReader;
-#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
@@ -1036,12 +1036,12 @@ impl R {
     pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R {
         INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
     pub fn ring_size(&self) -> RING_SIZE_R {
         RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
     pub fn ring_sel(&self) -> RING_SEL_R {
         RING_SEL_R::new(((self.bits >> 12) & 1) != 0)
@@ -1096,98 +1096,82 @@ impl R {
 impl W {
     #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CH_AL3_CTRL_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
     #[inline(always)]
-    #[must_use]
     pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<CH_AL3_CTRL_SPEC> {
         HIGH_PRIORITY_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn data_size(&mut self) -> DATA_SIZE_W<CH_AL3_CTRL_SPEC> {
         DATA_SIZE_W::new(self, 2)
     }
     #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read(&mut self) -> INCR_READ_W<CH_AL3_CTRL_SPEC> {
         INCR_READ_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W<CH_AL3_CTRL_SPEC> {
         INCR_READ_REV_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write(&mut self) -> INCR_WRITE_W<CH_AL3_CTRL_SPEC> {
         INCR_WRITE_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W<CH_AL3_CTRL_SPEC> {
         INCR_WRITE_REV_W::new(self, 7)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_size(&mut self) -> RING_SIZE_W<CH_AL3_CTRL_SPEC> {
         RING_SIZE_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_sel(&mut self) -> RING_SEL_W<CH_AL3_CTRL_SPEC> {
         RING_SEL_W::new(self, 12)
     }
     #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
     #[inline(always)]
-    #[must_use]
     pub fn chain_to(&mut self) -> CHAIN_TO_W<CH_AL3_CTRL_SPEC> {
         CHAIN_TO_W::new(self, 13)
     }
     #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn treq_sel(&mut self) -> TREQ_SEL_W<CH_AL3_CTRL_SPEC> {
         TREQ_SEL_W::new(self, 17)
     }
     #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<CH_AL3_CTRL_SPEC> {
         IRQ_QUIET_W::new(self, 23)
     }
     #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
     #[inline(always)]
-    #[must_use]
     pub fn bswap(&mut self) -> BSWAP_W<CH_AL3_CTRL_SPEC> {
         BSWAP_W::new(self, 24)
     }
     #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_en(&mut self) -> SNIFF_EN_W<CH_AL3_CTRL_SPEC> {
         SNIFF_EN_W::new(self, 25)
     }
     #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn write_error(&mut self) -> WRITE_ERROR_W<CH_AL3_CTRL_SPEC> {
         WRITE_ERROR_W::new(self, 29)
     }
     #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn read_error(&mut self) -> READ_ERROR_W<CH_AL3_CTRL_SPEC> {
         READ_ERROR_W::new(self, 30)
     }
diff --git a/src/inner/dma/ch/ch_al3_read_addr_trig.rs b/src/inner/dma/ch/ch_al3_read_addr_trig.rs
index fead2d2..e51968e 100644
--- a/src/inner/dma/ch/ch_al3_read_addr_trig.rs
+++ b/src/inner/dma/ch/ch_al3_read_addr_trig.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al3_read_addr_trig(
         &mut self,
     ) -> CH0_AL3_READ_ADDR_TRIG_W<CH_AL3_READ_ADDR_TRIG_SPEC> {
diff --git a/src/inner/dma/ch/ch_al3_trans_count.rs b/src/inner/dma/ch/ch_al3_trans_count.rs
index 044d8e7..2ee73e0 100644
--- a/src/inner/dma/ch/ch_al3_trans_count.rs
+++ b/src/inner/dma/ch/ch_al3_trans_count.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al3_trans_count(&mut self) -> CH0_AL3_TRANS_COUNT_W<CH_AL3_TRANS_COUNT_SPEC> {
         CH0_AL3_TRANS_COUNT_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_al3_write_addr.rs b/src/inner/dma/ch/ch_al3_write_addr.rs
index 6b0a773..4706298 100644
--- a/src/inner/dma/ch/ch_al3_write_addr.rs
+++ b/src/inner/dma/ch/ch_al3_write_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_al3_write_addr(&mut self) -> CH0_AL3_WRITE_ADDR_W<CH_AL3_WRITE_ADDR_SPEC> {
         CH0_AL3_WRITE_ADDR_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_ctrl_trig.rs b/src/inner/dma/ch/ch_ctrl_trig.rs
index 3c2c51a..d5fe179 100644
--- a/src/inner/dma/ch/ch_ctrl_trig.rs
+++ b/src/inner/dma/ch/ch_ctrl_trig.rs
@@ -101,7 +101,7 @@ pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
 pub type INCR_WRITE_REV_R = crate::BitReader;
 #[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
 pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
+#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -120,7 +120,7 @@ impl crate::FieldSpec for RING_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for RING_SIZE_A {}
-#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_R = crate::FieldReader<RING_SIZE_A>;
 impl RING_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -137,7 +137,7 @@ impl RING_SIZE_R {
         *self == RING_SIZE_A::RING_NONE
     }
 }
-#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
 pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>;
 impl<'a, REG> RING_SIZE_W<'a, REG>
 where
@@ -150,9 +150,9 @@ where
         self.variant(RING_SIZE_A::RING_NONE)
     }
 }
-#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_R = crate::BitReader;
-#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
 pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
@@ -1036,12 +1036,12 @@ impl R {
     pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R {
         INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
     pub fn ring_size(&self) -> RING_SIZE_R {
         RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
     pub fn ring_sel(&self) -> RING_SEL_R {
         RING_SEL_R::new(((self.bits >> 12) & 1) != 0)
@@ -1096,98 +1096,82 @@ impl R {
 impl W {
     #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CH_CTRL_TRIG_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."]
     #[inline(always)]
-    #[must_use]
     pub fn high_priority(&mut self) -> HIGH_PRIORITY_W<CH_CTRL_TRIG_SPEC> {
         HIGH_PRIORITY_W::new(self, 1)
     }
     #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn data_size(&mut self) -> DATA_SIZE_W<CH_CTRL_TRIG_SPEC> {
         DATA_SIZE_W::new(self, 2)
     }
     #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read(&mut self) -> INCR_READ_W<CH_CTRL_TRIG_SPEC> {
         INCR_READ_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W<CH_CTRL_TRIG_SPEC> {
         INCR_READ_REV_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write(&mut self) -> INCR_WRITE_W<CH_CTRL_TRIG_SPEC> {
         INCR_WRITE_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."]
     #[inline(always)]
-    #[must_use]
     pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W<CH_CTRL_TRIG_SPEC> {
         INCR_WRITE_REV_W::new(self, 7)
     }
-    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 &lt;&lt; n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
+    #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_size(&mut self) -> RING_SIZE_W<CH_CTRL_TRIG_SPEC> {
         RING_SIZE_W::new(self, 8)
     }
-    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 &lt;&lt; RING_SIZE) boundary. If 1, write addresses are wrapped."]
+    #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."]
     #[inline(always)]
-    #[must_use]
     pub fn ring_sel(&mut self) -> RING_SEL_W<CH_CTRL_TRIG_SPEC> {
         RING_SEL_W::new(self, 12)
     }
     #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.   
  Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."]
     #[inline(always)]
-    #[must_use]
     pub fn chain_to(&mut self) -> CHAIN_TO_W<CH_CTRL_TRIG_SPEC> {
         CHAIN_TO_W::new(self, 13)
     }
     #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"]
     #[inline(always)]
-    #[must_use]
     pub fn treq_sel(&mut self) -> TREQ_SEL_W<CH_CTRL_TRIG_SPEC> {
         TREQ_SEL_W::new(self, 17)
     }
     #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."]
     #[inline(always)]
-    #[must_use]
     pub fn irq_quiet(&mut self) -> IRQ_QUIET_W<CH_CTRL_TRIG_SPEC> {
         IRQ_QUIET_W::new(self, 23)
     }
     #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."]
     #[inline(always)]
-    #[must_use]
     pub fn bswap(&mut self) -> BSWAP_W<CH_CTRL_TRIG_SPEC> {
         BSWAP_W::new(self, 24)
     }
     #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_en(&mut self) -> SNIFF_EN_W<CH_CTRL_TRIG_SPEC> {
         SNIFF_EN_W::new(self, 25)
     }
     #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn write_error(&mut self) -> WRITE_ERROR_W<CH_CTRL_TRIG_SPEC> {
         WRITE_ERROR_W::new(self, 29)
     }
     #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"]
     #[inline(always)]
-    #[must_use]
     pub fn read_error(&mut self) -> READ_ERROR_W<CH_CTRL_TRIG_SPEC> {
         READ_ERROR_W::new(self, 30)
     }
diff --git a/src/inner/dma/ch/ch_read_addr.rs b/src/inner/dma/ch/ch_read_addr.rs
index 6f87fed..76e5a58 100644
--- a/src/inner/dma/ch/ch_read_addr.rs
+++ b/src/inner/dma/ch/ch_read_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_read_addr(&mut self) -> CH0_READ_ADDR_W<CH_READ_ADDR_SPEC> {
         CH0_READ_ADDR_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch/ch_trans_count.rs b/src/inner/dma/ch/ch_trans_count.rs
index 6a34ba8..dd8a8e8 100644
--- a/src/inner/dma/ch/ch_trans_count.rs
+++ b/src/inner/dma/ch/ch_trans_count.rs
@@ -96,13 +96,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:27 - 28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."]
     #[inline(always)]
-    #[must_use]
     pub fn count(&mut self) -> COUNT_W<CH_TRANS_COUNT_SPEC> {
         COUNT_W::new(self, 0)
     }
     #[doc = "Bits 28:31 - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<CH_TRANS_COUNT_SPEC> {
         MODE_W::new(self, 28)
     }
diff --git a/src/inner/dma/ch/ch_write_addr.rs b/src/inner/dma/ch/ch_write_addr.rs
index 77e195a..a56ea3f 100644
--- a/src/inner/dma/ch/ch_write_addr.rs
+++ b/src/inner/dma/ch/ch_write_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_write_addr(&mut self) -> CH0_WRITE_ADDR_W<CH_WRITE_ADDR_SPEC> {
         CH0_WRITE_ADDR_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch0_dbg_ctdreq.rs b/src/inner/dma/ch0_dbg_ctdreq.rs
index ec7ad62..adf34eb 100644
--- a/src/inner/dma/ch0_dbg_ctdreq.rs
+++ b/src/inner/dma/ch0_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0_dbg_ctdreq(&mut self) -> CH0_DBG_CTDREQ_W<CH0_DBG_CTDREQ_SPEC> {
         CH0_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch10_dbg_ctdreq.rs b/src/inner/dma/ch10_dbg_ctdreq.rs
index cbb3bda..9ed79b9 100644
--- a/src/inner/dma/ch10_dbg_ctdreq.rs
+++ b/src/inner/dma/ch10_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10_dbg_ctdreq(&mut self) -> CH10_DBG_CTDREQ_W<CH10_DBG_CTDREQ_SPEC> {
         CH10_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch11_dbg_ctdreq.rs b/src/inner/dma/ch11_dbg_ctdreq.rs
index c0ba0f2..f94ba11 100644
--- a/src/inner/dma/ch11_dbg_ctdreq.rs
+++ b/src/inner/dma/ch11_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11_dbg_ctdreq(&mut self) -> CH11_DBG_CTDREQ_W<CH11_DBG_CTDREQ_SPEC> {
         CH11_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch12_dbg_ctdreq.rs b/src/inner/dma/ch12_dbg_ctdreq.rs
index f5f3bc6..cf6de58 100644
--- a/src/inner/dma/ch12_dbg_ctdreq.rs
+++ b/src/inner/dma/ch12_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch12_dbg_ctdreq(&mut self) -> CH12_DBG_CTDREQ_W<CH12_DBG_CTDREQ_SPEC> {
         CH12_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch13_dbg_ctdreq.rs b/src/inner/dma/ch13_dbg_ctdreq.rs
index dd56789..bfe817f 100644
--- a/src/inner/dma/ch13_dbg_ctdreq.rs
+++ b/src/inner/dma/ch13_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch13_dbg_ctdreq(&mut self) -> CH13_DBG_CTDREQ_W<CH13_DBG_CTDREQ_SPEC> {
         CH13_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch14_dbg_ctdreq.rs b/src/inner/dma/ch14_dbg_ctdreq.rs
index 7139201..6147950 100644
--- a/src/inner/dma/ch14_dbg_ctdreq.rs
+++ b/src/inner/dma/ch14_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch14_dbg_ctdreq(&mut self) -> CH14_DBG_CTDREQ_W<CH14_DBG_CTDREQ_SPEC> {
         CH14_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch15_dbg_ctdreq.rs b/src/inner/dma/ch15_dbg_ctdreq.rs
index 7d2e78d..362e35a 100644
--- a/src/inner/dma/ch15_dbg_ctdreq.rs
+++ b/src/inner/dma/ch15_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch15_dbg_ctdreq(&mut self) -> CH15_DBG_CTDREQ_W<CH15_DBG_CTDREQ_SPEC> {
         CH15_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch1_dbg_ctdreq.rs b/src/inner/dma/ch1_dbg_ctdreq.rs
index 76305bd..b333fdb 100644
--- a/src/inner/dma/ch1_dbg_ctdreq.rs
+++ b/src/inner/dma/ch1_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1_dbg_ctdreq(&mut self) -> CH1_DBG_CTDREQ_W<CH1_DBG_CTDREQ_SPEC> {
         CH1_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch2_dbg_ctdreq.rs b/src/inner/dma/ch2_dbg_ctdreq.rs
index 0f5bb65..b38e022 100644
--- a/src/inner/dma/ch2_dbg_ctdreq.rs
+++ b/src/inner/dma/ch2_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2_dbg_ctdreq(&mut self) -> CH2_DBG_CTDREQ_W<CH2_DBG_CTDREQ_SPEC> {
         CH2_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch3_dbg_ctdreq.rs b/src/inner/dma/ch3_dbg_ctdreq.rs
index 3427fde..0981c4a 100644
--- a/src/inner/dma/ch3_dbg_ctdreq.rs
+++ b/src/inner/dma/ch3_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3_dbg_ctdreq(&mut self) -> CH3_DBG_CTDREQ_W<CH3_DBG_CTDREQ_SPEC> {
         CH3_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch4_dbg_ctdreq.rs b/src/inner/dma/ch4_dbg_ctdreq.rs
index 8adbc24..b105128 100644
--- a/src/inner/dma/ch4_dbg_ctdreq.rs
+++ b/src/inner/dma/ch4_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4_dbg_ctdreq(&mut self) -> CH4_DBG_CTDREQ_W<CH4_DBG_CTDREQ_SPEC> {
         CH4_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch5_dbg_ctdreq.rs b/src/inner/dma/ch5_dbg_ctdreq.rs
index e13044b..a191361 100644
--- a/src/inner/dma/ch5_dbg_ctdreq.rs
+++ b/src/inner/dma/ch5_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5_dbg_ctdreq(&mut self) -> CH5_DBG_CTDREQ_W<CH5_DBG_CTDREQ_SPEC> {
         CH5_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch6_dbg_ctdreq.rs b/src/inner/dma/ch6_dbg_ctdreq.rs
index ec820b3..e0b95b8 100644
--- a/src/inner/dma/ch6_dbg_ctdreq.rs
+++ b/src/inner/dma/ch6_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6_dbg_ctdreq(&mut self) -> CH6_DBG_CTDREQ_W<CH6_DBG_CTDREQ_SPEC> {
         CH6_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch7_dbg_ctdreq.rs b/src/inner/dma/ch7_dbg_ctdreq.rs
index c83561a..4d5f0a5 100644
--- a/src/inner/dma/ch7_dbg_ctdreq.rs
+++ b/src/inner/dma/ch7_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7_dbg_ctdreq(&mut self) -> CH7_DBG_CTDREQ_W<CH7_DBG_CTDREQ_SPEC> {
         CH7_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch8_dbg_ctdreq.rs b/src/inner/dma/ch8_dbg_ctdreq.rs
index 8ba03d5..0ba643d 100644
--- a/src/inner/dma/ch8_dbg_ctdreq.rs
+++ b/src/inner/dma/ch8_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8_dbg_ctdreq(&mut self) -> CH8_DBG_CTDREQ_W<CH8_DBG_CTDREQ_SPEC> {
         CH8_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/ch9_dbg_ctdreq.rs b/src/inner/dma/ch9_dbg_ctdreq.rs
index 8017e5c..369acbf 100644
--- a/src/inner/dma/ch9_dbg_ctdreq.rs
+++ b/src/inner/dma/ch9_dbg_ctdreq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9_dbg_ctdreq(&mut self) -> CH9_DBG_CTDREQ_W<CH9_DBG_CTDREQ_SPEC> {
         CH9_DBG_CTDREQ_W::new(self, 0)
     }
diff --git a/src/inner/dma/chan_abort.rs b/src/inner/dma/chan_abort.rs
index 92a26e3..607e105 100644
--- a/src/inner/dma/chan_abort.rs
+++ b/src/inner/dma/chan_abort.rs
@@ -7,7 +7,6 @@ pub type CHAN_ABORT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
 impl W {
     #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."]
     #[inline(always)]
-    #[must_use]
     pub fn chan_abort(&mut self) -> CHAN_ABORT_W<CHAN_ABORT_SPEC> {
         CHAN_ABORT_W::new(self, 0)
     }
diff --git a/src/inner/dma/inte0.rs b/src/inner/dma/inte0.rs
index c795b89..69e9a72 100644
--- a/src/inner/dma/inte0.rs
+++ b/src/inner/dma/inte0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."]
     #[inline(always)]
-    #[must_use]
     pub fn inte0(&mut self) -> INTE0_W<INTE0_SPEC> {
         INTE0_W::new(self, 0)
     }
diff --git a/src/inner/dma/inte1.rs b/src/inner/dma/inte1.rs
index 6779f7e..e9e2236 100644
--- a/src/inner/dma/inte1.rs
+++ b/src/inner/dma/inte1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."]
     #[inline(always)]
-    #[must_use]
     pub fn inte1(&mut self) -> INTE1_W<INTE1_SPEC> {
         INTE1_W::new(self, 0)
     }
diff --git a/src/inner/dma/inte2.rs b/src/inner/dma/inte2.rs
index a7f9b71..89ba227 100644
--- a/src/inner/dma/inte2.rs
+++ b/src/inner/dma/inte2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."]
     #[inline(always)]
-    #[must_use]
     pub fn inte2(&mut self) -> INTE2_W<INTE2_SPEC> {
         INTE2_W::new(self, 0)
     }
diff --git a/src/inner/dma/inte3.rs b/src/inner/dma/inte3.rs
index 15f880c..fc42d35 100644
--- a/src/inner/dma/inte3.rs
+++ b/src/inner/dma/inte3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."]
     #[inline(always)]
-    #[must_use]
     pub fn inte3(&mut self) -> INTE3_W<INTE3_SPEC> {
         INTE3_W::new(self, 0)
     }
diff --git a/src/inner/dma/intf0.rs b/src/inner/dma/intf0.rs
index a00489c..66de1ab 100644
--- a/src/inner/dma/intf0.rs
+++ b/src/inner/dma/intf0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn intf0(&mut self) -> INTF0_W<INTF0_SPEC> {
         INTF0_W::new(self, 0)
     }
diff --git a/src/inner/dma/intf1.rs b/src/inner/dma/intf1.rs
index 28bbabd..1ffe158 100644
--- a/src/inner/dma/intf1.rs
+++ b/src/inner/dma/intf1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn intf1(&mut self) -> INTF1_W<INTF1_SPEC> {
         INTF1_W::new(self, 0)
     }
diff --git a/src/inner/dma/intf2.rs b/src/inner/dma/intf2.rs
index a3e5bf1..626b7fd 100644
--- a/src/inner/dma/intf2.rs
+++ b/src/inner/dma/intf2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn intf2(&mut self) -> INTF2_W<INTF2_SPEC> {
         INTF2_W::new(self, 0)
     }
diff --git a/src/inner/dma/intf3.rs b/src/inner/dma/intf3.rs
index 377a7c0..8fa2fdb 100644
--- a/src/inner/dma/intf3.rs
+++ b/src/inner/dma/intf3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn intf3(&mut self) -> INTF3_W<INTF3_SPEC> {
         INTF3_W::new(self, 0)
     }
diff --git a/src/inner/dma/intr.rs b/src/inner/dma/intr.rs
index be53e26..2467bf2 100644
--- a/src/inner/dma/intr.rs
+++ b/src/inner/dma/intr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn intr(&mut self) -> INTR_W<INTR_SPEC> {
         INTR_W::new(self, 0)
     }
diff --git a/src/inner/dma/intr1.rs b/src/inner/dma/intr1.rs
index 25c2ce6..9abf856 100644
--- a/src/inner/dma/intr1.rs
+++ b/src/inner/dma/intr1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn intr1(&mut self) -> INTR1_W<INTR1_SPEC> {
         INTR1_W::new(self, 0)
     }
diff --git a/src/inner/dma/intr2.rs b/src/inner/dma/intr2.rs
index 84f0498..a35b8a6 100644
--- a/src/inner/dma/intr2.rs
+++ b/src/inner/dma/intr2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn intr2(&mut self) -> INTR2_W<INTR2_SPEC> {
         INTR2_W::new(self, 0)
     }
diff --git a/src/inner/dma/intr3.rs b/src/inner/dma/intr3.rs
index e589539..a8ff4eb 100644
--- a/src/inner/dma/intr3.rs
+++ b/src/inner/dma/intr3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn intr3(&mut self) -> INTR3_W<INTR3_SPEC> {
         INTR3_W::new(self, 0)
     }
diff --git a/src/inner/dma/ints0.rs b/src/inner/dma/ints0.rs
index b06bf67..351e3dc 100644
--- a/src/inner/dma/ints0.rs
+++ b/src/inner/dma/ints0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn ints0(&mut self) -> INTS0_W<INTS0_SPEC> {
         INTS0_W::new(self, 0)
     }
diff --git a/src/inner/dma/ints1.rs b/src/inner/dma/ints1.rs
index 114cb13..ca3df26 100644
--- a/src/inner/dma/ints1.rs
+++ b/src/inner/dma/ints1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn ints1(&mut self) -> INTS1_W<INTS1_SPEC> {
         INTS1_W::new(self, 0)
     }
diff --git a/src/inner/dma/ints2.rs b/src/inner/dma/ints2.rs
index e178af4..1028203 100644
--- a/src/inner/dma/ints2.rs
+++ b/src/inner/dma/ints2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn ints2(&mut self) -> INTS2_W<INTS2_SPEC> {
         INTS2_W::new(self, 0)
     }
diff --git a/src/inner/dma/ints3.rs b/src/inner/dma/ints3.rs
index 91c993e..cabd682 100644
--- a/src/inner/dma/ints3.rs
+++ b/src/inner/dma/ints3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."]
     #[inline(always)]
-    #[must_use]
     pub fn ints3(&mut self) -> INTS3_W<INTS3_SPEC> {
         INTS3_W::new(self, 0)
     }
diff --git a/src/inner/dma/mpu_bar0.rs b/src/inner/dma/mpu_bar0.rs
index 22df435..04d6f3a 100644
--- a/src/inner/dma/mpu_bar0.rs
+++ b/src/inner/dma/mpu_bar0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR0_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar1.rs b/src/inner/dma/mpu_bar1.rs
index 8c4fb21..74b5d65 100644
--- a/src/inner/dma/mpu_bar1.rs
+++ b/src/inner/dma/mpu_bar1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR1_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar2.rs b/src/inner/dma/mpu_bar2.rs
index 36e168c..14a4f97 100644
--- a/src/inner/dma/mpu_bar2.rs
+++ b/src/inner/dma/mpu_bar2.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR2_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar3.rs b/src/inner/dma/mpu_bar3.rs
index 4632e9d..6803c2e 100644
--- a/src/inner/dma/mpu_bar3.rs
+++ b/src/inner/dma/mpu_bar3.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR3_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar4.rs b/src/inner/dma/mpu_bar4.rs
index a97cc56..f8c2a75 100644
--- a/src/inner/dma/mpu_bar4.rs
+++ b/src/inner/dma/mpu_bar4.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR4_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar5.rs b/src/inner/dma/mpu_bar5.rs
index 8659002..807cff9 100644
--- a/src/inner/dma/mpu_bar5.rs
+++ b/src/inner/dma/mpu_bar5.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR5_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar6.rs b/src/inner/dma/mpu_bar6.rs
index 842faeb..c356fef 100644
--- a/src/inner/dma/mpu_bar6.rs
+++ b/src/inner/dma/mpu_bar6.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR6_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_bar7.rs b/src/inner/dma/mpu_bar7.rs
index fb8cf0d..d929385 100644
--- a/src/inner/dma/mpu_bar7.rs
+++ b/src/inner/dma/mpu_bar7.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\]
 (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_BAR7_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_ctrl.rs b/src/inner/dma/mpu_ctrl.rs
index 3d04289..3e4560d 100644
--- a/src/inner/dma/mpu_ctrl.rs
+++ b/src/inner/dma/mpu_ctrl.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_CTRL_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_CTRL_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bit 3 - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."]
     #[inline(always)]
-    #[must_use]
     pub fn ns_hide_addr(&mut self) -> NS_HIDE_ADDR_W<MPU_CTRL_SPEC> {
         NS_HIDE_ADDR_W::new(self, 3)
     }
diff --git a/src/inner/dma/mpu_lar0.rs b/src/inner/dma/mpu_lar0.rs
index ed63d14..a6b2acb 100644
--- a/src/inner/dma/mpu_lar0.rs
+++ b/src/inner/dma/mpu_lar0.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR0_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR0_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR0_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR0_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar1.rs b/src/inner/dma/mpu_lar1.rs
index 903640a..993ae63 100644
--- a/src/inner/dma/mpu_lar1.rs
+++ b/src/inner/dma/mpu_lar1.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR1_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR1_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR1_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR1_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar2.rs b/src/inner/dma/mpu_lar2.rs
index b9649ec..9c693b7 100644
--- a/src/inner/dma/mpu_lar2.rs
+++ b/src/inner/dma/mpu_lar2.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR2_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR2_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR2_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR2_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar3.rs b/src/inner/dma/mpu_lar3.rs
index a162727..77f749d 100644
--- a/src/inner/dma/mpu_lar3.rs
+++ b/src/inner/dma/mpu_lar3.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR3_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR3_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR3_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR3_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar4.rs b/src/inner/dma/mpu_lar4.rs
index 4018636..a1a7e59 100644
--- a/src/inner/dma/mpu_lar4.rs
+++ b/src/inner/dma/mpu_lar4.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR4_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR4_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR4_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR4_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar5.rs b/src/inner/dma/mpu_lar5.rs
index 81f43f4..af5030a 100644
--- a/src/inner/dma/mpu_lar5.rs
+++ b/src/inner/dma/mpu_lar5.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR5_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR5_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR5_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR5_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar6.rs b/src/inner/dma/mpu_lar6.rs
index 9cce5c3..3a44f85 100644
--- a/src/inner/dma/mpu_lar6.rs
+++ b/src/inner/dma/mpu_lar6.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR6_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR6_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR6_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR6_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/mpu_lar7.rs b/src/inner/dma/mpu_lar7.rs
index e958f91..b1aede7 100644
--- a/src/inner/dma/mpu_lar7.rs
+++ b/src/inner/dma/mpu_lar7.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_LAR7_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<MPU_LAR7_SPEC> {
         P_W::new(self, 1)
     }
     #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<MPU_LAR7_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."]
     #[inline(always)]
-    #[must_use]
     pub fn addr(&mut self) -> ADDR_W<MPU_LAR7_SPEC> {
         ADDR_W::new(self, 5)
     }
diff --git a/src/inner/dma/multi_chan_trigger.rs b/src/inner/dma/multi_chan_trigger.rs
index e676443..9b4f04e 100644
--- a/src/inner/dma/multi_chan_trigger.rs
+++ b/src/inner/dma/multi_chan_trigger.rs
@@ -7,7 +7,6 @@ pub type MULTI_CHAN_TRIGGER_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
 impl W {
     #[doc = "Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."]
     #[inline(always)]
-    #[must_use]
     pub fn multi_chan_trigger(&mut self) -> MULTI_CHAN_TRIGGER_W<MULTI_CHAN_TRIGGER_SPEC> {
         MULTI_CHAN_TRIGGER_W::new(self, 0)
     }
diff --git a/src/inner/dma/seccfg_ch0.rs b/src/inner/dma/seccfg_ch0.rs
index 49f0f6f..b66d1dd 100644
--- a/src/inner/dma/seccfg_ch0.rs
+++ b/src/inner/dma/seccfg_ch0.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH0_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH0_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH0_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch1.rs b/src/inner/dma/seccfg_ch1.rs
index c349238..525fac9 100644
--- a/src/inner/dma/seccfg_ch1.rs
+++ b/src/inner/dma/seccfg_ch1.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH1_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH1_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH1_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch10.rs b/src/inner/dma/seccfg_ch10.rs
index 42bde7e..8348958 100644
--- a/src/inner/dma/seccfg_ch10.rs
+++ b/src/inner/dma/seccfg_ch10.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH10_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH10_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH10_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch11.rs b/src/inner/dma/seccfg_ch11.rs
index 2a11fcb..a393d17 100644
--- a/src/inner/dma/seccfg_ch11.rs
+++ b/src/inner/dma/seccfg_ch11.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH11_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH11_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH11_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch12.rs b/src/inner/dma/seccfg_ch12.rs
index 24fbf00..4d31774 100644
--- a/src/inner/dma/seccfg_ch12.rs
+++ b/src/inner/dma/seccfg_ch12.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH12_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH12_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH12_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch13.rs b/src/inner/dma/seccfg_ch13.rs
index cd6d2ed..4f3c885 100644
--- a/src/inner/dma/seccfg_ch13.rs
+++ b/src/inner/dma/seccfg_ch13.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH13_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH13_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH13_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch14.rs b/src/inner/dma/seccfg_ch14.rs
index 84320d6..ad0e26c 100644
--- a/src/inner/dma/seccfg_ch14.rs
+++ b/src/inner/dma/seccfg_ch14.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH14_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH14_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH14_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch15.rs b/src/inner/dma/seccfg_ch15.rs
index fa61c66..6003821 100644
--- a/src/inner/dma/seccfg_ch15.rs
+++ b/src/inner/dma/seccfg_ch15.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH15_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH15_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH15_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch2.rs b/src/inner/dma/seccfg_ch2.rs
index 32d8b1b..4249898 100644
--- a/src/inner/dma/seccfg_ch2.rs
+++ b/src/inner/dma/seccfg_ch2.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH2_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH2_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH2_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch3.rs b/src/inner/dma/seccfg_ch3.rs
index dcb4cf7..2f290a3 100644
--- a/src/inner/dma/seccfg_ch3.rs
+++ b/src/inner/dma/seccfg_ch3.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH3_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH3_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH3_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch4.rs b/src/inner/dma/seccfg_ch4.rs
index 6294b85..7cfc223 100644
--- a/src/inner/dma/seccfg_ch4.rs
+++ b/src/inner/dma/seccfg_ch4.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH4_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH4_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH4_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch5.rs b/src/inner/dma/seccfg_ch5.rs
index 45a845d..a5fa3e8 100644
--- a/src/inner/dma/seccfg_ch5.rs
+++ b/src/inner/dma/seccfg_ch5.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH5_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH5_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH5_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch6.rs b/src/inner/dma/seccfg_ch6.rs
index c41b34e..b7cd8d3 100644
--- a/src/inner/dma/seccfg_ch6.rs
+++ b/src/inner/dma/seccfg_ch6.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH6_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH6_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH6_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch7.rs b/src/inner/dma/seccfg_ch7.rs
index c9a8a5c..e78fbac 100644
--- a/src/inner/dma/seccfg_ch7.rs
+++ b/src/inner/dma/seccfg_ch7.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH7_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH7_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH7_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch8.rs b/src/inner/dma/seccfg_ch8.rs
index b45c66b..2581d4e 100644
--- a/src/inner/dma/seccfg_ch8.rs
+++ b/src/inner/dma/seccfg_ch8.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH8_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH8_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH8_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_ch9.rs b/src/inner/dma/seccfg_ch9.rs
index 459c69b..3a72d2f 100644
--- a/src/inner/dma/seccfg_ch9.rs
+++ b/src/inner/dma/seccfg_ch9.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_CH9_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_CH9_SPEC> {
         S_W::new(self, 1)
     }
     #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<SECCFG_CH9_SPEC> {
         LOCK_W::new(self, 2)
     }
diff --git a/src/inner/dma/seccfg_irq0.rs b/src/inner/dma/seccfg_irq0.rs
index 85a8c27..8946599 100644
--- a/src/inner/dma/seccfg_irq0.rs
+++ b/src/inner/dma/seccfg_irq0.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_IRQ0_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_IRQ0_SPEC> {
         S_W::new(self, 1)
     }
diff --git a/src/inner/dma/seccfg_irq1.rs b/src/inner/dma/seccfg_irq1.rs
index 9f893e3..49ceda8 100644
--- a/src/inner/dma/seccfg_irq1.rs
+++ b/src/inner/dma/seccfg_irq1.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_IRQ1_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_IRQ1_SPEC> {
         S_W::new(self, 1)
     }
diff --git a/src/inner/dma/seccfg_irq2.rs b/src/inner/dma/seccfg_irq2.rs
index b82a6b3..dd0aa39 100644
--- a/src/inner/dma/seccfg_irq2.rs
+++ b/src/inner/dma/seccfg_irq2.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_IRQ2_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_IRQ2_SPEC> {
         S_W::new(self, 1)
     }
diff --git a/src/inner/dma/seccfg_irq3.rs b/src/inner/dma/seccfg_irq3.rs
index f227ee2..72437ba 100644
--- a/src/inner/dma/seccfg_irq3.rs
+++ b/src/inner/dma/seccfg_irq3.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."]
     #[inline(always)]
-    #[must_use]
     pub fn p(&mut self) -> P_W<SECCFG_IRQ3_SPEC> {
         P_W::new(self, 0)
     }
     #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<SECCFG_IRQ3_SPEC> {
         S_W::new(self, 1)
     }
diff --git a/src/inner/dma/seccfg_misc.rs b/src/inner/dma/seccfg_misc.rs
index 1ae0f2c..56230a7 100644
--- a/src/inner/dma/seccfg_misc.rs
+++ b/src/inner/dma/seccfg_misc.rs
@@ -97,61 +97,51 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_p(&mut self) -> SNIFF_P_W<SECCFG_MISC_SPEC> {
         SNIFF_P_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_s(&mut self) -> SNIFF_S_W<SECCFG_MISC_SPEC> {
         SNIFF_S_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_p(&mut self) -> TIMER0_P_W<SECCFG_MISC_SPEC> {
         TIMER0_P_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer0_s(&mut self) -> TIMER0_S_W<SECCFG_MISC_SPEC> {
         TIMER0_S_W::new(self, 3)
     }
     #[doc = "Bit 4 - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_p(&mut self) -> TIMER1_P_W<SECCFG_MISC_SPEC> {
         TIMER1_P_W::new(self, 4)
     }
     #[doc = "Bit 5 - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer1_s(&mut self) -> TIMER1_S_W<SECCFG_MISC_SPEC> {
         TIMER1_S_W::new(self, 5)
     }
     #[doc = "Bit 6 - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_p(&mut self) -> TIMER2_P_W<SECCFG_MISC_SPEC> {
         TIMER2_P_W::new(self, 6)
     }
     #[doc = "Bit 7 - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer2_s(&mut self) -> TIMER2_S_W<SECCFG_MISC_SPEC> {
         TIMER2_S_W::new(self, 7)
     }
     #[doc = "Bit 8 - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_p(&mut self) -> TIMER3_P_W<SECCFG_MISC_SPEC> {
         TIMER3_P_W::new(self, 8)
     }
     #[doc = "Bit 9 - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."]
     #[inline(always)]
-    #[must_use]
     pub fn timer3_s(&mut self) -> TIMER3_S_W<SECCFG_MISC_SPEC> {
         TIMER3_S_W::new(self, 9)
     }
diff --git a/src/inner/dma/sniff_ctrl.rs b/src/inner/dma/sniff_ctrl.rs
index 7869431..fe52c5d 100644
--- a/src/inner/dma/sniff_ctrl.rs
+++ b/src/inner/dma/sniff_ctrl.rs
@@ -171,37 +171,31 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable sniffer"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<SNIFF_CTRL_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - DMA channel for Sniffer to observe"]
     #[inline(always)]
-    #[must_use]
     pub fn dmach(&mut self) -> DMACH_W<SNIFF_CTRL_SPEC> {
         DMACH_W::new(self, 1)
     }
     #[doc = "Bits 5:8"]
     #[inline(always)]
-    #[must_use]
     pub fn calc(&mut self) -> CALC_W<SNIFF_CTRL_SPEC> {
         CALC_W::new(self, 5)
     }
     #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."]
     #[inline(always)]
-    #[must_use]
     pub fn bswap(&mut self) -> BSWAP_W<SNIFF_CTRL_SPEC> {
         BSWAP_W::new(self, 9)
     }
     #[doc = "Bit 10 - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."]
     #[inline(always)]
-    #[must_use]
     pub fn out_rev(&mut self) -> OUT_REV_W<SNIFF_CTRL_SPEC> {
         OUT_REV_W::new(self, 10)
     }
     #[doc = "Bit 11 - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."]
     #[inline(always)]
-    #[must_use]
     pub fn out_inv(&mut self) -> OUT_INV_W<SNIFF_CTRL_SPEC> {
         OUT_INV_W::new(self, 11)
     }
diff --git a/src/inner/dma/sniff_data.rs b/src/inner/dma/sniff_data.rs
index e48a906..50e104c 100644
--- a/src/inner/dma/sniff_data.rs
+++ b/src/inner/dma/sniff_data.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."]
     #[inline(always)]
-    #[must_use]
     pub fn sniff_data(&mut self) -> SNIFF_DATA_W<SNIFF_DATA_SPEC> {
         SNIFF_DATA_W::new(self, 0)
     }
diff --git a/src/inner/dma/timer0.rs b/src/inner/dma/timer0.rs
index f45cd7b..7683378 100644
--- a/src/inner/dma/timer0.rs
+++ b/src/inner/dma/timer0.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn y(&mut self) -> Y_W<TIMER0_SPEC> {
         Y_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn x(&mut self) -> X_W<TIMER0_SPEC> {
         X_W::new(self, 16)
     }
diff --git a/src/inner/dma/timer1.rs b/src/inner/dma/timer1.rs
index 1f7e437..7f7b0e1 100644
--- a/src/inner/dma/timer1.rs
+++ b/src/inner/dma/timer1.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn y(&mut self) -> Y_W<TIMER1_SPEC> {
         Y_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn x(&mut self) -> X_W<TIMER1_SPEC> {
         X_W::new(self, 16)
     }
diff --git a/src/inner/dma/timer2.rs b/src/inner/dma/timer2.rs
index 87d2e5d..43c3ddc 100644
--- a/src/inner/dma/timer2.rs
+++ b/src/inner/dma/timer2.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn y(&mut self) -> Y_W<TIMER2_SPEC> {
         Y_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn x(&mut self) -> X_W<TIMER2_SPEC> {
         X_W::new(self, 16)
     }
diff --git a/src/inner/dma/timer3.rs b/src/inner/dma/timer3.rs
index 9958ba2..0256ea5 100644
--- a/src/inner/dma/timer3.rs
+++ b/src/inner/dma/timer3.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn y(&mut self) -> Y_W<TIMER3_SPEC> {
         Y_W::new(self, 0)
     }
     #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."]
     #[inline(always)]
-    #[must_use]
     pub fn x(&mut self) -> X_W<TIMER3_SPEC> {
         X_W::new(self, 16)
     }
diff --git a/src/inner/eppb/nmi_mask0.rs b/src/inner/eppb/nmi_mask0.rs
index 600cfac..4dfc07d 100644
--- a/src/inner/eppb/nmi_mask0.rs
+++ b/src/inner/eppb/nmi_mask0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn nmi_mask0(&mut self) -> NMI_MASK0_W<NMI_MASK0_SPEC> {
         NMI_MASK0_W::new(self, 0)
     }
diff --git a/src/inner/eppb/nmi_mask1.rs b/src/inner/eppb/nmi_mask1.rs
index d4a9cb7..7e349df 100644
--- a/src/inner/eppb/nmi_mask1.rs
+++ b/src/inner/eppb/nmi_mask1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:19"]
     #[inline(always)]
-    #[must_use]
     pub fn nmi_mask1(&mut self) -> NMI_MASK1_W<NMI_MASK1_SPEC> {
         NMI_MASK1_W::new(self, 0)
     }
diff --git a/src/inner/eppb/sleepctrl.rs b/src/inner/eppb/sleepctrl.rs
index 64e2e46..a660199 100644
--- a/src/inner/eppb/sleepctrl.rs
+++ b/src/inner/eppb/sleepctrl.rs
@@ -32,13 +32,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."]
     #[inline(always)]
-    #[must_use]
     pub fn light_sleep(&mut self) -> LIGHT_SLEEP_W<SLEEPCTRL_SPEC> {
         LIGHT_SLEEP_W::new(self, 0)
     }
     #[doc = "Bit 1 - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."]
     #[inline(always)]
-    #[must_use]
     pub fn wicenreq(&mut self) -> WICENREQ_W<SLEEPCTRL_SPEC> {
         WICENREQ_W::new(self, 1)
     }
diff --git a/src/inner/generic.rs b/src/inner/generic.rs
index d57106c..a7cb020 100644
--- a/src/inner/generic.rs
+++ b/src/inner/generic.rs
@@ -524,18 +524,60 @@ impl<REG: Resettable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " In the latter case, other fields will be set to their reset value."]
     #[inline(always)]
-    pub fn write<F>(&self, f: F)
+    pub fn write<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes bits to a `Writable` register and produce a value."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write_and(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[doc = ""]
+    #[doc = " Values can be returned from the closure:"]
+    #[doc = " ```ignore"]
+    #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn from_write<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Writable> Reg<REG> {
@@ -547,17 +589,37 @@ impl<REG: Writable> Reg<REG> {
     #[doc = ""]
     #[doc = " Unsafe to use with registers which don't allow to write 0."]
     #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F)
+    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
     where
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
-        self.register.set(
-            f(&mut W {
-                bits: REG::Ux::default(),
-                _reg: marker::PhantomData,
-            })
-            .bits,
-        );
+        let value = f(&mut W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        })
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Writes 0 to a `Writable` register and produces a value."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
+    where
+        F: FnOnce(&mut W<REG>) -> T,
+    {
+        let mut writer = W {
+            bits: REG::Ux::default(),
+            _reg: marker::PhantomData,
+        };
+        let result = f(&mut writer);
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable + Writable> Reg<REG> {
@@ -587,25 +649,75 @@ impl<REG: Readable + Writable> Reg<REG> {
     #[doc = " ```"]
     #[doc = " Other fields will have the value they had before the call to `modify`."]
     #[inline(always)]
-    pub fn modify<F>(&self, f: F)
+    pub fn modify<F>(&self, f: F) -> REG::Ux
     where
         for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
     {
         let bits = self.register.get();
-        self.register.set(
-            f(
-                &R {
-                    bits,
-                    _reg: marker::PhantomData,
-                },
-                &mut W {
-                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                    _reg: marker::PhantomData,
-                },
-            )
-            .bits,
+        let value = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut W {
+                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            },
+        )
+        .bits;
+        self.register.set(value);
+        value
+    }
+    #[doc = " Modifies the contents of the register by reading and then writing it"]
+    #[doc = " and produces a value."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.modify(|r, w| {"]
+    #[doc = "     let new_bits = r.bits() | 3;"]
+    #[doc = "     unsafe {"]
+    #[doc = "         w.bits(new_bits);"]
+    #[doc = "     }"]
+    #[doc = ""]
+    #[doc = "     new_bits"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits)"]
+    #[doc = "         .field2().set_bit()"]
+    #[doc = "         .field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT);"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn from_modify<F, T>(&self, f: F) -> T
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
+    {
+        let bits = self.register.get();
+        let mut writer = W {
+            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+            _reg: marker::PhantomData,
+        };
+        let result = f(
+            &R {
+                bits,
+                _reg: marker::PhantomData,
+            },
+            &mut writer,
         );
+        self.register.set(writer.bits);
+        result
     }
 }
 impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
diff --git a/src/inner/generic/raw.rs b/src/inner/generic/raw.rs
index 81f5779..d60a23a 100644
--- a/src/inner/generic/raw.rs
+++ b/src/inner/generic/raw.rs
@@ -41,6 +41,7 @@ impl<FI> BitReader<FI> {
         }
     }
 }
+#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
 where
     REG: Writable + RegisterSpec,
@@ -66,6 +67,7 @@ where
         }
     }
 }
+#[must_use = "after creating `BitWriter` you need to call bit setting method"]
 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
 where
     REG: Writable + RegisterSpec,
diff --git a/src/inner/glitch_detector/arm.rs b/src/inner/glitch_detector/arm.rs
index b3a6120..e5b02a0 100644
--- a/src/inner/glitch_detector/arm.rs
+++ b/src/inner/glitch_detector/arm.rs
@@ -74,7 +74,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn arm(&mut self) -> ARM_W<ARM_SPEC> {
         ARM_W::new(self, 0)
     }
diff --git a/src/inner/glitch_detector/disarm.rs b/src/inner/glitch_detector/disarm.rs
index 6ddf16e..df0c686 100644
--- a/src/inner/glitch_detector/disarm.rs
+++ b/src/inner/glitch_detector/disarm.rs
@@ -74,7 +74,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."]
     #[inline(always)]
-    #[must_use]
     pub fn disarm(&mut self) -> DISARM_W<DISARM_SPEC> {
         DISARM_W::new(self, 0)
     }
diff --git a/src/inner/glitch_detector/lock.rs b/src/inner/glitch_detector/lock.rs
index 2800f37..10a5647 100644
--- a/src/inner/glitch_detector/lock.rs
+++ b/src/inner/glitch_detector/lock.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."]
     #[inline(always)]
-    #[must_use]
     pub fn lock(&mut self) -> LOCK_W<LOCK_SPEC> {
         LOCK_W::new(self, 0)
     }
diff --git a/src/inner/glitch_detector/sensitivity.rs b/src/inner/glitch_detector/sensitivity.rs
index 7b6ea26..9f4b374 100644
--- a/src/inner/glitch_detector/sensitivity.rs
+++ b/src/inner/glitch_detector/sensitivity.rs
@@ -146,55 +146,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Set sensitivity for detector 0. Higher values are more sensitive."]
     #[inline(always)]
-    #[must_use]
     pub fn det0(&mut self) -> DET0_W<SENSITIVITY_SPEC> {
         DET0_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Set sensitivity for detector 1. Higher values are more sensitive."]
     #[inline(always)]
-    #[must_use]
     pub fn det1(&mut self) -> DET1_W<SENSITIVITY_SPEC> {
         DET1_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Set sensitivity for detector 2. Higher values are more sensitive."]
     #[inline(always)]
-    #[must_use]
     pub fn det2(&mut self) -> DET2_W<SENSITIVITY_SPEC> {
         DET2_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - Set sensitivity for detector 3. Higher values are more sensitive."]
     #[inline(always)]
-    #[must_use]
     pub fn det3(&mut self) -> DET3_W<SENSITIVITY_SPEC> {
         DET3_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Must be the inverse of DET0, else the default value is used."]
     #[inline(always)]
-    #[must_use]
     pub fn det0_inv(&mut self) -> DET0_INV_W<SENSITIVITY_SPEC> {
         DET0_INV_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Must be the inverse of DET1, else the default value is used."]
     #[inline(always)]
-    #[must_use]
     pub fn det1_inv(&mut self) -> DET1_INV_W<SENSITIVITY_SPEC> {
         DET1_INV_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - Must be the inverse of DET2, else the default value is used."]
     #[inline(always)]
-    #[must_use]
     pub fn det2_inv(&mut self) -> DET2_INV_W<SENSITIVITY_SPEC> {
         DET2_INV_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Must be the inverse of DET3, else the default value is used."]
     #[inline(always)]
-    #[must_use]
     pub fn det3_inv(&mut self) -> DET3_INV_W<SENSITIVITY_SPEC> {
         DET3_INV_W::new(self, 14)
     }
     #[doc = "Bits 24:31"]
     #[inline(always)]
-    #[must_use]
     pub fn default(&mut self) -> DEFAULT_W<SENSITIVITY_SPEC> {
         DEFAULT_W::new(self, 24)
     }
diff --git a/src/inner/glitch_detector/trig_force.rs b/src/inner/glitch_detector/trig_force.rs
index 7e48d15..c8faf30 100644
--- a/src/inner/glitch_detector/trig_force.rs
+++ b/src/inner/glitch_detector/trig_force.rs
@@ -7,7 +7,6 @@ pub type TRIG_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn trig_force(&mut self) -> TRIG_FORCE_W<TRIG_FORCE_SPEC> {
         TRIG_FORCE_W::new(self, 0)
     }
diff --git a/src/inner/glitch_detector/trig_status.rs b/src/inner/glitch_detector/trig_status.rs
index e7c3ce6..5b15d1e 100644
--- a/src/inner/glitch_detector/trig_status.rs
+++ b/src/inner/glitch_detector/trig_status.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn det0(&mut self) -> DET0_W<TRIG_STATUS_SPEC> {
         DET0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn det1(&mut self) -> DET1_W<TRIG_STATUS_SPEC> {
         DET1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn det2(&mut self) -> DET2_W<TRIG_STATUS_SPEC> {
         DET2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn det3(&mut self) -> DET3_W<TRIG_STATUS_SPEC> {
         DET3_W::new(self, 3)
     }
diff --git a/src/inner/hstx_ctrl/bit0.rs b/src/inner/hstx_ctrl/bit0.rs
index 8fcfb3f..2a7071c 100644
--- a/src/inner/hstx_ctrl/bit0.rs
+++ b/src/inner/hstx_ctrl/bit0.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT0_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT0_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT0_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT0_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit1.rs b/src/inner/hstx_ctrl/bit1.rs
index efb08cd..8298541 100644
--- a/src/inner/hstx_ctrl/bit1.rs
+++ b/src/inner/hstx_ctrl/bit1.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT1_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT1_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT1_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT1_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit2.rs b/src/inner/hstx_ctrl/bit2.rs
index 890bc29..f78302c 100644
--- a/src/inner/hstx_ctrl/bit2.rs
+++ b/src/inner/hstx_ctrl/bit2.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT2_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT2_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT2_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT2_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit3.rs b/src/inner/hstx_ctrl/bit3.rs
index d29c812..03ce718 100644
--- a/src/inner/hstx_ctrl/bit3.rs
+++ b/src/inner/hstx_ctrl/bit3.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT3_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT3_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT3_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT3_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit4.rs b/src/inner/hstx_ctrl/bit4.rs
index 74cc705..e7fb1f7 100644
--- a/src/inner/hstx_ctrl/bit4.rs
+++ b/src/inner/hstx_ctrl/bit4.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT4_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT4_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT4_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT4_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit5.rs b/src/inner/hstx_ctrl/bit5.rs
index d5c0662..6bcaf65 100644
--- a/src/inner/hstx_ctrl/bit5.rs
+++ b/src/inner/hstx_ctrl/bit5.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT5_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT5_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT5_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT5_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit6.rs b/src/inner/hstx_ctrl/bit6.rs
index 234aa1f..3aba656 100644
--- a/src/inner/hstx_ctrl/bit6.rs
+++ b/src/inner/hstx_ctrl/bit6.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT6_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT6_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT6_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT6_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/bit7.rs b/src/inner/hstx_ctrl/bit7.rs
index 259927e..c88dcee 100644
--- a/src/inner/hstx_ctrl/bit7.rs
+++ b/src/inner/hstx_ctrl/bit7.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_p(&mut self) -> SEL_P_W<BIT7_SPEC> {
         SEL_P_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"]
     #[inline(always)]
-    #[must_use]
     pub fn sel_n(&mut self) -> SEL_N_W<BIT7_SPEC> {
         SEL_N_W::new(self, 8)
     }
     #[doc = "Bit 16 - Invert this data output (logical NOT)"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<BIT7_SPEC> {
         INV_W::new(self, 16)
     }
     #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clk(&mut self) -> CLK_W<BIT7_SPEC> {
         CLK_W::new(self, 17)
     }
diff --git a/src/inner/hstx_ctrl/csr.rs b/src/inner/hstx_ctrl/csr.rs
index 5da63b6..74474aa 100644
--- a/src/inner/hstx_ctrl/csr.rs
+++ b/src/inner/hstx_ctrl/csr.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CSR_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."]
     #[inline(always)]
-    #[must_use]
     pub fn expand_en(&mut self) -> EXPAND_EN_W<CSR_SPEC> {
         EXPAND_EN_W::new(self, 1)
     }
     #[doc = "Bit 4 - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."]
     #[inline(always)]
-    #[must_use]
     pub fn coupled_mode(&mut self) -> COUPLED_MODE_W<CSR_SPEC> {
         COUPLED_MODE_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Select which PIO to use for coupled mode operation."]
     #[inline(always)]
-    #[must_use]
     pub fn coupled_sel(&mut self) -> COUPLED_SEL_W<CSR_SPEC> {
         COUPLED_SEL_W::new(self, 5)
     }
     #[doc = "Bits 8:12 - How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<CSR_SPEC> {
         SHIFT_W::new(self, 8)
     }
     #[doc = "Bits 16:20 - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."]
     #[inline(always)]
-    #[must_use]
     pub fn n_shifts(&mut self) -> N_SHIFTS_W<CSR_SPEC> {
         N_SHIFTS_W::new(self, 16)
     }
     #[doc = "Bits 24:27 - Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."]
     #[inline(always)]
-    #[must_use]
     pub fn clkphase(&mut self) -> CLKPHASE_W<CSR_SPEC> {
         CLKPHASE_W::new(self, 24)
     }
     #[doc = "Bits 28:31 - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<CSR_SPEC> {
         CLKDIV_W::new(self, 28)
     }
diff --git a/src/inner/hstx_ctrl/expand_shift.rs b/src/inner/hstx_ctrl/expand_shift.rs
index 040f000..a684845 100644
--- a/src/inner/hstx_ctrl/expand_shift.rs
+++ b/src/inner/hstx_ctrl/expand_shift.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."]
     #[inline(always)]
-    #[must_use]
     pub fn raw_shift(&mut self) -> RAW_SHIFT_W<EXPAND_SHIFT_SPEC> {
         RAW_SHIFT_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."]
     #[inline(always)]
-    #[must_use]
     pub fn raw_n_shifts(&mut self) -> RAW_N_SHIFTS_W<EXPAND_SHIFT_SPEC> {
         RAW_N_SHIFTS_W::new(self, 8)
     }
     #[doc = "Bits 16:20 - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."]
     #[inline(always)]
-    #[must_use]
     pub fn enc_shift(&mut self) -> ENC_SHIFT_W<EXPAND_SHIFT_SPEC> {
         ENC_SHIFT_W::new(self, 16)
     }
     #[doc = "Bits 24:28 - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."]
     #[inline(always)]
-    #[must_use]
     pub fn enc_n_shifts(&mut self) -> ENC_N_SHIFTS_W<EXPAND_SHIFT_SPEC> {
         ENC_N_SHIFTS_W::new(self, 24)
     }
diff --git a/src/inner/hstx_ctrl/expand_tmds.rs b/src/inner/hstx_ctrl/expand_tmds.rs
index 41619c0..f64ec64 100644
--- a/src/inner/hstx_ctrl/expand_tmds.rs
+++ b/src/inner/hstx_ctrl/expand_tmds.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."]
     #[inline(always)]
-    #[must_use]
     pub fn l0_rot(&mut self) -> L0_ROT_W<EXPAND_TMDS_SPEC> {
         L0_ROT_W::new(self, 0)
     }
     #[doc = "Bits 5:7 - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn l0_nbits(&mut self) -> L0_NBITS_W<EXPAND_TMDS_SPEC> {
         L0_NBITS_W::new(self, 5)
     }
     #[doc = "Bits 8:12 - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."]
     #[inline(always)]
-    #[must_use]
     pub fn l1_rot(&mut self) -> L1_ROT_W<EXPAND_TMDS_SPEC> {
         L1_ROT_W::new(self, 8)
     }
     #[doc = "Bits 13:15 - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn l1_nbits(&mut self) -> L1_NBITS_W<EXPAND_TMDS_SPEC> {
         L1_NBITS_W::new(self, 13)
     }
     #[doc = "Bits 16:20 - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."]
     #[inline(always)]
-    #[must_use]
     pub fn l2_rot(&mut self) -> L2_ROT_W<EXPAND_TMDS_SPEC> {
         L2_ROT_W::new(self, 16)
     }
     #[doc = "Bits 21:23 - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn l2_nbits(&mut self) -> L2_NBITS_W<EXPAND_TMDS_SPEC> {
         L2_NBITS_W::new(self, 21)
     }
diff --git a/src/inner/hstx_fifo/fifo.rs b/src/inner/hstx_fifo/fifo.rs
index 41e40d3..49406a3 100644
--- a/src/inner/hstx_fifo/fifo.rs
+++ b/src/inner/hstx_fifo/fifo.rs
@@ -7,7 +7,6 @@ pub type FIFO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn fifo(&mut self) -> FIFO_W<FIFO_SPEC> {
         FIFO_W::new(self, 0)
     }
diff --git a/src/inner/hstx_fifo/stat.rs b/src/inner/hstx_fifo/stat.rs
index dbdd7a8..046f3d8 100644
--- a/src/inner/hstx_fifo/stat.rs
+++ b/src/inner/hstx_fifo/stat.rs
@@ -37,7 +37,6 @@ impl R {
 impl W {
     #[doc = "Bit 10 - FIFO was written when full. Write 1 to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn wof(&mut self) -> WOF_W<STAT_SPEC> {
         WOF_W::new(self, 10)
     }
diff --git a/src/inner/i2c0/ic_ack_general_call.rs b/src/inner/i2c0/ic_ack_general_call.rs
index e0f2b03..32eb2a6 100644
--- a/src/inner/i2c0/ic_ack_general_call.rs
+++ b/src/inner/i2c0/ic_ack_general_call.rs
@@ -67,7 +67,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_gen_call(&mut self) -> ACK_GEN_CALL_W<IC_ACK_GENERAL_CALL_SPEC> {
         ACK_GEN_CALL_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_con.rs b/src/inner/i2c0/ic_con.rs
index 0f2fdde..3d720aa 100644
--- a/src/inner/i2c0/ic_con.rs
+++ b/src/inner/i2c0/ic_con.rs
@@ -57,7 +57,7 @@ where
         self.variant(MASTER_MODE_A::ENABLED)
     }
 }
-#[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1  
+#[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1  
 
 Value on reset: 2"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -80,7 +80,7 @@ impl crate::FieldSpec for SPEED_A {
     type Ux = u8;
 }
 impl crate::IsEnum for SPEED_A {}
-#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
+#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
 pub type SPEED_R = crate::FieldReader<SPEED_A>;
 impl SPEED_R {
     #[doc = "Get enumerated values variant"]
@@ -109,7 +109,7 @@ impl SPEED_R {
         *self == SPEED_A::HIGH
     }
 }
-#[doc = "Field `SPEED` writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
+#[doc = "Field `SPEED` writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
 pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPEED_A>;
 impl<'a, REG> SPEED_W<'a, REG>
 where
@@ -525,7 +525,7 @@ impl R {
     pub fn master_mode(&self) -> MASTER_MODE_R {
         MASTER_MODE_R::new((self.bits & 1) != 0)
     }
-    #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
+    #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
     #[inline(always)]
     pub fn speed(&self) -> SPEED_R {
         SPEED_R::new(((self.bits >> 1) & 3) as u8)
@@ -574,55 +574,46 @@ impl R {
 impl W {
     #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."]
     #[inline(always)]
-    #[must_use]
     pub fn master_mode(&mut self) -> MASTER_MODE_W<IC_CON_SPEC> {
         MASTER_MODE_W::new(self, 0)
     }
-    #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (&lt;=400 kbit/s) or fast mode plus (&lt;=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
+    #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"]
     #[inline(always)]
-    #[must_use]
     pub fn speed(&mut self) -> SPEED_W<IC_CON_SPEC> {
         SPEED_W::new(self, 1)
     }
     #[doc = "Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W<IC_CON_SPEC> {
         IC_10BITADDR_SLAVE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"]
     #[inline(always)]
-    #[must_use]
     pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W<IC_CON_SPEC> {
         IC_10BITADDR_MASTER_W::new(self, 4)
     }
     #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"]
     #[inline(always)]
-    #[must_use]
     pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W<IC_CON_SPEC> {
         IC_RESTART_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W<IC_CON_SPEC> {
         IC_SLAVE_DISABLE_W::new(self, 6)
     }
     #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."]
     #[inline(always)]
-    #[must_use]
     pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W<IC_CON_SPEC> {
         STOP_DET_IFADDRESSED_W::new(self, 7)
     }
     #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W<IC_CON_SPEC> {
         TX_EMPTY_CTRL_W::new(self, 8)
     }
     #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W<IC_CON_SPEC> {
         RX_FIFO_FULL_HLD_CTRL_W::new(self, 9)
     }
diff --git a/src/inner/i2c0/ic_data_cmd.rs b/src/inner/i2c0/ic_data_cmd.rs
index 44916e5..fee2060 100644
--- a/src/inner/i2c0/ic_data_cmd.rs
+++ b/src/inner/i2c0/ic_data_cmd.rs
@@ -167,25 +167,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn dat(&mut self) -> DAT_W<IC_DATA_CMD_SPEC> {
         DAT_W::new(self, 0)
     }
     #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn cmd(&mut self) -> CMD_W<IC_DATA_CMD_SPEC> {
         CMD_W::new(self, 8)
     }
     #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn stop(&mut self) -> STOP_W<IC_DATA_CMD_SPEC> {
         STOP_W::new(self, 9)
     }
     #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn restart(&mut self) -> RESTART_W<IC_DATA_CMD_SPEC> {
         RESTART_W::new(self, 10)
     }
diff --git a/src/inner/i2c0/ic_dma_cr.rs b/src/inner/i2c0/ic_dma_cr.rs
index aa78434..691c134 100644
--- a/src/inner/i2c0/ic_dma_cr.rs
+++ b/src/inner/i2c0/ic_dma_cr.rs
@@ -127,13 +127,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn rdmae(&mut self) -> RDMAE_W<IC_DMA_CR_SPEC> {
         RDMAE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn tdmae(&mut self) -> TDMAE_W<IC_DMA_CR_SPEC> {
         TDMAE_W::new(self, 1)
     }
diff --git a/src/inner/i2c0/ic_dma_rdlr.rs b/src/inner/i2c0/ic_dma_rdlr.rs
index 63d0865..de5b247 100644
--- a/src/inner/i2c0/ic_dma_rdlr.rs
+++ b/src/inner/i2c0/ic_dma_rdlr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn dmardl(&mut self) -> DMARDL_W<IC_DMA_RDLR_SPEC> {
         DMARDL_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_dma_tdlr.rs b/src/inner/i2c0/ic_dma_tdlr.rs
index 58e9d57..b2da39e 100644
--- a/src/inner/i2c0/ic_dma_tdlr.rs
+++ b/src/inner/i2c0/ic_dma_tdlr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn dmatdl(&mut self) -> DMATDL_W<IC_DMA_TDLR_SPEC> {
         DMATDL_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_enable.rs b/src/inner/i2c0/ic_enable.rs
index 6db7477..bab9c7f 100644
--- a/src/inner/i2c0/ic_enable.rs
+++ b/src/inner/i2c0/ic_enable.rs
@@ -191,20 +191,17 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<IC_ENABLE_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn abort(&mut self) -> ABORT_W<IC_ENABLE_SPEC> {
         ABORT_W::new(self, 1)
     }
     #[doc = "Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\]
 == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W<IC_ENABLE_SPEC> {
         TX_CMD_BLOCK_W::new(self, 2)
     }
diff --git a/src/inner/i2c0/ic_fs_scl_hcnt.rs b/src/inner/i2c0/ic_fs_scl_hcnt.rs
index 70135be..30795bd 100644
--- a/src/inner/i2c0/ic_fs_scl_hcnt.rs
+++ b/src/inner/i2c0/ic_fs_scl_hcnt.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
 register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W<IC_FS_SCL_HCNT_SPEC> {
         IC_FS_SCL_HCNT_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_fs_scl_lcnt.rs b/src/inner/i2c0/ic_fs_scl_lcnt.rs
index 5d51387..05d84e4 100644
--- a/src/inner/i2c0/ic_fs_scl_lcnt.rs
+++ b/src/inner/i2c0/ic_fs_scl_lcnt.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
 register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W<IC_FS_SCL_LCNT_SPEC> {
         IC_FS_SCL_LCNT_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_fs_spklen.rs b/src/inner/i2c0/ic_fs_spklen.rs
index a1b185d..403e498 100644
--- a/src/inner/i2c0/ic_fs_spklen.rs
+++ b/src/inner/i2c0/ic_fs_spklen.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:7 - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
 register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_fs_spklen(&mut self) -> IC_FS_SPKLEN_W<IC_FS_SPKLEN_SPEC> {
         IC_FS_SPKLEN_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_intr_mask.rs b/src/inner/i2c0/ic_intr_mask.rs
index ada3994..81b24b4 100644
--- a/src/inner/i2c0/ic_intr_mask.rs
+++ b/src/inner/i2c0/ic_intr_mask.rs
@@ -787,79 +787,66 @@ impl R {
 impl W {
     #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_rx_under(&mut self) -> M_RX_UNDER_W<IC_INTR_MASK_SPEC> {
         M_RX_UNDER_W::new(self, 0)
     }
     #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_rx_over(&mut self) -> M_RX_OVER_W<IC_INTR_MASK_SPEC> {
         M_RX_OVER_W::new(self, 1)
     }
     #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_rx_full(&mut self) -> M_RX_FULL_W<IC_INTR_MASK_SPEC> {
         M_RX_FULL_W::new(self, 2)
     }
     #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_tx_over(&mut self) -> M_TX_OVER_W<IC_INTR_MASK_SPEC> {
         M_TX_OVER_W::new(self, 3)
     }
     #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W<IC_INTR_MASK_SPEC> {
         M_TX_EMPTY_W::new(self, 4)
     }
     #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_rd_req(&mut self) -> M_RD_REQ_W<IC_INTR_MASK_SPEC> {
         M_RD_REQ_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W<IC_INTR_MASK_SPEC> {
         M_TX_ABRT_W::new(self, 6)
     }
     #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_rx_done(&mut self) -> M_RX_DONE_W<IC_INTR_MASK_SPEC> {
         M_RX_DONE_W::new(self, 7)
     }
     #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn m_activity(&mut self) -> M_ACTIVITY_W<IC_INTR_MASK_SPEC> {
         M_ACTIVITY_W::new(self, 8)
     }
     #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn m_stop_det(&mut self) -> M_STOP_DET_W<IC_INTR_MASK_SPEC> {
         M_STOP_DET_W::new(self, 9)
     }
     #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn m_start_det(&mut self) -> M_START_DET_W<IC_INTR_MASK_SPEC> {
         M_START_DET_W::new(self, 10)
     }
     #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"]
     #[inline(always)]
-    #[must_use]
     pub fn m_gen_call(&mut self) -> M_GEN_CALL_W<IC_INTR_MASK_SPEC> {
         M_GEN_CALL_W::new(self, 11)
     }
     #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn m_restart_det(&mut self) -> M_RESTART_DET_W<IC_INTR_MASK_SPEC> {
         M_RESTART_DET_W::new(self, 12)
     }
diff --git a/src/inner/i2c0/ic_rx_tl.rs b/src/inner/i2c0/ic_rx_tl.rs
index 397733a..e82a36e 100644
--- a/src/inner/i2c0/ic_rx_tl.rs
+++ b/src/inner/i2c0/ic_rx_tl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_tl(&mut self) -> RX_TL_W<IC_RX_TL_SPEC> {
         RX_TL_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_sar.rs b/src/inner/i2c0/ic_sar.rs
index eb21c5d..6f0c6e6 100644
--- a/src/inner/i2c0/ic_sar.rs
+++ b/src/inner/i2c0/ic_sar.rs
@@ -4,16 +4,16 @@ pub type R = crate::R<IC_SAR_SPEC>;
 pub type W = crate::W<IC_SAR_SPEC>;
 #[doc = "Field `IC_SAR` reader - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\]
 is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
-register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
+register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
 pub type IC_SAR_R = crate::FieldReader<u16>;
 #[doc = "Field `IC_SAR` writer - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\]
 is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
-register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
+register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
 pub type IC_SAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
 impl R {
     #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\]
 is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
-register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
+register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
     #[inline(always)]
     pub fn ic_sar(&self) -> IC_SAR_R {
         IC_SAR_R::new((self.bits & 0x03ff) as u16)
@@ -22,9 +22,8 @@ register being set to 0. Writes at other times have no effect. Note: The default
 impl W {
     #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\]
 is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\]
-register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to &lt;&lt;table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
+register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_sar(&mut self) -> IC_SAR_W<IC_SAR_SPEC> {
         IC_SAR_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_sda_hold.rs b/src/inner/i2c0/ic_sda_hold.rs
index 881adcd..31da4e5 100644
--- a/src/inner/i2c0/ic_sda_hold.rs
+++ b/src/inner/i2c0/ic_sda_hold.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W<IC_SDA_HOLD_SPEC> {
         IC_SDA_TX_HOLD_W::new(self, 0)
     }
     #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W<IC_SDA_HOLD_SPEC> {
         IC_SDA_RX_HOLD_W::new(self, 16)
     }
diff --git a/src/inner/i2c0/ic_sda_setup.rs b/src/inner/i2c0/ic_sda_setup.rs
index 25058c9..6589521 100644
--- a/src/inner/i2c0/ic_sda_setup.rs
+++ b/src/inner/i2c0/ic_sda_setup.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."]
     #[inline(always)]
-    #[must_use]
     pub fn sda_setup(&mut self) -> SDA_SETUP_W<IC_SDA_SETUP_SPEC> {
         SDA_SETUP_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_slv_data_nack_only.rs b/src/inner/i2c0/ic_slv_data_nack_only.rs
index c5d4d9a..7e41769 100644
--- a/src/inner/i2c0/ic_slv_data_nack_only.rs
+++ b/src/inner/i2c0/ic_slv_data_nack_only.rs
@@ -67,7 +67,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn nack(&mut self) -> NACK_W<IC_SLV_DATA_NACK_ONLY_SPEC> {
         NACK_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_ss_scl_hcnt.rs b/src/inner/i2c0/ic_ss_scl_hcnt.rs
index 805d35a..22bb6d6 100644
--- a/src/inner/i2c0/ic_ss_scl_hcnt.rs
+++ b/src/inner/i2c0/ic_ss_scl_hcnt.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
 register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W<IC_SS_SCL_HCNT_SPEC> {
         IC_SS_SCL_HCNT_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_ss_scl_lcnt.rs b/src/inner/i2c0/ic_ss_scl_lcnt.rs
index a7921e2..18052ee 100644
--- a/src/inner/i2c0/ic_ss_scl_lcnt.rs
+++ b/src/inner/i2c0/ic_ss_scl_lcnt.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\]
 register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W<IC_SS_SCL_LCNT_SPEC> {
         IC_SS_SCL_LCNT_W::new(self, 0)
     }
diff --git a/src/inner/i2c0/ic_tar.rs b/src/inner/i2c0/ic_tar.rs
index 422b10f..2dfa8db 100644
--- a/src/inner/i2c0/ic_tar.rs
+++ b/src/inner/i2c0/ic_tar.rs
@@ -136,19 +136,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."]
     #[inline(always)]
-    #[must_use]
     pub fn ic_tar(&mut self) -> IC_TAR_W<IC_TAR_SPEC> {
         IC_TAR_W::new(self, 0)
     }
     #[doc = "Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn gc_or_start(&mut self) -> GC_OR_START_W<IC_TAR_SPEC> {
         GC_OR_START_W::new(self, 10)
     }
     #[doc = "Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"]
     #[inline(always)]
-    #[must_use]
     pub fn special(&mut self) -> SPECIAL_W<IC_TAR_SPEC> {
         SPECIAL_W::new(self, 11)
     }
diff --git a/src/inner/i2c0/ic_tx_tl.rs b/src/inner/i2c0/ic_tx_tl.rs
index 5cced03..911f2e0 100644
--- a/src/inner/i2c0/ic_tx_tl.rs
+++ b/src/inner/i2c0/ic_tx_tl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_tl(&mut self) -> TX_TL_W<IC_TX_TL_SPEC> {
         TX_TL_W::new(self, 0)
     }
diff --git a/src/inner/io_bank0.rs b/src/inner/io_bank0.rs
index 7523a6e..fb5be0b 100644
--- a/src/inner/io_bank0.rs
+++ b/src/inner/io_bank0.rs
@@ -131,13 +131,13 @@ impl RegisterBlock {
     pub fn proc0_intf_iter(&self) -> impl Iterator<Item = &PROC0_INTF> {
         self.proc0_intf.iter()
     }
-    #[doc = "0x278..0x290 - Interrupt status after masking &amp; forcing for proc0"]
+    #[doc = "0x278..0x290 - Interrupt status after masking & forcing for proc0"]
     #[inline(always)]
     pub const fn proc0_ints(&self, n: usize) -> &PROC0_INTS {
         &self.proc0_ints[n]
     }
     #[doc = "Iterator for array of:"]
-    #[doc = "0x278..0x290 - Interrupt status after masking &amp; forcing for proc0"]
+    #[doc = "0x278..0x290 - Interrupt status after masking & forcing for proc0"]
     #[inline(always)]
     pub fn proc0_ints_iter(&self) -> impl Iterator<Item = &PROC0_INTS> {
         self.proc0_ints.iter()
@@ -164,13 +164,13 @@ impl RegisterBlock {
     pub fn proc1_intf_iter(&self) -> impl Iterator<Item = &PROC1_INTF> {
         self.proc1_intf.iter()
     }
-    #[doc = "0x2c0..0x2d8 - Interrupt status after masking &amp; forcing for proc1"]
+    #[doc = "0x2c0..0x2d8 - Interrupt status after masking & forcing for proc1"]
     #[inline(always)]
     pub const fn proc1_ints(&self, n: usize) -> &PROC1_INTS {
         &self.proc1_ints[n]
     }
     #[doc = "Iterator for array of:"]
-    #[doc = "0x2c0..0x2d8 - Interrupt status after masking &amp; forcing for proc1"]
+    #[doc = "0x2c0..0x2d8 - Interrupt status after masking & forcing for proc1"]
     #[inline(always)]
     pub fn proc1_ints_iter(&self) -> impl Iterator<Item = &PROC1_INTS> {
         self.proc1_ints.iter()
@@ -197,13 +197,13 @@ impl RegisterBlock {
     pub fn dormant_wake_intf_iter(&self) -> impl Iterator<Item = &DORMANT_WAKE_INTF> {
         self.dormant_wake_intf.iter()
     }
-    #[doc = "0x308..0x320 - Interrupt status after masking &amp; forcing for dormant_wake"]
+    #[doc = "0x308..0x320 - Interrupt status after masking & forcing for dormant_wake"]
     #[inline(always)]
     pub const fn dormant_wake_ints(&self, n: usize) -> &DORMANT_WAKE_INTS {
         &self.dormant_wake_ints[n]
     }
     #[doc = "Iterator for array of:"]
-    #[doc = "0x308..0x320 - Interrupt status after masking &amp; forcing for dormant_wake"]
+    #[doc = "0x308..0x320 - Interrupt status after masking & forcing for dormant_wake"]
     #[inline(always)]
     pub fn dormant_wake_ints_iter(&self) -> impl Iterator<Item = &DORMANT_WAKE_INTS> {
         self.dormant_wake_ints.iter()
@@ -361,14 +361,14 @@ module"]
 pub type PROC0_INTF = crate::Reg<proc0_intf::PROC0_INTF_SPEC>;
 #[doc = "Interrupt Force for proc0"]
 pub mod proc0_intf;
-#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for proc0  
+#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking & forcing for proc0  
 
 You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_ints`]
 module"]
 pub type PROC0_INTS = crate::Reg<proc0_ints::PROC0_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for proc0"]
+#[doc = "Interrupt status after masking & forcing for proc0"]
 pub mod proc0_ints;
 #[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1  
 
@@ -388,14 +388,14 @@ module"]
 pub type PROC1_INTF = crate::Reg<proc1_intf::PROC1_INTF_SPEC>;
 #[doc = "Interrupt Force for proc1"]
 pub mod proc1_intf;
-#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for proc1  
+#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking & forcing for proc1  
 
 You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_ints`]
 module"]
 pub type PROC1_INTS = crate::Reg<proc1_ints::PROC1_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for proc1"]
+#[doc = "Interrupt status after masking & forcing for proc1"]
 pub mod proc1_ints;
 #[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake  
 
@@ -415,12 +415,12 @@ module"]
 pub type DORMANT_WAKE_INTF = crate::Reg<dormant_wake_intf::DORMANT_WAKE_INTF_SPEC>;
 #[doc = "Interrupt Force for dormant_wake"]
 pub mod dormant_wake_intf;
-#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for dormant_wake  
+#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking & forcing for dormant_wake  
 
 You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_ints`]
 module"]
 pub type DORMANT_WAKE_INTS = crate::Reg<dormant_wake_ints::DORMANT_WAKE_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for dormant_wake"]
+#[doc = "Interrupt status after masking & forcing for dormant_wake"]
 pub mod dormant_wake_ints;
diff --git a/src/inner/io_bank0/dormant_wake_inte.rs b/src/inner/io_bank0/dormant_wake_inte.rs
index e45d87a..6f1c334 100644
--- a/src/inner/io_bank0/dormant_wake_inte.rs
+++ b/src/inner/io_bank0/dormant_wake_inte.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO0_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO0_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO1_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO1_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO2_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO2_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO3_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO3_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO4_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO4_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO5_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO5_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO6_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO6_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO7_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO7_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/dormant_wake_intf.rs b/src/inner/io_bank0/dormant_wake_intf.rs
index 5a61c16..b3e2124 100644
--- a/src/inner/io_bank0/dormant_wake_intf.rs
+++ b/src/inner/io_bank0/dormant_wake_intf.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO0_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO0_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO1_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO1_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO2_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO2_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO3_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO3_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO4_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO4_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO5_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO5_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO6_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO6_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO7_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO7_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/dormant_wake_ints.rs b/src/inner/io_bank0/dormant_wake_ints.rs
index 375adf7..ed53cfc 100644
--- a/src/inner/io_bank0/dormant_wake_ints.rs
+++ b/src/inner/io_bank0/dormant_wake_ints.rs
@@ -229,7 +229,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for dormant_wake  
+#[doc = "Interrupt status after masking & forcing for dormant_wake  
 
 You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTS_SPEC;
diff --git a/src/inner/io_bank0/gpio/gpio_ctrl.rs b/src/inner/io_bank0/gpio/gpio_ctrl.rs
index bd01066..85c9507 100644
--- a/src/inner/io_bank0/gpio/gpio_ctrl.rs
+++ b/src/inner/io_bank0/gpio/gpio_ctrl.rs
@@ -589,31 +589,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."]
     #[inline(always)]
-    #[must_use]
     pub fn funcsel(&mut self) -> FUNCSEL_W<GPIO_CTRL_SPEC> {
         FUNCSEL_W::new(self, 0)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn outover(&mut self) -> OUTOVER_W<GPIO_CTRL_SPEC> {
         OUTOVER_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn oeover(&mut self) -> OEOVER_W<GPIO_CTRL_SPEC> {
         OEOVER_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn inover(&mut self) -> INOVER_W<GPIO_CTRL_SPEC> {
         INOVER_W::new(self, 16)
     }
     #[doc = "Bits 28:29"]
     #[inline(always)]
-    #[must_use]
     pub fn irqover(&mut self) -> IRQOVER_W<GPIO_CTRL_SPEC> {
         IRQOVER_W::new(self, 28)
     }
diff --git a/src/inner/io_bank0/intr.rs b/src/inner/io_bank0/intr.rs
index 2f2f3f5..c1e63c8 100644
--- a/src/inner/io_bank0/intr.rs
+++ b/src/inner/io_bank0/intr.rs
@@ -263,97 +263,81 @@ impl R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<INTR_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<INTR_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<INTR_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<INTR_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<INTR_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<INTR_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<INTR_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<INTR_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<INTR_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<INTR_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<INTR_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<INTR_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<INTR_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<INTR_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<INTR_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<INTR_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/proc0_inte.rs b/src/inner/io_bank0/proc0_inte.rs
index 39ba86d..46d7bf1 100644
--- a/src/inner/io_bank0/proc0_inte.rs
+++ b/src/inner/io_bank0/proc0_inte.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO0_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO0_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO1_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO1_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO2_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO2_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO3_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO3_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO4_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO4_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO5_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO5_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO6_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO6_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO7_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO7_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/proc0_intf.rs b/src/inner/io_bank0/proc0_intf.rs
index 0ef08c9..899f2d3 100644
--- a/src/inner/io_bank0/proc0_intf.rs
+++ b/src/inner/io_bank0/proc0_intf.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO0_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO0_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO1_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO1_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO2_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO2_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO3_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO3_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO4_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO4_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO5_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO5_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO6_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO6_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO7_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO7_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/proc0_ints.rs b/src/inner/io_bank0/proc0_ints.rs
index 9868be1..2876fc5 100644
--- a/src/inner/io_bank0/proc0_ints.rs
+++ b/src/inner/io_bank0/proc0_ints.rs
@@ -229,7 +229,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for proc0  
+#[doc = "Interrupt status after masking & forcing for proc0  
 
 You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTS_SPEC;
diff --git a/src/inner/io_bank0/proc1_inte.rs b/src/inner/io_bank0/proc1_inte.rs
index 856a70a..c8cc972 100644
--- a/src/inner/io_bank0/proc1_inte.rs
+++ b/src/inner/io_bank0/proc1_inte.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO0_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO0_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO1_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO1_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO2_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO2_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO3_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO3_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO4_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO4_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO5_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO5_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO6_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO6_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO7_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO7_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/proc1_intf.rs b/src/inner/io_bank0/proc1_intf.rs
index 5f8ba20..c1c22d6 100644
--- a/src/inner/io_bank0/proc1_intf.rs
+++ b/src/inner/io_bank0/proc1_intf.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO0_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO0_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO0_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO0_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO1_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO1_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO1_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO1_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO2_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO2_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO2_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO2_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO3_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO3_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO3_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO3_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO4_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO4_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO4_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO4_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO5_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO5_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO5_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO5_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO6_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO6_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO6_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO6_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO7_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO7_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO7_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO7_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_bank0/proc1_ints.rs b/src/inner/io_bank0/proc1_ints.rs
index a9d347a..f706871 100644
--- a/src/inner/io_bank0/proc1_ints.rs
+++ b/src/inner/io_bank0/proc1_ints.rs
@@ -229,7 +229,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for proc1  
+#[doc = "Interrupt status after masking & forcing for proc1  
 
 You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTS_SPEC;
diff --git a/src/inner/io_qspi.rs b/src/inner/io_qspi.rs
index 1f66f36..b23041c 100644
--- a/src/inner/io_qspi.rs
+++ b/src/inner/io_qspi.rs
@@ -46,6 +46,8 @@ impl RegisterBlock {
         &self.usbphy_dm_ctrl
     }
     #[doc = "0x10..0x40 - Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of cluster in the array. `n == 0` corresponds to `GPIO_QSPISCLK` cluster.</div>"]
     #[inline(always)]
     pub const fn gpio_qspi(&self, n: usize) -> &GPIO_QSPI {
         &self.gpio_qspi[n]
@@ -131,7 +133,7 @@ impl RegisterBlock {
     pub const fn proc0_intf(&self) -> &PROC0_INTF {
         &self.proc0_intf
     }
-    #[doc = "0x224 - Interrupt status after masking &amp; forcing for proc0"]
+    #[doc = "0x224 - Interrupt status after masking & forcing for proc0"]
     #[inline(always)]
     pub const fn proc0_ints(&self) -> &PROC0_INTS {
         &self.proc0_ints
@@ -146,7 +148,7 @@ impl RegisterBlock {
     pub const fn proc1_intf(&self) -> &PROC1_INTF {
         &self.proc1_intf
     }
-    #[doc = "0x230 - Interrupt status after masking &amp; forcing for proc1"]
+    #[doc = "0x230 - Interrupt status after masking & forcing for proc1"]
     #[inline(always)]
     pub const fn proc1_ints(&self) -> &PROC1_INTS {
         &self.proc1_ints
@@ -161,7 +163,7 @@ impl RegisterBlock {
     pub const fn dormant_wake_intf(&self) -> &DORMANT_WAKE_INTF {
         &self.dormant_wake_intf
     }
-    #[doc = "0x23c - Interrupt status after masking &amp; forcing for dormant_wake"]
+    #[doc = "0x23c - Interrupt status after masking & forcing for dormant_wake"]
     #[inline(always)]
     pub const fn dormant_wake_ints(&self) -> &DORMANT_WAKE_INTS {
         &self.dormant_wake_ints
@@ -295,14 +297,14 @@ module"]
 pub type PROC0_INTF = crate::Reg<proc0_intf::PROC0_INTF_SPEC>;
 #[doc = "Interrupt Force for proc0"]
 pub mod proc0_intf;
-#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for proc0  
+#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking & forcing for proc0  
 
 You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc0_ints`]
 module"]
 pub type PROC0_INTS = crate::Reg<proc0_ints::PROC0_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for proc0"]
+#[doc = "Interrupt status after masking & forcing for proc0"]
 pub mod proc0_ints;
 #[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1  
 
@@ -322,14 +324,14 @@ module"]
 pub type PROC1_INTF = crate::Reg<proc1_intf::PROC1_INTF_SPEC>;
 #[doc = "Interrupt Force for proc1"]
 pub mod proc1_intf;
-#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for proc1  
+#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking & forcing for proc1  
 
 You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@proc1_ints`]
 module"]
 pub type PROC1_INTS = crate::Reg<proc1_ints::PROC1_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for proc1"]
+#[doc = "Interrupt status after masking & forcing for proc1"]
 pub mod proc1_ints;
 #[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake  
 
@@ -349,12 +351,12 @@ module"]
 pub type DORMANT_WAKE_INTF = crate::Reg<dormant_wake_intf::DORMANT_WAKE_INTF_SPEC>;
 #[doc = "Interrupt Force for dormant_wake"]
 pub mod dormant_wake_intf;
-#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for dormant_wake  
+#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking & forcing for dormant_wake  
 
 You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@dormant_wake_ints`]
 module"]
 pub type DORMANT_WAKE_INTS = crate::Reg<dormant_wake_ints::DORMANT_WAKE_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for dormant_wake"]
+#[doc = "Interrupt status after masking & forcing for dormant_wake"]
 pub mod dormant_wake_ints;
diff --git a/src/inner/io_qspi/dormant_wake_inte.rs b/src/inner/io_qspi/dormant_wake_inte.rs
index ecf4199..7d9a849 100644
--- a/src/inner/io_qspi/dormant_wake_inte.rs
+++ b/src/inner/io_qspi/dormant_wake_inte.rs
@@ -295,55 +295,46 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DP_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DP_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DM_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DM_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_low(
         &mut self,
     ) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
@@ -351,7 +342,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_high(
         &mut self,
     ) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
@@ -359,13 +349,11 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(
         &mut self,
     ) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
@@ -373,37 +361,31 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
@@ -411,25 +393,21 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
@@ -437,25 +415,21 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
@@ -463,25 +437,21 @@ impl W {
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
@@ -489,13 +459,11 @@ impl W {
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<DORMANT_WAKE_INTE_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/dormant_wake_intf.rs b/src/inner/io_qspi/dormant_wake_intf.rs
index 52d970e..6a67b18 100644
--- a/src/inner/io_qspi/dormant_wake_intf.rs
+++ b/src/inner/io_qspi/dormant_wake_intf.rs
@@ -295,55 +295,46 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DP_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DP_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DM_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DM_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_low(
         &mut self,
     ) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
@@ -351,7 +342,6 @@ impl W {
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_high(
         &mut self,
     ) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
@@ -359,13 +349,11 @@ impl W {
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(
         &mut self,
     ) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
@@ -373,37 +361,31 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
@@ -411,25 +393,21 @@ impl W {
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
@@ -437,25 +415,21 @@ impl W {
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
@@ -463,25 +437,21 @@ impl W {
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_high(
         &mut self,
     ) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
@@ -489,13 +459,11 @@ impl W {
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<DORMANT_WAKE_INTF_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/dormant_wake_ints.rs b/src/inner/io_qspi/dormant_wake_ints.rs
index 43ce9d4..8110774 100644
--- a/src/inner/io_qspi/dormant_wake_ints.rs
+++ b/src/inner/io_qspi/dormant_wake_ints.rs
@@ -229,7 +229,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for dormant_wake  
+#[doc = "Interrupt status after masking & forcing for dormant_wake  
 
 You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DORMANT_WAKE_INTS_SPEC;
diff --git a/src/inner/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/inner/io_qspi/gpio_qspi/gpio_ctrl.rs
index 3b471f3..21562b0 100644
--- a/src/inner/io_qspi/gpio_qspi/gpio_ctrl.rs
+++ b/src/inner/io_qspi/gpio_qspi/gpio_ctrl.rs
@@ -498,31 +498,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"]
     #[inline(always)]
-    #[must_use]
     pub fn funcsel(&mut self) -> FUNCSEL_W<GPIO_CTRL_SPEC> {
         FUNCSEL_W::new(self, 0)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn outover(&mut self) -> OUTOVER_W<GPIO_CTRL_SPEC> {
         OUTOVER_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn oeover(&mut self) -> OEOVER_W<GPIO_CTRL_SPEC> {
         OEOVER_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn inover(&mut self) -> INOVER_W<GPIO_CTRL_SPEC> {
         INOVER_W::new(self, 16)
     }
     #[doc = "Bits 28:29"]
     #[inline(always)]
-    #[must_use]
     pub fn irqover(&mut self) -> IRQOVER_W<GPIO_CTRL_SPEC> {
         IRQOVER_W::new(self, 28)
     }
diff --git a/src/inner/io_qspi/intr.rs b/src/inner/io_qspi/intr.rs
index 6c90c16..c355e2a 100644
--- a/src/inner/io_qspi/intr.rs
+++ b/src/inner/io_qspi/intr.rs
@@ -263,97 +263,81 @@ impl R {
 impl W {
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<INTR_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<INTR_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<INTR_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<INTR_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<INTR_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<INTR_SPEC> {
         GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<INTR_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<INTR_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<INTR_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<INTR_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<INTR_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<INTR_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<INTR_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<INTR_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<INTR_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<INTR_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/proc0_inte.rs b/src/inner/io_qspi/proc0_inte.rs
index 7e8fef5..69e024c 100644
--- a/src/inner/io_qspi/proc0_inte.rs
+++ b/src/inner/io_qspi/proc0_inte.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         USBPHY_DP_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         USBPHY_DP_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<PROC0_INTE_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         USBPHY_DM_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         USBPHY_DM_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<PROC0_INTE_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<PROC0_INTE_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/proc0_intf.rs b/src/inner/io_qspi/proc0_intf.rs
index 7ce9453..1a7a084 100644
--- a/src/inner/io_qspi/proc0_intf.rs
+++ b/src/inner/io_qspi/proc0_intf.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         USBPHY_DP_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         USBPHY_DP_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<PROC0_INTF_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         USBPHY_DM_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         USBPHY_DM_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<PROC0_INTF_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<PROC0_INTF_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/proc0_ints.rs b/src/inner/io_qspi/proc0_ints.rs
index 36a6907..16e266a 100644
--- a/src/inner/io_qspi/proc0_ints.rs
+++ b/src/inner/io_qspi/proc0_ints.rs
@@ -229,7 +229,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for proc0  
+#[doc = "Interrupt status after masking & forcing for proc0  
 
 You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC0_INTS_SPEC;
diff --git a/src/inner/io_qspi/proc1_inte.rs b/src/inner/io_qspi/proc1_inte.rs
index 0000418..f6b59ac 100644
--- a/src/inner/io_qspi/proc1_inte.rs
+++ b/src/inner/io_qspi/proc1_inte.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         USBPHY_DP_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         USBPHY_DP_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<PROC1_INTE_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         USBPHY_DM_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         USBPHY_DM_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<PROC1_INTE_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<PROC1_INTE_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/proc1_intf.rs b/src/inner/io_qspi/proc1_intf.rs
index 83e2586..bdc5559 100644
--- a/src/inner/io_qspi/proc1_intf.rs
+++ b/src/inner/io_qspi/proc1_intf.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         USBPHY_DP_LEVEL_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         USBPHY_DP_LEVEL_HIGH_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W<PROC1_INTF_SPEC> {
         USBPHY_DP_EDGE_LOW_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         USBPHY_DP_EDGE_HIGH_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         USBPHY_DM_LEVEL_LOW_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         USBPHY_DM_LEVEL_HIGH_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W<PROC1_INTF_SPEC> {
         USBPHY_DM_EDGE_LOW_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         USBPHY_DM_EDGE_HIGH_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W<PROC1_INTF_SPEC> {
         GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31)
     }
diff --git a/src/inner/io_qspi/proc1_ints.rs b/src/inner/io_qspi/proc1_ints.rs
index a0854b7..fa63816 100644
--- a/src/inner/io_qspi/proc1_ints.rs
+++ b/src/inner/io_qspi/proc1_ints.rs
@@ -229,7 +229,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for proc1  
+#[doc = "Interrupt status after masking & forcing for proc1  
 
 You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PROC1_INTS_SPEC;
diff --git a/src/inner/io_qspi/usbphy_dm_ctrl.rs b/src/inner/io_qspi/usbphy_dm_ctrl.rs
index bbe3e13..1720bfb 100644
--- a/src/inner/io_qspi/usbphy_dm_ctrl.rs
+++ b/src/inner/io_qspi/usbphy_dm_ctrl.rs
@@ -472,31 +472,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"]
     #[inline(always)]
-    #[must_use]
     pub fn funcsel(&mut self) -> FUNCSEL_W<USBPHY_DM_CTRL_SPEC> {
         FUNCSEL_W::new(self, 0)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn outover(&mut self) -> OUTOVER_W<USBPHY_DM_CTRL_SPEC> {
         OUTOVER_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn oeover(&mut self) -> OEOVER_W<USBPHY_DM_CTRL_SPEC> {
         OEOVER_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn inover(&mut self) -> INOVER_W<USBPHY_DM_CTRL_SPEC> {
         INOVER_W::new(self, 16)
     }
     #[doc = "Bits 28:29"]
     #[inline(always)]
-    #[must_use]
     pub fn irqover(&mut self) -> IRQOVER_W<USBPHY_DM_CTRL_SPEC> {
         IRQOVER_W::new(self, 28)
     }
diff --git a/src/inner/io_qspi/usbphy_dp_ctrl.rs b/src/inner/io_qspi/usbphy_dp_ctrl.rs
index d65f0e1..5fcdbee 100644
--- a/src/inner/io_qspi/usbphy_dp_ctrl.rs
+++ b/src/inner/io_qspi/usbphy_dp_ctrl.rs
@@ -472,31 +472,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"]
     #[inline(always)]
-    #[must_use]
     pub fn funcsel(&mut self) -> FUNCSEL_W<USBPHY_DP_CTRL_SPEC> {
         FUNCSEL_W::new(self, 0)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn outover(&mut self) -> OUTOVER_W<USBPHY_DP_CTRL_SPEC> {
         OUTOVER_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn oeover(&mut self) -> OEOVER_W<USBPHY_DP_CTRL_SPEC> {
         OEOVER_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn inover(&mut self) -> INOVER_W<USBPHY_DP_CTRL_SPEC> {
         INOVER_W::new(self, 16)
     }
     #[doc = "Bits 28:29"]
     #[inline(always)]
-    #[must_use]
     pub fn irqover(&mut self) -> IRQOVER_W<USBPHY_DP_CTRL_SPEC> {
         IRQOVER_W::new(self, 28)
     }
diff --git a/src/inner/mod_cortex_m.rs b/src/inner/mod_cortex_m.rs
index e68bda7..5ad8700 100644
--- a/src/inner/mod_cortex_m.rs
+++ b/src/inner/mod_cortex_m.rs
@@ -1,11 +1,11 @@
-#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.33.4 ( ))  
+#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.35.0 ( ))  
 
 You can find an overview of the generated API [here].  
 
 API features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.  
 
-[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api  
+[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api  
 [next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased  
 [repository]: https://github.com/rust-embedded/svd2rust"]
 use core::marker::PhantomData;
@@ -1564,7 +1564,7 @@ impl core::fmt::Debug for POWMAN {
         f.debug_struct("POWMAN").finish()
     }
 }
-#[doc = "Controls vreg, bor, lposc, chip resets &amp; xosc startup, powman and provides scratch register for general use and for bootcode use"]
+#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"]
 pub mod powman;
 #[doc = "WATCHDOG"]
 pub struct WATCHDOG {
@@ -1702,7 +1702,7 @@ impl core::fmt::Debug for TIMER0 {
         f.debug_struct("TIMER0").finish()
     }
 }
-#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time &amp; timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
+#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
 pub mod timer0;
 #[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
 pub struct TIMER1 {
diff --git a/src/inner/mod_risc_v.rs b/src/inner/mod_risc_v.rs
index c20489a..c6d4d96 100644
--- a/src/inner/mod_risc_v.rs
+++ b/src/inner/mod_risc_v.rs
@@ -1,11 +1,11 @@
-#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.33.4 ( ))  
+#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.35.0 ( ))  
 
 You can find an overview of the generated API [here].  
 
 API features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.  
 
-[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api  
+[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api  
 [next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased  
 [repository]: https://github.com/rust-embedded/svd2rust"]
 use core::marker::PhantomData;
@@ -1451,7 +1451,7 @@ impl core::fmt::Debug for POWMAN {
         f.debug_struct("POWMAN").finish()
     }
 }
-#[doc = "Controls vreg, bor, lposc, chip resets &amp; xosc startup, powman and provides scratch register for general use and for bootcode use"]
+#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"]
 pub mod powman;
 #[doc = "WATCHDOG"]
 pub struct WATCHDOG {
@@ -1589,7 +1589,7 @@ impl core::fmt::Debug for TIMER0 {
         f.debug_struct("TIMER0").finish()
     }
 }
-#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time &amp; timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
+#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
 pub mod timer0;
 #[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"]
 pub struct TIMER1 {
diff --git a/src/inner/otp.rs b/src/inner/otp.rs
index bff12c6..e68b7ea 100644
--- a/src/inner/otp.rs
+++ b/src/inner/otp.rs
@@ -551,7 +551,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0x170 - Interrupt status after masking &amp; forcing"]
+    #[doc = "0x170 - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -1376,12 +1376,12 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
diff --git a/src/inner/otp/archsel.rs b/src/inner/otp/archsel.rs
index 53ab19d..73a02ba 100644
--- a/src/inner/otp/archsel.rs
+++ b/src/inner/otp/archsel.rs
@@ -127,13 +127,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Select architecture for core 0."]
     #[inline(always)]
-    #[must_use]
     pub fn core0(&mut self) -> CORE0_W<ARCHSEL_SPEC> {
         CORE0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Select architecture for core 1."]
     #[inline(always)]
-    #[must_use]
     pub fn core1(&mut self) -> CORE1_W<ARCHSEL_SPEC> {
         CORE1_W::new(self, 1)
     }
diff --git a/src/inner/otp/bist.rs b/src/inner/otp/bist.rs
index 88a8215..4ca4e18 100644
--- a/src/inner/otp/bist.rs
+++ b/src/inner/otp/bist.rs
@@ -41,19 +41,16 @@ impl R {
 impl W {
     #[doc = "Bits 16:27 - The cnt_fail flag will be set if the number of leaky locations exceeds this number"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_max(&mut self) -> CNT_MAX_W<BIST_SPEC> {
         CNT_MAX_W::new(self, 16)
     }
     #[doc = "Bit 28 - Enable the counter before the BIST function is initiated"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_ena(&mut self) -> CNT_ENA_W<BIST_SPEC> {
         CNT_ENA_W::new(self, 28)
     }
     #[doc = "Bit 29 - Clear counter before use"]
     #[inline(always)]
-    #[must_use]
     pub fn cnt_clr(&mut self) -> CNT_CLR_W<BIST_SPEC> {
         CNT_CLR_W::new(self, 29)
     }
diff --git a/src/inner/otp/bootdis.rs b/src/inner/otp/bootdis.rs
index 146170d..f3d2049 100644
--- a/src/inner/otp/bootdis.rs
+++ b/src/inner/otp/bootdis.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."]
     #[inline(always)]
-    #[must_use]
     pub fn now(&mut self) -> NOW_W<BOOTDIS_SPEC> {
         NOW_W::new(self, 0)
     }
     #[doc = "Bit 1 - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."]
     #[inline(always)]
-    #[must_use]
     pub fn next(&mut self) -> NEXT_W<BOOTDIS_SPEC> {
         NEXT_W::new(self, 1)
     }
diff --git a/src/inner/otp/crt_key_w0.rs b/src/inner/otp/crt_key_w0.rs
index 2195623..f1679d8 100644
--- a/src/inner/otp/crt_key_w0.rs
+++ b/src/inner/otp/crt_key_w0.rs
@@ -7,7 +7,6 @@ pub type CRT_KEY_W0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn crt_key_w0(&mut self) -> CRT_KEY_W0_W<CRT_KEY_W0_SPEC> {
         CRT_KEY_W0_W::new(self, 0)
     }
diff --git a/src/inner/otp/crt_key_w1.rs b/src/inner/otp/crt_key_w1.rs
index ba5b52f..dc1a36b 100644
--- a/src/inner/otp/crt_key_w1.rs
+++ b/src/inner/otp/crt_key_w1.rs
@@ -7,7 +7,6 @@ pub type CRT_KEY_W1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn crt_key_w1(&mut self) -> CRT_KEY_W1_W<CRT_KEY_W1_SPEC> {
         CRT_KEY_W1_W::new(self, 0)
     }
diff --git a/src/inner/otp/crt_key_w2.rs b/src/inner/otp/crt_key_w2.rs
index bafc4e8..ff593b5 100644
--- a/src/inner/otp/crt_key_w2.rs
+++ b/src/inner/otp/crt_key_w2.rs
@@ -7,7 +7,6 @@ pub type CRT_KEY_W2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn crt_key_w2(&mut self) -> CRT_KEY_W2_W<CRT_KEY_W2_SPEC> {
         CRT_KEY_W2_W::new(self, 0)
     }
diff --git a/src/inner/otp/crt_key_w3.rs b/src/inner/otp/crt_key_w3.rs
index 96bfc83..8aa7d02 100644
--- a/src/inner/otp/crt_key_w3.rs
+++ b/src/inner/otp/crt_key_w3.rs
@@ -7,7 +7,6 @@ pub type CRT_KEY_W3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn crt_key_w3(&mut self) -> CRT_KEY_W3_W<CRT_KEY_W3_SPEC> {
         CRT_KEY_W3_W::new(self, 0)
     }
diff --git a/src/inner/otp/dbg.rs b/src/inner/otp/dbg.rs
index fc4ccb9..5cb9db4 100644
--- a/src/inner/otp/dbg.rs
+++ b/src/inner/otp/dbg.rs
@@ -51,7 +51,6 @@ impl R {
 impl W {
     #[doc = "Bit 2 - Ring oscillator was seen up and running"]
     #[inline(always)]
-    #[must_use]
     pub fn rosc_up_seen(&mut self) -> ROSC_UP_SEEN_W<DBG_SPEC> {
         ROSC_UP_SEEN_W::new(self, 2)
     }
diff --git a/src/inner/otp/debugen.rs b/src/inner/otp/debugen.rs
index 1fc1224..bccfec9 100644
--- a/src/inner/otp/debugen.rs
+++ b/src/inner/otp/debugen.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."]
     #[inline(always)]
-    #[must_use]
     pub fn proc0(&mut self) -> PROC0_W<DEBUGEN_SPEC> {
         PROC0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."]
     #[inline(always)]
-    #[must_use]
     pub fn proc0_secure(&mut self) -> PROC0_SECURE_W<DEBUGEN_SPEC> {
         PROC0_SECURE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."]
     #[inline(always)]
-    #[must_use]
     pub fn proc1(&mut self) -> PROC1_W<DEBUGEN_SPEC> {
         PROC1_W::new(self, 2)
     }
     #[doc = "Bit 3 - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."]
     #[inline(always)]
-    #[must_use]
     pub fn proc1_secure(&mut self) -> PROC1_SECURE_W<DEBUGEN_SPEC> {
         PROC1_SECURE_W::new(self, 3)
     }
     #[doc = "Bit 8 - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."]
     #[inline(always)]
-    #[must_use]
     pub fn misc(&mut self) -> MISC_W<DEBUGEN_SPEC> {
         MISC_W::new(self, 8)
     }
diff --git a/src/inner/otp/debugen_lock.rs b/src/inner/otp/debugen_lock.rs
index d797316..ef8d021 100644
--- a/src/inner/otp/debugen_lock.rs
+++ b/src/inner/otp/debugen_lock.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."]
     #[inline(always)]
-    #[must_use]
     pub fn proc0(&mut self) -> PROC0_W<DEBUGEN_LOCK_SPEC> {
         PROC0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."]
     #[inline(always)]
-    #[must_use]
     pub fn proc0_secure(&mut self) -> PROC0_SECURE_W<DEBUGEN_LOCK_SPEC> {
         PROC0_SECURE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."]
     #[inline(always)]
-    #[must_use]
     pub fn proc1(&mut self) -> PROC1_W<DEBUGEN_LOCK_SPEC> {
         PROC1_W::new(self, 2)
     }
     #[doc = "Bit 3 - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."]
     #[inline(always)]
-    #[must_use]
     pub fn proc1_secure(&mut self) -> PROC1_SECURE_W<DEBUGEN_LOCK_SPEC> {
         PROC1_SECURE_W::new(self, 3)
     }
     #[doc = "Bit 8 - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."]
     #[inline(always)]
-    #[must_use]
     pub fn misc(&mut self) -> MISC_W<DEBUGEN_LOCK_SPEC> {
         MISC_W::new(self, 8)
     }
diff --git a/src/inner/otp/inte.rs b/src/inner/otp/inte.rs
index e73c279..70b5fa7 100644
--- a/src/inner/otp/inte.rs
+++ b/src/inner/otp/inte.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_flag_n(&mut self) -> SBPI_FLAG_N_W<INTE_SPEC> {
         SBPI_FLAG_N_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wr_fail(&mut self) -> SBPI_WR_FAIL_W<INTE_SPEC> {
         SBPI_WR_FAIL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_dctrl_fail(&mut self) -> APB_DCTRL_FAIL_W<INTE_SPEC> {
         APB_DCTRL_FAIL_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_rd_sec_fail(&mut self) -> APB_RD_SEC_FAIL_W<INTE_SPEC> {
         APB_RD_SEC_FAIL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_rd_nsec_fail(&mut self) -> APB_RD_NSEC_FAIL_W<INTE_SPEC> {
         APB_RD_NSEC_FAIL_W::new(self, 4)
     }
diff --git a/src/inner/otp/intf.rs b/src/inner/otp/intf.rs
index fa7dbef..d37fd3e 100644
--- a/src/inner/otp/intf.rs
+++ b/src/inner/otp/intf.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_flag_n(&mut self) -> SBPI_FLAG_N_W<INTF_SPEC> {
         SBPI_FLAG_N_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wr_fail(&mut self) -> SBPI_WR_FAIL_W<INTF_SPEC> {
         SBPI_WR_FAIL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_dctrl_fail(&mut self) -> APB_DCTRL_FAIL_W<INTF_SPEC> {
         APB_DCTRL_FAIL_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_rd_sec_fail(&mut self) -> APB_RD_SEC_FAIL_W<INTF_SPEC> {
         APB_RD_SEC_FAIL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_rd_nsec_fail(&mut self) -> APB_RD_NSEC_FAIL_W<INTF_SPEC> {
         APB_RD_NSEC_FAIL_W::new(self, 4)
     }
diff --git a/src/inner/otp/intr.rs b/src/inner/otp/intr.rs
index 9e388e6..8743021 100644
--- a/src/inner/otp/intr.rs
+++ b/src/inner/otp/intr.rs
@@ -50,25 +50,21 @@ impl R {
 impl W {
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wr_fail(&mut self) -> SBPI_WR_FAIL_W<INTR_SPEC> {
         SBPI_WR_FAIL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_dctrl_fail(&mut self) -> APB_DCTRL_FAIL_W<INTR_SPEC> {
         APB_DCTRL_FAIL_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_rd_sec_fail(&mut self) -> APB_RD_SEC_FAIL_W<INTR_SPEC> {
         APB_RD_SEC_FAIL_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn apb_rd_nsec_fail(&mut self) -> APB_RD_NSEC_FAIL_W<INTR_SPEC> {
         APB_RD_NSEC_FAIL_W::new(self, 4)
     }
diff --git a/src/inner/otp/ints.rs b/src/inner/otp/ints.rs
index f0aa769..1629a7f 100644
--- a/src/inner/otp/ints.rs
+++ b/src/inner/otp/ints.rs
@@ -40,7 +40,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/otp/sbpi_instr.rs b/src/inner/otp/sbpi_instr.rs
index 716c9e5..c405575 100644
--- a/src/inner/otp/sbpi_instr.rs
+++ b/src/inner/otp/sbpi_instr.rs
@@ -63,43 +63,36 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - wdata to be used only when payload_size_m1=0"]
     #[inline(always)]
-    #[must_use]
     pub fn short_wdata(&mut self) -> SHORT_WDATA_W<SBPI_INSTR_SPEC> {
         SHORT_WDATA_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn cmd(&mut self) -> CMD_W<SBPI_INSTR_SPEC> {
         CMD_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - Instruction target, it can be PMC (0x3a) or DAP (0x02)"]
     #[inline(always)]
-    #[must_use]
     pub fn target(&mut self) -> TARGET_W<SBPI_INSTR_SPEC> {
         TARGET_W::new(self, 16)
     }
     #[doc = "Bits 24:27 - Instruction payload size in bytes minus 1"]
     #[inline(always)]
-    #[must_use]
     pub fn payload_size_m1(&mut self) -> PAYLOAD_SIZE_M1_W<SBPI_INSTR_SPEC> {
         PAYLOAD_SIZE_M1_W::new(self, 24)
     }
     #[doc = "Bit 28 - Instruction has payload (data to be written or to be read)"]
     #[inline(always)]
-    #[must_use]
     pub fn has_payload(&mut self) -> HAS_PAYLOAD_W<SBPI_INSTR_SPEC> {
         HAS_PAYLOAD_W::new(self, 28)
     }
     #[doc = "Bit 29 - Payload type is write"]
     #[inline(always)]
-    #[must_use]
     pub fn is_wr(&mut self) -> IS_WR_W<SBPI_INSTR_SPEC> {
         IS_WR_W::new(self, 29)
     }
     #[doc = "Bit 30 - Execute instruction"]
     #[inline(always)]
-    #[must_use]
     pub fn exec(&mut self) -> EXEC_W<SBPI_INSTR_SPEC> {
         EXEC_W::new(self, 30)
     }
diff --git a/src/inner/otp/sbpi_status.rs b/src/inner/otp/sbpi_status.rs
index ea382fe..25c6288 100644
--- a/src/inner/otp/sbpi_status.rs
+++ b/src/inner/otp/sbpi_status.rs
@@ -48,19 +48,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Read command has returned data"]
     #[inline(always)]
-    #[must_use]
     pub fn rdata_vld(&mut self) -> RDATA_VLD_W<SBPI_STATUS_SPEC> {
         RDATA_VLD_W::new(self, 0)
     }
     #[doc = "Bit 4 - Last instruction done"]
     #[inline(always)]
-    #[must_use]
     pub fn instr_done(&mut self) -> INSTR_DONE_W<SBPI_STATUS_SPEC> {
         INSTR_DONE_W::new(self, 4)
     }
     #[doc = "Bit 8 - Last instruction missed (dropped), as the previous has not finished running"]
     #[inline(always)]
-    #[must_use]
     pub fn instr_miss(&mut self) -> INSTR_MISS_W<SBPI_STATUS_SPEC> {
         INSTR_MISS_W::new(self, 8)
     }
diff --git a/src/inner/otp/sbpi_wdata_0.rs b/src/inner/otp/sbpi_wdata_0.rs
index 1411320..a7df8fa 100644
--- a/src/inner/otp/sbpi_wdata_0.rs
+++ b/src/inner/otp/sbpi_wdata_0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wdata_0(&mut self) -> SBPI_WDATA_0_W<SBPI_WDATA_0_SPEC> {
         SBPI_WDATA_0_W::new(self, 0)
     }
diff --git a/src/inner/otp/sbpi_wdata_1.rs b/src/inner/otp/sbpi_wdata_1.rs
index 176463d..3776962 100644
--- a/src/inner/otp/sbpi_wdata_1.rs
+++ b/src/inner/otp/sbpi_wdata_1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wdata_1(&mut self) -> SBPI_WDATA_1_W<SBPI_WDATA_1_SPEC> {
         SBPI_WDATA_1_W::new(self, 0)
     }
diff --git a/src/inner/otp/sbpi_wdata_2.rs b/src/inner/otp/sbpi_wdata_2.rs
index 96eb9e7..b265aff 100644
--- a/src/inner/otp/sbpi_wdata_2.rs
+++ b/src/inner/otp/sbpi_wdata_2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wdata_2(&mut self) -> SBPI_WDATA_2_W<SBPI_WDATA_2_SPEC> {
         SBPI_WDATA_2_W::new(self, 0)
     }
diff --git a/src/inner/otp/sbpi_wdata_3.rs b/src/inner/otp/sbpi_wdata_3.rs
index dcddcf4..353a950 100644
--- a/src/inner/otp/sbpi_wdata_3.rs
+++ b/src/inner/otp/sbpi_wdata_3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn sbpi_wdata_3(&mut self) -> SBPI_WDATA_3_W<SBPI_WDATA_3_SPEC> {
         SBPI_WDATA_3_W::new(self, 0)
     }
diff --git a/src/inner/otp/sw_lock0.rs b/src/inner/otp/sw_lock0.rs
index 94ebb95..98d4e7b 100644
--- a/src/inner/otp/sw_lock0.rs
+++ b/src/inner/otp/sw_lock0.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK0_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK0_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock1.rs b/src/inner/otp/sw_lock1.rs
index 64b2448..2cf35bd 100644
--- a/src/inner/otp/sw_lock1.rs
+++ b/src/inner/otp/sw_lock1.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK1_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK1_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock10.rs b/src/inner/otp/sw_lock10.rs
index e35ca2e..3162dda 100644
--- a/src/inner/otp/sw_lock10.rs
+++ b/src/inner/otp/sw_lock10.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK10_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK10_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock11.rs b/src/inner/otp/sw_lock11.rs
index 4d010d7..003109f 100644
--- a/src/inner/otp/sw_lock11.rs
+++ b/src/inner/otp/sw_lock11.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK11_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK11_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock12.rs b/src/inner/otp/sw_lock12.rs
index 49970ac..5e35beb 100644
--- a/src/inner/otp/sw_lock12.rs
+++ b/src/inner/otp/sw_lock12.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK12_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK12_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock13.rs b/src/inner/otp/sw_lock13.rs
index cb6fab4..6b13034 100644
--- a/src/inner/otp/sw_lock13.rs
+++ b/src/inner/otp/sw_lock13.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK13_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK13_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock14.rs b/src/inner/otp/sw_lock14.rs
index fa6719f..74b5fd6 100644
--- a/src/inner/otp/sw_lock14.rs
+++ b/src/inner/otp/sw_lock14.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK14_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK14_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock15.rs b/src/inner/otp/sw_lock15.rs
index 60942e5..56aecb3 100644
--- a/src/inner/otp/sw_lock15.rs
+++ b/src/inner/otp/sw_lock15.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK15_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK15_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock16.rs b/src/inner/otp/sw_lock16.rs
index cfdd136..a668be2 100644
--- a/src/inner/otp/sw_lock16.rs
+++ b/src/inner/otp/sw_lock16.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK16_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK16_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock17.rs b/src/inner/otp/sw_lock17.rs
index 50c0d89..7aab86b 100644
--- a/src/inner/otp/sw_lock17.rs
+++ b/src/inner/otp/sw_lock17.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK17_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK17_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock18.rs b/src/inner/otp/sw_lock18.rs
index 867dec7..e74bab8 100644
--- a/src/inner/otp/sw_lock18.rs
+++ b/src/inner/otp/sw_lock18.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK18_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK18_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock19.rs b/src/inner/otp/sw_lock19.rs
index 7cc1fdc..4626fd0 100644
--- a/src/inner/otp/sw_lock19.rs
+++ b/src/inner/otp/sw_lock19.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK19_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK19_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock2.rs b/src/inner/otp/sw_lock2.rs
index 93bfc34..ef2dfdc 100644
--- a/src/inner/otp/sw_lock2.rs
+++ b/src/inner/otp/sw_lock2.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK2_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK2_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock20.rs b/src/inner/otp/sw_lock20.rs
index 2e5eceb..1c766a0 100644
--- a/src/inner/otp/sw_lock20.rs
+++ b/src/inner/otp/sw_lock20.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK20_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK20_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock21.rs b/src/inner/otp/sw_lock21.rs
index 7cacb78..6d2e246 100644
--- a/src/inner/otp/sw_lock21.rs
+++ b/src/inner/otp/sw_lock21.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK21_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK21_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock22.rs b/src/inner/otp/sw_lock22.rs
index 92ed34c..fd210ef 100644
--- a/src/inner/otp/sw_lock22.rs
+++ b/src/inner/otp/sw_lock22.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK22_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK22_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock23.rs b/src/inner/otp/sw_lock23.rs
index 32e0f3b..4c02261 100644
--- a/src/inner/otp/sw_lock23.rs
+++ b/src/inner/otp/sw_lock23.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK23_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK23_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock24.rs b/src/inner/otp/sw_lock24.rs
index b666367..4e518b5 100644
--- a/src/inner/otp/sw_lock24.rs
+++ b/src/inner/otp/sw_lock24.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK24_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK24_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock25.rs b/src/inner/otp/sw_lock25.rs
index 7b62245..fd79467 100644
--- a/src/inner/otp/sw_lock25.rs
+++ b/src/inner/otp/sw_lock25.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK25_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK25_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock26.rs b/src/inner/otp/sw_lock26.rs
index 2f8729b..e99f7a2 100644
--- a/src/inner/otp/sw_lock26.rs
+++ b/src/inner/otp/sw_lock26.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK26_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK26_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock27.rs b/src/inner/otp/sw_lock27.rs
index aa2a4b9..9b0120e 100644
--- a/src/inner/otp/sw_lock27.rs
+++ b/src/inner/otp/sw_lock27.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK27_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK27_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock28.rs b/src/inner/otp/sw_lock28.rs
index c59bb04..8ec9871 100644
--- a/src/inner/otp/sw_lock28.rs
+++ b/src/inner/otp/sw_lock28.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK28_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK28_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock29.rs b/src/inner/otp/sw_lock29.rs
index 0696f3a..ef85f5d 100644
--- a/src/inner/otp/sw_lock29.rs
+++ b/src/inner/otp/sw_lock29.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK29_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK29_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock3.rs b/src/inner/otp/sw_lock3.rs
index 3d3d18a..f341c8d 100644
--- a/src/inner/otp/sw_lock3.rs
+++ b/src/inner/otp/sw_lock3.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK3_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK3_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock30.rs b/src/inner/otp/sw_lock30.rs
index 27294ca..639fdd6 100644
--- a/src/inner/otp/sw_lock30.rs
+++ b/src/inner/otp/sw_lock30.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK30_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK30_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock31.rs b/src/inner/otp/sw_lock31.rs
index 3960221..099e098 100644
--- a/src/inner/otp/sw_lock31.rs
+++ b/src/inner/otp/sw_lock31.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK31_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK31_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock32.rs b/src/inner/otp/sw_lock32.rs
index 9d45d0a..484c9a8 100644
--- a/src/inner/otp/sw_lock32.rs
+++ b/src/inner/otp/sw_lock32.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK32_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK32_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock33.rs b/src/inner/otp/sw_lock33.rs
index 57d8b89..44d775b 100644
--- a/src/inner/otp/sw_lock33.rs
+++ b/src/inner/otp/sw_lock33.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK33_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK33_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock34.rs b/src/inner/otp/sw_lock34.rs
index eb0bdc1..5622c9e 100644
--- a/src/inner/otp/sw_lock34.rs
+++ b/src/inner/otp/sw_lock34.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK34_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK34_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock35.rs b/src/inner/otp/sw_lock35.rs
index 20d358d..6a0da1b 100644
--- a/src/inner/otp/sw_lock35.rs
+++ b/src/inner/otp/sw_lock35.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK35_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK35_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock36.rs b/src/inner/otp/sw_lock36.rs
index 35a2c63..ea3ff19 100644
--- a/src/inner/otp/sw_lock36.rs
+++ b/src/inner/otp/sw_lock36.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK36_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK36_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock37.rs b/src/inner/otp/sw_lock37.rs
index a2edd82..85b6b86 100644
--- a/src/inner/otp/sw_lock37.rs
+++ b/src/inner/otp/sw_lock37.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK37_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK37_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock38.rs b/src/inner/otp/sw_lock38.rs
index c5cb425..55c76cf 100644
--- a/src/inner/otp/sw_lock38.rs
+++ b/src/inner/otp/sw_lock38.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK38_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK38_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock39.rs b/src/inner/otp/sw_lock39.rs
index 1371539..e25f0aa 100644
--- a/src/inner/otp/sw_lock39.rs
+++ b/src/inner/otp/sw_lock39.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK39_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK39_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock4.rs b/src/inner/otp/sw_lock4.rs
index 29f789c..b9bfb11 100644
--- a/src/inner/otp/sw_lock4.rs
+++ b/src/inner/otp/sw_lock4.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK4_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK4_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock40.rs b/src/inner/otp/sw_lock40.rs
index 27bbfca..82fdc23 100644
--- a/src/inner/otp/sw_lock40.rs
+++ b/src/inner/otp/sw_lock40.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK40_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK40_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock41.rs b/src/inner/otp/sw_lock41.rs
index 365c9e1..e14b436 100644
--- a/src/inner/otp/sw_lock41.rs
+++ b/src/inner/otp/sw_lock41.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK41_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK41_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock42.rs b/src/inner/otp/sw_lock42.rs
index ac0e129..124657e 100644
--- a/src/inner/otp/sw_lock42.rs
+++ b/src/inner/otp/sw_lock42.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK42_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK42_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock43.rs b/src/inner/otp/sw_lock43.rs
index b5d100c..b4f9bab 100644
--- a/src/inner/otp/sw_lock43.rs
+++ b/src/inner/otp/sw_lock43.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK43_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK43_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock44.rs b/src/inner/otp/sw_lock44.rs
index 98cfb47..5efad55 100644
--- a/src/inner/otp/sw_lock44.rs
+++ b/src/inner/otp/sw_lock44.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK44_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK44_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock45.rs b/src/inner/otp/sw_lock45.rs
index 75339b5..bd9e15d 100644
--- a/src/inner/otp/sw_lock45.rs
+++ b/src/inner/otp/sw_lock45.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK45_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK45_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock46.rs b/src/inner/otp/sw_lock46.rs
index 85ee5f9..22acece 100644
--- a/src/inner/otp/sw_lock46.rs
+++ b/src/inner/otp/sw_lock46.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK46_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK46_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock47.rs b/src/inner/otp/sw_lock47.rs
index 5dae091..6f78277 100644
--- a/src/inner/otp/sw_lock47.rs
+++ b/src/inner/otp/sw_lock47.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK47_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK47_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock48.rs b/src/inner/otp/sw_lock48.rs
index b1e9fea..01d23d7 100644
--- a/src/inner/otp/sw_lock48.rs
+++ b/src/inner/otp/sw_lock48.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK48_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK48_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock49.rs b/src/inner/otp/sw_lock49.rs
index a652e79..04f1bfc 100644
--- a/src/inner/otp/sw_lock49.rs
+++ b/src/inner/otp/sw_lock49.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK49_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK49_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock5.rs b/src/inner/otp/sw_lock5.rs
index fc13fda..a535f88 100644
--- a/src/inner/otp/sw_lock5.rs
+++ b/src/inner/otp/sw_lock5.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK5_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK5_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock50.rs b/src/inner/otp/sw_lock50.rs
index 123aac0..3777c43 100644
--- a/src/inner/otp/sw_lock50.rs
+++ b/src/inner/otp/sw_lock50.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK50_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK50_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock51.rs b/src/inner/otp/sw_lock51.rs
index f4f488a..d4ae211 100644
--- a/src/inner/otp/sw_lock51.rs
+++ b/src/inner/otp/sw_lock51.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK51_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK51_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock52.rs b/src/inner/otp/sw_lock52.rs
index 31d0a15..f34c055 100644
--- a/src/inner/otp/sw_lock52.rs
+++ b/src/inner/otp/sw_lock52.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK52_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK52_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock53.rs b/src/inner/otp/sw_lock53.rs
index d6606bb..2baafe6 100644
--- a/src/inner/otp/sw_lock53.rs
+++ b/src/inner/otp/sw_lock53.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK53_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK53_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock54.rs b/src/inner/otp/sw_lock54.rs
index dbdc1da..9ab2641 100644
--- a/src/inner/otp/sw_lock54.rs
+++ b/src/inner/otp/sw_lock54.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK54_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK54_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock55.rs b/src/inner/otp/sw_lock55.rs
index e04ad54..55f4cd0 100644
--- a/src/inner/otp/sw_lock55.rs
+++ b/src/inner/otp/sw_lock55.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK55_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK55_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock56.rs b/src/inner/otp/sw_lock56.rs
index 61bf3aa..fdbbe7c 100644
--- a/src/inner/otp/sw_lock56.rs
+++ b/src/inner/otp/sw_lock56.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK56_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK56_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock57.rs b/src/inner/otp/sw_lock57.rs
index 3f44a54..0c91ea8 100644
--- a/src/inner/otp/sw_lock57.rs
+++ b/src/inner/otp/sw_lock57.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK57_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK57_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock58.rs b/src/inner/otp/sw_lock58.rs
index 142defe..7ee5205 100644
--- a/src/inner/otp/sw_lock58.rs
+++ b/src/inner/otp/sw_lock58.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK58_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK58_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock59.rs b/src/inner/otp/sw_lock59.rs
index fa3ee62..0a3f085 100644
--- a/src/inner/otp/sw_lock59.rs
+++ b/src/inner/otp/sw_lock59.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK59_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK59_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock6.rs b/src/inner/otp/sw_lock6.rs
index ea688a4..848a9bf 100644
--- a/src/inner/otp/sw_lock6.rs
+++ b/src/inner/otp/sw_lock6.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK6_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK6_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock60.rs b/src/inner/otp/sw_lock60.rs
index 0662c2f..c28b503 100644
--- a/src/inner/otp/sw_lock60.rs
+++ b/src/inner/otp/sw_lock60.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK60_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK60_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock61.rs b/src/inner/otp/sw_lock61.rs
index 5325984..5d2fb58 100644
--- a/src/inner/otp/sw_lock61.rs
+++ b/src/inner/otp/sw_lock61.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK61_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK61_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock62.rs b/src/inner/otp/sw_lock62.rs
index 00e0833..73898a7 100644
--- a/src/inner/otp/sw_lock62.rs
+++ b/src/inner/otp/sw_lock62.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK62_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK62_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock63.rs b/src/inner/otp/sw_lock63.rs
index 68f4759..2508572 100644
--- a/src/inner/otp/sw_lock63.rs
+++ b/src/inner/otp/sw_lock63.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK63_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK63_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock7.rs b/src/inner/otp/sw_lock7.rs
index add90c3..9ca6d32 100644
--- a/src/inner/otp/sw_lock7.rs
+++ b/src/inner/otp/sw_lock7.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK7_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK7_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock8.rs b/src/inner/otp/sw_lock8.rs
index 70a87e4..0915723 100644
--- a/src/inner/otp/sw_lock8.rs
+++ b/src/inner/otp/sw_lock8.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK8_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK8_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/sw_lock9.rs b/src/inner/otp/sw_lock9.rs
index 32367b3..c9571a6 100644
--- a/src/inner/otp/sw_lock9.rs
+++ b/src/inner/otp/sw_lock9.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn sec(&mut self) -> SEC_W<SW_LOCK9_SPEC> {
         SEC_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."]
     #[inline(always)]
-    #[must_use]
     pub fn nsec(&mut self) -> NSEC_W<SW_LOCK9_SPEC> {
         NSEC_W::new(self, 2)
     }
diff --git a/src/inner/otp/usr.rs b/src/inner/otp/usr.rs
index 493bf78..cdce0c2 100644
--- a/src/inner/otp/usr.rs
+++ b/src/inner/otp/usr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - 1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."]
     #[inline(always)]
-    #[must_use]
     pub fn dctrl(&mut self) -> DCTRL_W<USR_SPEC> {
         DCTRL_W::new(self, 0)
     }
     #[doc = "Bit 4 - Power-down; 1 disables current reference. Must be 0 to read data from the OTP."]
     #[inline(always)]
-    #[must_use]
     pub fn pd(&mut self) -> PD_W<USR_SPEC> {
         PD_W::new(self, 4)
     }
diff --git a/src/inner/otp_data/flash_devinfo.rs b/src/inner/otp_data/flash_devinfo.rs
index 0823f87..831f7e7 100644
--- a/src/inner/otp_data/flash_devinfo.rs
+++ b/src/inner/otp_data/flash_devinfo.rs
@@ -6,7 +6,7 @@ pub type W = crate::W<FLASH_DEVINFO_SPEC>;
 pub type CS1_GPIO_R = crate::FieldReader;
 #[doc = "Field `D8H_ERASE_SUPPORTED` reader - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."]
 pub type D8H_ERASE_SUPPORTED_R = crate::BitReader;
-#[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.  
+#[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -49,7 +49,7 @@ impl crate::FieldSpec for CS0_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for CS0_SIZE_A {}
-#[doc = "Field `CS0_SIZE` reader - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+#[doc = "Field `CS0_SIZE` reader - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
 pub type CS0_SIZE_R = crate::FieldReader<CS0_SIZE_A>;
 impl CS0_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -138,7 +138,7 @@ impl CS0_SIZE_R {
         *self == CS0_SIZE_A::_16M
     }
 }
-#[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.  
+#[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -181,7 +181,7 @@ impl crate::FieldSpec for CS1_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for CS1_SIZE_A {}
-#[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+#[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
 pub type CS1_SIZE_R = crate::FieldReader<CS1_SIZE_A>;
 impl CS1_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -281,12 +281,12 @@ impl R {
     pub fn d8h_erase_supported(&self) -> D8H_ERASE_SUPPORTED_R {
         D8H_ERASE_SUPPORTED_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bits 8:11 - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+    #[doc = "Bits 8:11 - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
     #[inline(always)]
     pub fn cs0_size(&self) -> CS0_SIZE_R {
         CS0_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8)
     }
-    #[doc = "Bits 12:15 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+    #[doc = "Bits 12:15 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
     #[inline(always)]
     pub fn cs1_size(&self) -> CS1_SIZE_R {
         CS1_SIZE_R::new(((self.bits >> 12) & 0x0f) as u8)
diff --git a/src/inner/otp_data_raw/flash_devinfo.rs b/src/inner/otp_data_raw/flash_devinfo.rs
index fdd9cf6..8d105f8 100644
--- a/src/inner/otp_data_raw/flash_devinfo.rs
+++ b/src/inner/otp_data_raw/flash_devinfo.rs
@@ -6,7 +6,7 @@ pub type W = crate::W<FLASH_DEVINFO_SPEC>;
 pub type CS1_GPIO_R = crate::FieldReader;
 #[doc = "Field `D8H_ERASE_SUPPORTED` reader - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."]
 pub type D8H_ERASE_SUPPORTED_R = crate::BitReader;
-#[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.  
+#[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -49,7 +49,7 @@ impl crate::FieldSpec for CS0_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for CS0_SIZE_A {}
-#[doc = "Field `CS0_SIZE` reader - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+#[doc = "Field `CS0_SIZE` reader - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
 pub type CS0_SIZE_R = crate::FieldReader<CS0_SIZE_A>;
 impl CS0_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -138,7 +138,7 @@ impl CS0_SIZE_R {
         *self == CS0_SIZE_A::_16M
     }
 }
-#[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.  
+#[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.  
 
 Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -181,7 +181,7 @@ impl crate::FieldSpec for CS1_SIZE_A {
     type Ux = u8;
 }
 impl crate::IsEnum for CS1_SIZE_A {}
-#[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+#[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
 pub type CS1_SIZE_R = crate::FieldReader<CS1_SIZE_A>;
 impl CS1_SIZE_R {
     #[doc = "Get enumerated values variant"]
@@ -281,12 +281,12 @@ impl R {
     pub fn d8h_erase_supported(&self) -> D8H_ERASE_SUPPORTED_R {
         D8H_ERASE_SUPPORTED_R::new(((self.bits >> 7) & 1) != 0)
     }
-    #[doc = "Bits 8:11 - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
+    #[doc = "Bits 8:11 - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."]
     #[inline(always)]
     pub fn cs0_size(&self) -> CS0_SIZE_R {
         CS0_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8)
     }
-    #[doc = "Bits 12:15 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB &lt;&lt; CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
+    #[doc = "Bits 12:15 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."]
     #[inline(always)]
     pub fn cs1_size(&self) -> CS1_SIZE_R {
         CS1_SIZE_R::new(((self.bits >> 12) & 0x0f) as u8)
diff --git a/src/inner/pads_bank0/gpio.rs b/src/inner/pads_bank0/gpio.rs
index 2bd7256..ac177ea 100644
--- a/src/inner/pads_bank0/gpio.rs
+++ b/src/inner/pads_bank0/gpio.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_bank0/swclk.rs b/src/inner/pads_bank0/swclk.rs
index 1b30c9b..3600006 100644
--- a/src/inner/pads_bank0/swclk.rs
+++ b/src/inner/pads_bank0/swclk.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<SWCLK_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<SWCLK_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<SWCLK_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<SWCLK_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<SWCLK_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<SWCLK_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<SWCLK_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<SWCLK_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_bank0/swd.rs b/src/inner/pads_bank0/swd.rs
index 20e0e80..4408905 100644
--- a/src/inner/pads_bank0/swd.rs
+++ b/src/inner/pads_bank0/swd.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<SWD_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<SWD_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<SWD_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<SWD_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<SWD_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<SWD_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<SWD_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<SWD_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_bank0/voltage_select.rs b/src/inner/pads_bank0/voltage_select.rs
index f9c428e..e8817e5 100644
--- a/src/inner/pads_bank0/voltage_select.rs
+++ b/src/inner/pads_bank0/voltage_select.rs
@@ -9,7 +9,7 @@ Value on reset: 0"]
 pub enum VOLTAGE_SELECT_A {
     #[doc = "0: Set voltage to 3.3V (DVDD >= 2V5)"]
     _3V3 = 0,
-    #[doc = "1: Set voltage to 1.8V (DVDD &lt;= 1V8)"]
+    #[doc = "1: Set voltage to 1.8V (DVDD <= 1V8)"]
     _1V8 = 1,
 }
 impl From<VOLTAGE_SELECT_A> for bool {
@@ -34,7 +34,7 @@ impl VOLTAGE_SELECT_R {
     pub fn is_3v3(&self) -> bool {
         *self == VOLTAGE_SELECT_A::_3V3
     }
-    #[doc = "Set voltage to 1.8V (DVDD &lt;= 1V8)"]
+    #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"]
     #[inline(always)]
     pub fn is_1v8(&self) -> bool {
         *self == VOLTAGE_SELECT_A::_1V8
@@ -51,7 +51,7 @@ where
     pub fn _3v3(self) -> &'a mut crate::W<REG> {
         self.variant(VOLTAGE_SELECT_A::_3V3)
     }
-    #[doc = "Set voltage to 1.8V (DVDD &lt;= 1V8)"]
+    #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"]
     #[inline(always)]
     pub fn _1v8(self) -> &'a mut crate::W<REG> {
         self.variant(VOLTAGE_SELECT_A::_1V8)
@@ -67,7 +67,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W<VOLTAGE_SELECT_SPEC> {
         VOLTAGE_SELECT_W::new(self, 0)
     }
diff --git a/src/inner/pads_qspi/gpio_qspi_sclk.rs b/src/inner/pads_qspi/gpio_qspi_sclk.rs
index b890100..3b0679f 100644
--- a/src/inner/pads_qspi/gpio_qspi_sclk.rs
+++ b/src/inner/pads_qspi/gpio_qspi_sclk.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SCLK_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SCLK_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SCLK_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SCLK_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SCLK_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SCLK_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_QSPI_SCLK_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_QSPI_SCLK_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_qspi/gpio_qspi_sd0.rs b/src/inner/pads_qspi/gpio_qspi_sd0.rs
index 038428d..5dcd8c3 100644
--- a/src/inner/pads_qspi/gpio_qspi_sd0.rs
+++ b/src/inner/pads_qspi/gpio_qspi_sd0.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SD0_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SD0_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SD0_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SD0_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SD0_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SD0_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_QSPI_SD0_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_QSPI_SD0_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_qspi/gpio_qspi_sd1.rs b/src/inner/pads_qspi/gpio_qspi_sd1.rs
index acc1d2f..55bfbd1 100644
--- a/src/inner/pads_qspi/gpio_qspi_sd1.rs
+++ b/src/inner/pads_qspi/gpio_qspi_sd1.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SD1_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SD1_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SD1_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SD1_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SD1_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SD1_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_QSPI_SD1_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_QSPI_SD1_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_qspi/gpio_qspi_sd2.rs b/src/inner/pads_qspi/gpio_qspi_sd2.rs
index d137828..2eb60d0 100644
--- a/src/inner/pads_qspi/gpio_qspi_sd2.rs
+++ b/src/inner/pads_qspi/gpio_qspi_sd2.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SD2_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SD2_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SD2_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SD2_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SD2_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SD2_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_QSPI_SD2_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_QSPI_SD2_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_qspi/gpio_qspi_sd3.rs b/src/inner/pads_qspi/gpio_qspi_sd3.rs
index 6a1dfe1..7ed0a7e 100644
--- a/src/inner/pads_qspi/gpio_qspi_sd3.rs
+++ b/src/inner/pads_qspi/gpio_qspi_sd3.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SD3_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SD3_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SD3_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SD3_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SD3_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SD3_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_QSPI_SD3_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_QSPI_SD3_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_qspi/gpio_qspi_ss.rs b/src/inner/pads_qspi/gpio_qspi_ss.rs
index 1059658..6bf88ca 100644
--- a/src/inner/pads_qspi/gpio_qspi_ss.rs
+++ b/src/inner/pads_qspi/gpio_qspi_ss.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"]
     #[inline(always)]
-    #[must_use]
     pub fn slewfast(&mut self) -> SLEWFAST_W<GPIO_QSPI_SS_SPEC> {
         SLEWFAST_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable schmitt trigger"]
     #[inline(always)]
-    #[must_use]
     pub fn schmitt(&mut self) -> SCHMITT_W<GPIO_QSPI_SS_SPEC> {
         SCHMITT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pde(&mut self) -> PDE_W<GPIO_QSPI_SS_SPEC> {
         PDE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn pue(&mut self) -> PUE_W<GPIO_QSPI_SS_SPEC> {
         PUE_W::new(self, 3)
     }
     #[doc = "Bits 4:5 - Drive strength."]
     #[inline(always)]
-    #[must_use]
     pub fn drive(&mut self) -> DRIVE_W<GPIO_QSPI_SS_SPEC> {
         DRIVE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Input enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ie(&mut self) -> IE_W<GPIO_QSPI_SS_SPEC> {
         IE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"]
     #[inline(always)]
-    #[must_use]
     pub fn od(&mut self) -> OD_W<GPIO_QSPI_SS_SPEC> {
         OD_W::new(self, 7)
     }
     #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."]
     #[inline(always)]
-    #[must_use]
     pub fn iso(&mut self) -> ISO_W<GPIO_QSPI_SS_SPEC> {
         ISO_W::new(self, 8)
     }
diff --git a/src/inner/pads_qspi/voltage_select.rs b/src/inner/pads_qspi/voltage_select.rs
index f9c428e..e8817e5 100644
--- a/src/inner/pads_qspi/voltage_select.rs
+++ b/src/inner/pads_qspi/voltage_select.rs
@@ -9,7 +9,7 @@ Value on reset: 0"]
 pub enum VOLTAGE_SELECT_A {
     #[doc = "0: Set voltage to 3.3V (DVDD >= 2V5)"]
     _3V3 = 0,
-    #[doc = "1: Set voltage to 1.8V (DVDD &lt;= 1V8)"]
+    #[doc = "1: Set voltage to 1.8V (DVDD <= 1V8)"]
     _1V8 = 1,
 }
 impl From<VOLTAGE_SELECT_A> for bool {
@@ -34,7 +34,7 @@ impl VOLTAGE_SELECT_R {
     pub fn is_3v3(&self) -> bool {
         *self == VOLTAGE_SELECT_A::_3V3
     }
-    #[doc = "Set voltage to 1.8V (DVDD &lt;= 1V8)"]
+    #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"]
     #[inline(always)]
     pub fn is_1v8(&self) -> bool {
         *self == VOLTAGE_SELECT_A::_1V8
@@ -51,7 +51,7 @@ where
     pub fn _3v3(self) -> &'a mut crate::W<REG> {
         self.variant(VOLTAGE_SELECT_A::_3V3)
     }
-    #[doc = "Set voltage to 1.8V (DVDD &lt;= 1V8)"]
+    #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"]
     #[inline(always)]
     pub fn _1v8(self) -> &'a mut crate::W<REG> {
         self.variant(VOLTAGE_SELECT_A::_1V8)
@@ -67,7 +67,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W<VOLTAGE_SELECT_SPEC> {
         VOLTAGE_SELECT_W::new(self, 0)
     }
diff --git a/src/inner/pio0/ctrl.rs b/src/inner/pio0/ctrl.rs
index cbabfc5..9491475 100644
--- a/src/inner/pio0/ctrl.rs
+++ b/src/inner/pio0/ctrl.rs
@@ -30,49 +30,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."]
     #[inline(always)]
-    #[must_use]
     pub fn sm_enable(&mut self) -> SM_ENABLE_W<CTRL_SPEC> {
         SM_ENABLE_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The contents of the output shift register and the X/Y scratch registers are not affected."]
     #[inline(always)]
-    #[must_use]
     pub fn sm_restart(&mut self) -> SM_RESTART_W<CTRL_SPEC> {
         SM_RESTART_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W<CTRL_SPEC> {
         CLKDIV_RESTART_W::new(self, 8)
     }
     #[doc = "Bits 16:19 - A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."]
     #[inline(always)]
-    #[must_use]
     pub fn prev_pio_mask(&mut self) -> PREV_PIO_MASK_W<CTRL_SPEC> {
         PREV_PIO_MASK_W::new(self, 16)
     }
     #[doc = "Bits 20:23 - A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."]
     #[inline(always)]
-    #[must_use]
     pub fn next_pio_mask(&mut self) -> NEXT_PIO_MASK_W<CTRL_SPEC> {
         NEXT_PIO_MASK_W::new(self, 20)
     }
     #[doc = "Bit 24 - Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence."]
     #[inline(always)]
-    #[must_use]
     pub fn nextprev_sm_enable(&mut self) -> NEXTPREV_SM_ENABLE_W<CTRL_SPEC> {
         NEXTPREV_SM_ENABLE_W::new(self, 24)
     }
     #[doc = "Bit 25 - Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers."]
     #[inline(always)]
-    #[must_use]
     pub fn nextprev_sm_disable(&mut self) -> NEXTPREV_SM_DISABLE_W<CTRL_SPEC> {
         NEXTPREV_SM_DISABLE_W::new(self, 25)
     }
     #[doc = "Bit 26 - Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers."]
     #[inline(always)]
-    #[must_use]
     pub fn nextprev_clkdiv_restart(&mut self) -> NEXTPREV_CLKDIV_RESTART_W<CTRL_SPEC> {
         NEXTPREV_CLKDIV_RESTART_W::new(self, 26)
     }
diff --git a/src/inner/pio0/fdebug.rs b/src/inner/pio0/fdebug.rs
index cd1ea56..0a72164 100644
--- a/src/inner/pio0/fdebug.rs
+++ b/src/inner/pio0/fdebug.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn rxstall(&mut self) -> RXSTALL_W<FDEBUG_SPEC> {
         RXSTALL_W::new(self, 0)
     }
     #[doc = "Bits 8:11 - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."]
     #[inline(always)]
-    #[must_use]
     pub fn rxunder(&mut self) -> RXUNDER_W<FDEBUG_SPEC> {
         RXUNDER_W::new(self, 8)
     }
     #[doc = "Bits 16:19 - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."]
     #[inline(always)]
-    #[must_use]
     pub fn txover(&mut self) -> TXOVER_W<FDEBUG_SPEC> {
         TXOVER_W::new(self, 16)
     }
     #[doc = "Bits 24:27 - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn txstall(&mut self) -> TXSTALL_W<FDEBUG_SPEC> {
         TXSTALL_W::new(self, 24)
     }
diff --git a/src/inner/pio0/gpiobase.rs b/src/inner/pio0/gpiobase.rs
index 4860515..eec465c 100644
--- a/src/inner/pio0/gpiobase.rs
+++ b/src/inner/pio0/gpiobase.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn gpiobase(&mut self) -> GPIOBASE_W<GPIOBASE_SPEC> {
         GPIOBASE_W::new(self, 4)
     }
diff --git a/src/inner/pio0/input_sync_bypass.rs b/src/inner/pio0/input_sync_bypass.rs
index 0522b72..1580723 100644
--- a/src/inner/pio0/input_sync_bypass.rs
+++ b/src/inner/pio0/input_sync_bypass.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn input_sync_bypass(&mut self) -> INPUT_SYNC_BYPASS_W<INPUT_SYNC_BYPASS_SPEC> {
         INPUT_SYNC_BYPASS_W::new(self, 0)
     }
diff --git a/src/inner/pio0/instr_mem.rs b/src/inner/pio0/instr_mem.rs
index b2d023f..c310b65 100644
--- a/src/inner/pio0/instr_mem.rs
+++ b/src/inner/pio0/instr_mem.rs
@@ -7,7 +7,6 @@ pub type INSTR_MEM0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn instr_mem0(&mut self) -> INSTR_MEM0_W<INSTR_MEM_SPEC> {
         INSTR_MEM0_W::new(self, 0)
     }
diff --git a/src/inner/pio0/irq.rs b/src/inner/pio0/irq.rs
index 5353a28..bc02aa6 100644
--- a/src/inner/pio0/irq.rs
+++ b/src/inner/pio0/irq.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn irq(&mut self) -> IRQ_W<IRQ_SPEC> {
         IRQ_W::new(self, 0)
     }
diff --git a/src/inner/pio0/irq_force.rs b/src/inner/pio0/irq_force.rs
index 33887dd..a20f61f 100644
--- a/src/inner/pio0/irq_force.rs
+++ b/src/inner/pio0/irq_force.rs
@@ -7,7 +7,6 @@ pub type IRQ_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn irq_force(&mut self) -> IRQ_FORCE_W<IRQ_FORCE_SPEC> {
         IRQ_FORCE_W::new(self, 0)
     }
diff --git a/src/inner/pio0/rxf0_putget.rs b/src/inner/pio0/rxf0_putget.rs
index 124d16e..ce890d9 100644
--- a/src/inner/pio0/rxf0_putget.rs
+++ b/src/inner/pio0/rxf0_putget.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rxf0_putget0(&mut self) -> RXF0_PUTGET0_W<RXF0_PUTGET_SPEC> {
         RXF0_PUTGET0_W::new(self, 0)
     }
diff --git a/src/inner/pio0/rxf1_putget.rs b/src/inner/pio0/rxf1_putget.rs
index 77ab90b..e1b49d8 100644
--- a/src/inner/pio0/rxf1_putget.rs
+++ b/src/inner/pio0/rxf1_putget.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rxf1_putget0(&mut self) -> RXF1_PUTGET0_W<RXF1_PUTGET_SPEC> {
         RXF1_PUTGET0_W::new(self, 0)
     }
diff --git a/src/inner/pio0/rxf2_putget.rs b/src/inner/pio0/rxf2_putget.rs
index 4fa9dc1..9a04c16 100644
--- a/src/inner/pio0/rxf2_putget.rs
+++ b/src/inner/pio0/rxf2_putget.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rxf2_putget0(&mut self) -> RXF2_PUTGET0_W<RXF2_PUTGET_SPEC> {
         RXF2_PUTGET0_W::new(self, 0)
     }
diff --git a/src/inner/pio0/rxf3_putget.rs b/src/inner/pio0/rxf3_putget.rs
index 045d903..f547155 100644
--- a/src/inner/pio0/rxf3_putget.rs
+++ b/src/inner/pio0/rxf3_putget.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn rxf3_putget0(&mut self) -> RXF3_PUTGET0_W<RXF3_PUTGET_SPEC> {
         RXF3_PUTGET0_W::new(self, 0)
     }
diff --git a/src/inner/pio0/sm/sm_clkdiv.rs b/src/inner/pio0/sm/sm_clkdiv.rs
index d9ac3bd..1fb9606 100644
--- a/src/inner/pio0/sm/sm_clkdiv.rs
+++ b/src/inner/pio0/sm/sm_clkdiv.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 8:15 - Fractional part of clock divisor"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<SM_CLKDIV_SPEC> {
         FRAC_W::new(self, 8)
     }
     #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<SM_CLKDIV_SPEC> {
         INT_W::new(self, 16)
     }
diff --git a/src/inner/pio0/sm/sm_execctrl.rs b/src/inner/pio0/sm/sm_execctrl.rs
index bfe17df..84a9f4a 100644
--- a/src/inner/pio0/sm/sm_execctrl.rs
+++ b/src/inner/pio0/sm/sm_execctrl.rs
@@ -83,9 +83,9 @@ Value on reset: 0"]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum STATUS_SEL_A {
-    #[doc = "0: All-ones if TX FIFO level &lt; N, otherwise all-zeroes"]
+    #[doc = "0: All-ones if TX FIFO level < N, otherwise all-zeroes"]
     TXLEVEL = 0,
-    #[doc = "1: All-ones if RX FIFO level &lt; N, otherwise all-zeroes"]
+    #[doc = "1: All-ones if RX FIFO level < N, otherwise all-zeroes"]
     RXLEVEL = 1,
     #[doc = "2: All-ones if the indexed IRQ flag is raised, otherwise all-zeroes"]
     IRQ = 2,
@@ -113,12 +113,12 @@ impl STATUS_SEL_R {
             _ => None,
         }
     }
-    #[doc = "All-ones if TX FIFO level &lt; N, otherwise all-zeroes"]
+    #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"]
     #[inline(always)]
     pub fn is_txlevel(&self) -> bool {
         *self == STATUS_SEL_A::TXLEVEL
     }
-    #[doc = "All-ones if RX FIFO level &lt; N, otherwise all-zeroes"]
+    #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"]
     #[inline(always)]
     pub fn is_rxlevel(&self) -> bool {
         *self == STATUS_SEL_A::RXLEVEL
@@ -136,12 +136,12 @@ where
     REG: crate::Writable + crate::RegisterSpec,
     REG::Ux: From<u8>,
 {
-    #[doc = "All-ones if TX FIFO level &lt; N, otherwise all-zeroes"]
+    #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"]
     #[inline(always)]
     pub fn txlevel(self) -> &'a mut crate::W<REG> {
         self.variant(STATUS_SEL_A::TXLEVEL)
     }
-    #[doc = "All-ones if RX FIFO level &lt; N, otherwise all-zeroes"]
+    #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"]
     #[inline(always)]
     pub fn rxlevel(self) -> &'a mut crate::W<REG> {
         self.variant(STATUS_SEL_A::RXLEVEL)
@@ -164,9 +164,9 @@ pub type WRAP_TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 pub type OUT_STICKY_R = crate::BitReader;
 #[doc = "Field `OUT_STICKY` writer - Continuously assert the most recent OUT/SET to the pins"]
 pub type OUT_STICKY_W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
+#[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
 pub type INLINE_OUT_EN_R = crate::BitReader;
-#[doc = "Field `INLINE_OUT_EN` writer - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
+#[doc = "Field `INLINE_OUT_EN` writer - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
 pub type INLINE_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `OUT_EN_SEL` reader - Which data bit to use for inline OUT enable"]
 pub type OUT_EN_SEL_R = crate::FieldReader;
@@ -212,7 +212,7 @@ impl R {
     pub fn out_sticky(&self) -> OUT_STICKY_R {
         OUT_STICKY_R::new(((self.bits >> 17) & 1) != 0)
     }
-    #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
+    #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
     #[inline(always)]
     pub fn inline_out_en(&self) -> INLINE_OUT_EN_R {
         INLINE_OUT_EN_R::new(((self.bits >> 18) & 1) != 0)
@@ -246,61 +246,51 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."]
     #[inline(always)]
-    #[must_use]
     pub fn status_n(&mut self) -> STATUS_N_W<SM_EXECCTRL_SPEC> {
         STATUS_N_W::new(self, 0)
     }
     #[doc = "Bits 5:6 - Comparison used for the MOV x, STATUS instruction."]
     #[inline(always)]
-    #[must_use]
     pub fn status_sel(&mut self) -> STATUS_SEL_W<SM_EXECCTRL_SPEC> {
         STATUS_SEL_W::new(self, 5)
     }
     #[doc = "Bits 7:11 - After reaching wrap_top, execution is wrapped to this address."]
     #[inline(always)]
-    #[must_use]
     pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W<SM_EXECCTRL_SPEC> {
         WRAP_BOTTOM_W::new(self, 7)
     }
     #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."]
     #[inline(always)]
-    #[must_use]
     pub fn wrap_top(&mut self) -> WRAP_TOP_W<SM_EXECCTRL_SPEC> {
         WRAP_TOP_W::new(self, 12)
     }
     #[doc = "Bit 17 - Continuously assert the most recent OUT/SET to the pins"]
     #[inline(always)]
-    #[must_use]
     pub fn out_sticky(&mut self) -> OUT_STICKY_W<SM_EXECCTRL_SPEC> {
         OUT_STICKY_W::new(self, 17)
     }
-    #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 &lt; SM1 &lt; ...)"]
+    #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"]
     #[inline(always)]
-    #[must_use]
     pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W<SM_EXECCTRL_SPEC> {
         INLINE_OUT_EN_W::new(self, 18)
     }
     #[doc = "Bits 19:23 - Which data bit to use for inline OUT enable"]
     #[inline(always)]
-    #[must_use]
     pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W<SM_EXECCTRL_SPEC> {
         OUT_EN_SEL_W::new(self, 19)
     }
     #[doc = "Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."]
     #[inline(always)]
-    #[must_use]
     pub fn jmp_pin(&mut self) -> JMP_PIN_W<SM_EXECCTRL_SPEC> {
         JMP_PIN_W::new(self, 24)
     }
     #[doc = "Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values"]
     #[inline(always)]
-    #[must_use]
     pub fn side_pindir(&mut self) -> SIDE_PINDIR_W<SM_EXECCTRL_SPEC> {
         SIDE_PINDIR_W::new(self, 29)
     }
     #[doc = "Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."]
     #[inline(always)]
-    #[must_use]
     pub fn side_en(&mut self) -> SIDE_EN_W<SM_EXECCTRL_SPEC> {
         SIDE_EN_W::new(self, 30)
     }
diff --git a/src/inner/pio0/sm/sm_instr.rs b/src/inner/pio0/sm/sm_instr.rs
index 431ff6a..180376a 100644
--- a/src/inner/pio0/sm/sm_instr.rs
+++ b/src/inner/pio0/sm/sm_instr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0_instr(&mut self) -> SM0_INSTR_W<SM_INSTR_SPEC> {
         SM0_INSTR_W::new(self, 0)
     }
diff --git a/src/inner/pio0/sm/sm_pinctrl.rs b/src/inner/pio0/sm/sm_pinctrl.rs
index 23664f1..d703443 100644
--- a/src/inner/pio0/sm/sm_pinctrl.rs
+++ b/src/inner/pio0/sm/sm_pinctrl.rs
@@ -70,43 +70,36 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."]
     #[inline(always)]
-    #[must_use]
     pub fn out_base(&mut self) -> OUT_BASE_W<SM_PINCTRL_SPEC> {
         OUT_BASE_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."]
     #[inline(always)]
-    #[must_use]
     pub fn set_base(&mut self) -> SET_BASE_W<SM_PINCTRL_SPEC> {
         SET_BASE_W::new(self, 5)
     }
     #[doc = "Bits 10:14 - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."]
     #[inline(always)]
-    #[must_use]
     pub fn sideset_base(&mut self) -> SIDESET_BASE_W<SM_PINCTRL_SPEC> {
         SIDESET_BASE_W::new(self, 10)
     }
     #[doc = "Bits 15:19 - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."]
     #[inline(always)]
-    #[must_use]
     pub fn in_base(&mut self) -> IN_BASE_W<SM_PINCTRL_SPEC> {
         IN_BASE_W::new(self, 15)
     }
     #[doc = "Bits 20:25 - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."]
     #[inline(always)]
-    #[must_use]
     pub fn out_count(&mut self) -> OUT_COUNT_W<SM_PINCTRL_SPEC> {
         OUT_COUNT_W::new(self, 20)
     }
     #[doc = "Bits 26:28 - The number of pins asserted by a SET. In the range 0 to 5 inclusive."]
     #[inline(always)]
-    #[must_use]
     pub fn set_count(&mut self) -> SET_COUNT_W<SM_PINCTRL_SPEC> {
         SET_COUNT_W::new(self, 26)
     }
     #[doc = "Bits 29:31 - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."]
     #[inline(always)]
-    #[must_use]
     pub fn sideset_count(&mut self) -> SIDESET_COUNT_W<SM_PINCTRL_SPEC> {
         SIDESET_COUNT_W::new(self, 29)
     }
diff --git a/src/inner/pio0/sm/sm_shiftctrl.rs b/src/inner/pio0/sm/sm_shiftctrl.rs
index cc25b7b..ec9c39c 100644
--- a/src/inner/pio0/sm/sm_shiftctrl.rs
+++ b/src/inner/pio0/sm/sm_shiftctrl.rs
@@ -106,67 +106,56 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."]
     #[inline(always)]
-    #[must_use]
     pub fn in_count(&mut self) -> IN_COUNT_W<SM_SHIFTCTRL_SPEC> {
         IN_COUNT_W::new(self, 0)
     }
     #[doc = "Bit 14 - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."]
     #[inline(always)]
-    #[must_use]
     pub fn fjoin_rx_get(&mut self) -> FJOIN_RX_GET_W<SM_SHIFTCTRL_SPEC> {
         FJOIN_RX_GET_W::new(self, 14)
     }
     #[doc = "Bit 15 - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."]
     #[inline(always)]
-    #[must_use]
     pub fn fjoin_rx_put(&mut self) -> FJOIN_RX_PUT_W<SM_SHIFTCTRL_SPEC> {
         FJOIN_RX_PUT_W::new(self, 15)
     }
     #[doc = "Bit 16 - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."]
     #[inline(always)]
-    #[must_use]
     pub fn autopush(&mut self) -> AUTOPUSH_W<SM_SHIFTCTRL_SPEC> {
         AUTOPUSH_W::new(self, 16)
     }
     #[doc = "Bit 17 - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."]
     #[inline(always)]
-    #[must_use]
     pub fn autopull(&mut self) -> AUTOPULL_W<SM_SHIFTCTRL_SPEC> {
         AUTOPULL_W::new(self, 17)
     }
     #[doc = "Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left."]
     #[inline(always)]
-    #[must_use]
     pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W<SM_SHIFTCTRL_SPEC> {
         IN_SHIFTDIR_W::new(self, 18)
     }
     #[doc = "Bit 19 - 1 = shift out of output shift register to right. 0 = to left."]
     #[inline(always)]
-    #[must_use]
     pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W<SM_SHIFTCTRL_SPEC> {
         OUT_SHIFTDIR_W::new(self, 19)
     }
     #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."]
     #[inline(always)]
-    #[must_use]
     pub fn push_thresh(&mut self) -> PUSH_THRESH_W<SM_SHIFTCTRL_SPEC> {
         PUSH_THRESH_W::new(self, 20)
     }
     #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."]
     #[inline(always)]
-    #[must_use]
     pub fn pull_thresh(&mut self) -> PULL_THRESH_W<SM_SHIFTCTRL_SPEC> {
         PULL_THRESH_W::new(self, 25)
     }
     #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
     #[inline(always)]
-    #[must_use]
     pub fn fjoin_tx(&mut self) -> FJOIN_TX_W<SM_SHIFTCTRL_SPEC> {
         FJOIN_TX_W::new(self, 30)
     }
     #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."]
     #[inline(always)]
-    #[must_use]
     pub fn fjoin_rx(&mut self) -> FJOIN_RX_W<SM_SHIFTCTRL_SPEC> {
         FJOIN_RX_W::new(self, 31)
     }
diff --git a/src/inner/pio0/sm_irq.rs b/src/inner/pio0/sm_irq.rs
index 1ecc1d2..2a089a6 100644
--- a/src/inner/pio0/sm_irq.rs
+++ b/src/inner/pio0/sm_irq.rs
@@ -16,7 +16,7 @@ impl SM_IRQ {
     pub const fn irq_intf(&self) -> &IRQ_INTF {
         &self.irq_intf
     }
-    #[doc = "0x08 - Interrupt status after masking &amp; forcing for irq0"]
+    #[doc = "0x08 - Interrupt status after masking & forcing for irq0"]
     #[inline(always)]
     pub const fn irq_ints(&self) -> &IRQ_INTS {
         &self.irq_ints
@@ -40,12 +40,12 @@ module"]
 pub type IRQ_INTF = crate::Reg<irq_intf::IRQ_INTF_SPEC>;
 #[doc = "Interrupt Force for irq0"]
 pub mod irq_intf;
-#[doc = "IRQ_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for irq0  
+#[doc = "IRQ_INTS (rw) register accessor: Interrupt status after masking & forcing for irq0  
 
 You can [`read`](crate::Reg::read) this register and get [`irq_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq_ints`]
 module"]
 pub type IRQ_INTS = crate::Reg<irq_ints::IRQ_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for irq0"]
+#[doc = "Interrupt status after masking & forcing for irq0"]
 pub mod irq_ints;
diff --git a/src/inner/pio0/sm_irq/irq_inte.rs b/src/inner/pio0/sm_irq/irq_inte.rs
index 8f70f8f..3f4fb62 100644
--- a/src/inner/pio0/sm_irq/irq_inte.rs
+++ b/src/inner/pio0/sm_irq/irq_inte.rs
@@ -151,97 +151,81 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<IRQ_INTE_SPEC> {
         SM0_RXNEMPTY_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<IRQ_INTE_SPEC> {
         SM1_RXNEMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<IRQ_INTE_SPEC> {
         SM2_RXNEMPTY_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<IRQ_INTE_SPEC> {
         SM3_RXNEMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<IRQ_INTE_SPEC> {
         SM0_TXNFULL_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<IRQ_INTE_SPEC> {
         SM1_TXNFULL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<IRQ_INTE_SPEC> {
         SM2_TXNFULL_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<IRQ_INTE_SPEC> {
         SM3_TXNFULL_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0(&mut self) -> SM0_W<IRQ_INTE_SPEC> {
         SM0_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn sm1(&mut self) -> SM1_W<IRQ_INTE_SPEC> {
         SM1_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sm2(&mut self) -> SM2_W<IRQ_INTE_SPEC> {
         SM2_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn sm3(&mut self) -> SM3_W<IRQ_INTE_SPEC> {
         SM3_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sm4(&mut self) -> SM4_W<IRQ_INTE_SPEC> {
         SM4_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn sm5(&mut self) -> SM5_W<IRQ_INTE_SPEC> {
         SM5_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn sm6(&mut self) -> SM6_W<IRQ_INTE_SPEC> {
         SM6_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn sm7(&mut self) -> SM7_W<IRQ_INTE_SPEC> {
         SM7_W::new(self, 15)
     }
diff --git a/src/inner/pio0/sm_irq/irq_intf.rs b/src/inner/pio0/sm_irq/irq_intf.rs
index d20325b..15f5f6e 100644
--- a/src/inner/pio0/sm_irq/irq_intf.rs
+++ b/src/inner/pio0/sm_irq/irq_intf.rs
@@ -151,97 +151,81 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W<IRQ_INTF_SPEC> {
         SM0_RXNEMPTY_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W<IRQ_INTF_SPEC> {
         SM1_RXNEMPTY_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W<IRQ_INTF_SPEC> {
         SM2_RXNEMPTY_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W<IRQ_INTF_SPEC> {
         SM3_RXNEMPTY_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W<IRQ_INTF_SPEC> {
         SM0_TXNFULL_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W<IRQ_INTF_SPEC> {
         SM1_TXNFULL_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W<IRQ_INTF_SPEC> {
         SM2_TXNFULL_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W<IRQ_INTF_SPEC> {
         SM3_TXNFULL_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sm0(&mut self) -> SM0_W<IRQ_INTF_SPEC> {
         SM0_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn sm1(&mut self) -> SM1_W<IRQ_INTF_SPEC> {
         SM1_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sm2(&mut self) -> SM2_W<IRQ_INTF_SPEC> {
         SM2_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn sm3(&mut self) -> SM3_W<IRQ_INTF_SPEC> {
         SM3_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sm4(&mut self) -> SM4_W<IRQ_INTF_SPEC> {
         SM4_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn sm5(&mut self) -> SM5_W<IRQ_INTF_SPEC> {
         SM5_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn sm6(&mut self) -> SM6_W<IRQ_INTF_SPEC> {
         SM6_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn sm7(&mut self) -> SM7_W<IRQ_INTF_SPEC> {
         SM7_W::new(self, 15)
     }
diff --git a/src/inner/pio0/sm_irq/irq_ints.rs b/src/inner/pio0/sm_irq/irq_ints.rs
index 86556de..76a21ef 100644
--- a/src/inner/pio0/sm_irq/irq_ints.rs
+++ b/src/inner/pio0/sm_irq/irq_ints.rs
@@ -117,7 +117,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for irq0  
+#[doc = "Interrupt status after masking & forcing for irq0  
 
 You can [`read`](crate::Reg::read) this register and get [`irq_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ_INTS_SPEC;
diff --git a/src/inner/pio0/txf.rs b/src/inner/pio0/txf.rs
index 2e65018..22c2b2b 100644
--- a/src/inner/pio0/txf.rs
+++ b/src/inner/pio0/txf.rs
@@ -7,7 +7,6 @@ pub type TXF0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn txf0(&mut self) -> TXF0_W<TXF_SPEC> {
         TXF0_W::new(self, 0)
     }
diff --git a/src/inner/pll_sys.rs b/src/inner/pll_sys.rs
index bfe5e3c..da429f7 100644
--- a/src/inner/pll_sys.rs
+++ b/src/inner/pll_sys.rs
@@ -46,7 +46,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0x1c - Interrupt status after masking &amp; forcing"]
+    #[doc = "0x1c - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -115,12 +115,12 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
diff --git a/src/inner/pll_sys/cs.rs b/src/inner/pll_sys/cs.rs
index 82f46ec..81b7a5c 100644
--- a/src/inner/pll_sys/cs.rs
+++ b/src/inner/pll_sys/cs.rs
@@ -41,19 +41,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."]
     #[inline(always)]
-    #[must_use]
     pub fn refdiv(&mut self) -> REFDIV_W<CS_SPEC> {
         REFDIV_W::new(self, 0)
     }
     #[doc = "Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."]
     #[inline(always)]
-    #[must_use]
     pub fn bypass(&mut self) -> BYPASS_W<CS_SPEC> {
         BYPASS_W::new(self, 8)
     }
     #[doc = "Bit 30 - PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"]
     #[inline(always)]
-    #[must_use]
     pub fn lock_n(&mut self) -> LOCK_N_W<CS_SPEC> {
         LOCK_N_W::new(self, 30)
     }
diff --git a/src/inner/pll_sys/fbdiv_int.rs b/src/inner/pll_sys/fbdiv_int.rs
index 5a42ca1..19ff819 100644
--- a/src/inner/pll_sys/fbdiv_int.rs
+++ b/src/inner/pll_sys/fbdiv_int.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - see ctrl reg description for constraints"]
     #[inline(always)]
-    #[must_use]
     pub fn fbdiv_int(&mut self) -> FBDIV_INT_W<FBDIV_INT_SPEC> {
         FBDIV_INT_W::new(self, 0)
     }
diff --git a/src/inner/pll_sys/inte.rs b/src/inner/pll_sys/inte.rs
index 148644d..47a3152 100644
--- a/src/inner/pll_sys/inte.rs
+++ b/src/inner/pll_sys/inte.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn lock_n_sticky(&mut self) -> LOCK_N_STICKY_W<INTE_SPEC> {
         LOCK_N_STICKY_W::new(self, 0)
     }
diff --git a/src/inner/pll_sys/intf.rs b/src/inner/pll_sys/intf.rs
index 10d1913..bed1247 100644
--- a/src/inner/pll_sys/intf.rs
+++ b/src/inner/pll_sys/intf.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn lock_n_sticky(&mut self) -> LOCK_N_STICKY_W<INTF_SPEC> {
         LOCK_N_STICKY_W::new(self, 0)
     }
diff --git a/src/inner/pll_sys/intr.rs b/src/inner/pll_sys/intr.rs
index 30b6be4..b287733 100644
--- a/src/inner/pll_sys/intr.rs
+++ b/src/inner/pll_sys/intr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn lock_n_sticky(&mut self) -> LOCK_N_STICKY_W<INTR_SPEC> {
         LOCK_N_STICKY_W::new(self, 0)
     }
diff --git a/src/inner/pll_sys/ints.rs b/src/inner/pll_sys/ints.rs
index fc5817e..6df9301 100644
--- a/src/inner/pll_sys/ints.rs
+++ b/src/inner/pll_sys/ints.rs
@@ -12,7 +12,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/pll_sys/prim.rs b/src/inner/pll_sys/prim.rs
index a42a093..2eeccbe 100644
--- a/src/inner/pll_sys/prim.rs
+++ b/src/inner/pll_sys/prim.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 12:14 - divide by 1-7"]
     #[inline(always)]
-    #[must_use]
     pub fn postdiv2(&mut self) -> POSTDIV2_W<PRIM_SPEC> {
         POSTDIV2_W::new(self, 12)
     }
     #[doc = "Bits 16:18 - divide by 1-7"]
     #[inline(always)]
-    #[must_use]
     pub fn postdiv1(&mut self) -> POSTDIV1_W<PRIM_SPEC> {
         POSTDIV1_W::new(self, 16)
     }
diff --git a/src/inner/pll_sys/pwr.rs b/src/inner/pll_sys/pwr.rs
index d2bff09..e6b82c5 100644
--- a/src/inner/pll_sys/pwr.rs
+++ b/src/inner/pll_sys/pwr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."]
     #[inline(always)]
-    #[must_use]
     pub fn pd(&mut self) -> PD_W<PWR_SPEC> {
         PD_W::new(self, 0)
     }
     #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."]
     #[inline(always)]
-    #[must_use]
     pub fn dsmpd(&mut self) -> DSMPD_W<PWR_SPEC> {
         DSMPD_W::new(self, 2)
     }
     #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."]
     #[inline(always)]
-    #[must_use]
     pub fn postdivpd(&mut self) -> POSTDIVPD_W<PWR_SPEC> {
         POSTDIVPD_W::new(self, 3)
     }
     #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."]
     #[inline(always)]
-    #[must_use]
     pub fn vcopd(&mut self) -> VCOPD_W<PWR_SPEC> {
         VCOPD_W::new(self, 5)
     }
diff --git a/src/inner/powman.rs b/src/inner/powman.rs
index cc9d082..c2eb68d 100644
--- a/src/inner/powman.rs
+++ b/src/inner/powman.rs
@@ -133,7 +133,7 @@ impl RegisterBlock {
     pub const fn seq_cfg(&self) -> &SEQ_CFG {
         &self.seq_cfg
     }
-    #[doc = "0x38 - This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT &amp; POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."]
+    #[doc = "0x38 - This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."]
     #[inline(always)]
     pub const fn state(&self) -> &STATE {
         &self.state
@@ -358,7 +358,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0xec - Interrupt status after masking &amp; forcing"]
+    #[doc = "0xec - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -490,14 +490,14 @@ module"]
 pub type SEQ_CFG = crate::Reg<seq_cfg::SEQ_CFG_SPEC>;
 #[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"]
 pub mod seq_cfg;
-#[doc = "STATE (rw) register accessor: This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT &amp; POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.  
+#[doc = "STATE (rw) register accessor: This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.  
 
 You can [`read`](crate::Reg::read) this register and get [`state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@state`]
 module"]
 pub type STATE = crate::Reg<state::STATE_SPEC>;
-#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT &amp; POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."]
+#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."]
 pub mod state;
 #[doc = "POW_FASTDIV (rw) register accessor:   
 
@@ -895,12 +895,12 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
diff --git a/src/inner/powman/alarm_time_15to0.rs b/src/inner/powman/alarm_time_15to0.rs
index 338dff6..d84953c 100644
--- a/src/inner/powman/alarm_time_15to0.rs
+++ b/src/inner/powman/alarm_time_15to0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_time_15to0(&mut self) -> ALARM_TIME_15TO0_W<ALARM_TIME_15TO0_SPEC> {
         ALARM_TIME_15TO0_W::new(self, 0)
     }
diff --git a/src/inner/powman/alarm_time_31to16.rs b/src/inner/powman/alarm_time_31to16.rs
index f8ceb9f..dc508cb 100644
--- a/src/inner/powman/alarm_time_31to16.rs
+++ b/src/inner/powman/alarm_time_31to16.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_time_31to16(&mut self) -> ALARM_TIME_31TO16_W<ALARM_TIME_31TO16_SPEC> {
         ALARM_TIME_31TO16_W::new(self, 0)
     }
diff --git a/src/inner/powman/alarm_time_47to32.rs b/src/inner/powman/alarm_time_47to32.rs
index 33857ed..282e67d 100644
--- a/src/inner/powman/alarm_time_47to32.rs
+++ b/src/inner/powman/alarm_time_47to32.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_time_47to32(&mut self) -> ALARM_TIME_47TO32_W<ALARM_TIME_47TO32_SPEC> {
         ALARM_TIME_47TO32_W::new(self, 0)
     }
diff --git a/src/inner/powman/alarm_time_63to48.rs b/src/inner/powman/alarm_time_63to48.rs
index aedf44a..a5f47ef 100644
--- a/src/inner/powman/alarm_time_63to48.rs
+++ b/src/inner/powman/alarm_time_63to48.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_time_63to48(&mut self) -> ALARM_TIME_63TO48_W<ALARM_TIME_63TO48_SPEC> {
         ALARM_TIME_63TO48_W::new(self, 0)
     }
diff --git a/src/inner/powman/badpasswd.rs b/src/inner/powman/badpasswd.rs
index 743fd1a..6528e9b 100644
--- a/src/inner/powman/badpasswd.rs
+++ b/src/inner/powman/badpasswd.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn badpasswd(&mut self) -> BADPASSWD_W<BADPASSWD_SPEC> {
         BADPASSWD_W::new(self, 0)
     }
diff --git a/src/inner/powman/bod.rs b/src/inner/powman/bod.rs
index 6cf7ddd..b738178 100644
--- a/src/inner/powman/bod.rs
+++ b/src/inner/powman/bod.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<BOD_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
     #[inline(always)]
-    #[must_use]
     pub fn vsel(&mut self) -> VSEL_W<BOD_SPEC> {
         VSEL_W::new(self, 4)
     }
diff --git a/src/inner/powman/bod_ctrl.rs b/src/inner/powman/bod_ctrl.rs
index 5d5f30d..b51d3f6 100644
--- a/src/inner/powman/bod_ctrl.rs
+++ b/src/inner/powman/bod_ctrl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 12 - isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"]
     #[inline(always)]
-    #[must_use]
     pub fn isolate(&mut self) -> ISOLATE_W<BOD_CTRL_SPEC> {
         ISOLATE_W::new(self, 12)
     }
diff --git a/src/inner/powman/bod_lp_entry.rs b/src/inner/powman/bod_lp_entry.rs
index c179097..968c0b8 100644
--- a/src/inner/powman/bod_lp_entry.rs
+++ b/src/inner/powman/bod_lp_entry.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<BOD_LP_ENTRY_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
     #[inline(always)]
-    #[must_use]
     pub fn vsel(&mut self) -> VSEL_W<BOD_LP_ENTRY_SPEC> {
         VSEL_W::new(self, 4)
     }
diff --git a/src/inner/powman/bod_lp_exit.rs b/src/inner/powman/bod_lp_exit.rs
index 0b5a0e6..af48f48 100644
--- a/src/inner/powman/bod_lp_exit.rs
+++ b/src/inner/powman/bod_lp_exit.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<BOD_LP_EXIT_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"]
     #[inline(always)]
-    #[must_use]
     pub fn vsel(&mut self) -> VSEL_W<BOD_LP_EXIT_SPEC> {
         VSEL_W::new(self, 4)
     }
diff --git a/src/inner/powman/boot0.rs b/src/inner/powman/boot0.rs
index 21e2fb7..37017ea 100644
--- a/src/inner/powman/boot0.rs
+++ b/src/inner/powman/boot0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn boot0(&mut self) -> BOOT0_W<BOOT0_SPEC> {
         BOOT0_W::new(self, 0)
     }
diff --git a/src/inner/powman/boot1.rs b/src/inner/powman/boot1.rs
index 2c8d39e..95b4e47 100644
--- a/src/inner/powman/boot1.rs
+++ b/src/inner/powman/boot1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn boot1(&mut self) -> BOOT1_W<BOOT1_SPEC> {
         BOOT1_W::new(self, 0)
     }
diff --git a/src/inner/powman/boot2.rs b/src/inner/powman/boot2.rs
index a482e13..e7550f5 100644
--- a/src/inner/powman/boot2.rs
+++ b/src/inner/powman/boot2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn boot2(&mut self) -> BOOT2_W<BOOT2_SPEC> {
         BOOT2_W::new(self, 0)
     }
diff --git a/src/inner/powman/boot3.rs b/src/inner/powman/boot3.rs
index 21a1c88..9abed06 100644
--- a/src/inner/powman/boot3.rs
+++ b/src/inner/powman/boot3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn boot3(&mut self) -> BOOT3_W<BOOT3_SPEC> {
         BOOT3_W::new(self, 0)
     }
diff --git a/src/inner/powman/bootdis.rs b/src/inner/powman/bootdis.rs
index 2749d3c..114a27b 100644
--- a/src/inner/powman/bootdis.rs
+++ b/src/inner/powman/bootdis.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."]
     #[inline(always)]
-    #[must_use]
     pub fn now(&mut self) -> NOW_W<BOOTDIS_SPEC> {
         NOW_W::new(self, 0)
     }
     #[doc = "Bit 1 - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."]
     #[inline(always)]
-    #[must_use]
     pub fn next(&mut self) -> NEXT_W<BOOTDIS_SPEC> {
         NEXT_W::new(self, 1)
     }
diff --git a/src/inner/powman/chip_reset.rs b/src/inner/powman/chip_reset.rs
index 9833df7..8a11180 100644
--- a/src/inner/powman/chip_reset.rs
+++ b/src/inner/powman/chip_reset.rs
@@ -109,13 +109,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."]
     #[inline(always)]
-    #[must_use]
     pub fn double_tap(&mut self) -> DOUBLE_TAP_W<CHIP_RESET_SPEC> {
         DOUBLE_TAP_W::new(self, 0)
     }
     #[doc = "Bit 4 - This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."]
     #[inline(always)]
-    #[must_use]
     pub fn rescue_flag(&mut self) -> RESCUE_FLAG_W<CHIP_RESET_SPEC> {
         RESCUE_FLAG_W::new(self, 4)
     }
diff --git a/src/inner/powman/dbg_pwrcfg.rs b/src/inner/powman/dbg_pwrcfg.rs
index 854a01f..7abfd91 100644
--- a/src/inner/powman/dbg_pwrcfg.rs
+++ b/src/inner/powman/dbg_pwrcfg.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"]
     #[inline(always)]
-    #[must_use]
     pub fn ignore(&mut self) -> IGNORE_W<DBG_PWRCFG_SPEC> {
         IGNORE_W::new(self, 0)
     }
diff --git a/src/inner/powman/dbgconfig.rs b/src/inner/powman/dbgconfig.rs
index 751dca9..50bb0ed 100644
--- a/src/inner/powman/dbgconfig.rs
+++ b/src/inner/powman/dbgconfig.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_instid(&mut self) -> DP_INSTID_W<DBGCONFIG_SPEC> {
         DP_INSTID_W::new(self, 0)
     }
diff --git a/src/inner/powman/ext_ctrl0.rs b/src/inner/powman/ext_ctrl0.rs
index db92115..4f8ad16 100644
--- a/src/inner/powman/ext_ctrl0.rs
+++ b/src/inner/powman/ext_ctrl0.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:5 - selects from gpio 0->30 set to 31 to disable this feature"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_select(&mut self) -> GPIO_SELECT_W<EXT_CTRL0_SPEC> {
         GPIO_SELECT_W::new(self, 0)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn init(&mut self) -> INIT_W<EXT_CTRL0_SPEC> {
         INIT_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn init_state(&mut self) -> INIT_STATE_W<EXT_CTRL0_SPEC> {
         INIT_STATE_W::new(self, 12)
     }
     #[doc = "Bit 13 - output level when entering the low power state"]
     #[inline(always)]
-    #[must_use]
     pub fn lp_entry_state(&mut self) -> LP_ENTRY_STATE_W<EXT_CTRL0_SPEC> {
         LP_ENTRY_STATE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output level when exiting the low power state"]
     #[inline(always)]
-    #[must_use]
     pub fn lp_exit_state(&mut self) -> LP_EXIT_STATE_W<EXT_CTRL0_SPEC> {
         LP_EXIT_STATE_W::new(self, 14)
     }
diff --git a/src/inner/powman/ext_ctrl1.rs b/src/inner/powman/ext_ctrl1.rs
index a8061a7..d762ef9 100644
--- a/src/inner/powman/ext_ctrl1.rs
+++ b/src/inner/powman/ext_ctrl1.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:5 - selects from gpio 0->30 set to 31 to disable this feature"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_select(&mut self) -> GPIO_SELECT_W<EXT_CTRL1_SPEC> {
         GPIO_SELECT_W::new(self, 0)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn init(&mut self) -> INIT_W<EXT_CTRL1_SPEC> {
         INIT_W::new(self, 8)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn init_state(&mut self) -> INIT_STATE_W<EXT_CTRL1_SPEC> {
         INIT_STATE_W::new(self, 12)
     }
     #[doc = "Bit 13 - output level when entering the low power state"]
     #[inline(always)]
-    #[must_use]
     pub fn lp_entry_state(&mut self) -> LP_ENTRY_STATE_W<EXT_CTRL1_SPEC> {
         LP_ENTRY_STATE_W::new(self, 13)
     }
     #[doc = "Bit 14 - output level when exiting the low power state"]
     #[inline(always)]
-    #[must_use]
     pub fn lp_exit_state(&mut self) -> LP_EXIT_STATE_W<EXT_CTRL1_SPEC> {
         LP_EXIT_STATE_W::new(self, 14)
     }
diff --git a/src/inner/powman/ext_time_ref.rs b/src/inner/powman/ext_time_ref.rs
index 99f9ad3..5f6806e 100644
--- a/src/inner/powman/ext_time_ref.rs
+++ b/src/inner/powman/ext_time_ref.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"]
     #[inline(always)]
-    #[must_use]
     pub fn source_sel(&mut self) -> SOURCE_SEL_W<EXT_TIME_REF_SPEC> {
         SOURCE_SEL_W::new(self, 0)
     }
     #[doc = "Bit 4 - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"]
     #[inline(always)]
-    #[must_use]
     pub fn drive_lpck(&mut self) -> DRIVE_LPCK_W<EXT_TIME_REF_SPEC> {
         DRIVE_LPCK_W::new(self, 4)
     }
diff --git a/src/inner/powman/inte.rs b/src/inner/powman/inte.rs
index f76f2c1..b2536c1 100644
--- a/src/inner/powman/inte.rs
+++ b/src/inner/powman/inte.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn vreg_output_low(&mut self) -> VREG_OUTPUT_LOW_W<INTE_SPEC> {
         VREG_OUTPUT_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn timer(&mut self) -> TIMER_W<INTE_SPEC> {
         TIMER_W::new(self, 1)
     }
     #[doc = "Bit 2 - Source is state.req_ignored"]
     #[inline(always)]
-    #[must_use]
     pub fn state_req_ignored(&mut self) -> STATE_REQ_IGNORED_W<INTE_SPEC> {
         STATE_REQ_IGNORED_W::new(self, 2)
     }
     #[doc = "Bit 3 - Source is state.pwrup_while_waiting"]
     #[inline(always)]
-    #[must_use]
     pub fn pwrup_while_waiting(&mut self) -> PWRUP_WHILE_WAITING_W<INTE_SPEC> {
         PWRUP_WHILE_WAITING_W::new(self, 3)
     }
diff --git a/src/inner/powman/intf.rs b/src/inner/powman/intf.rs
index c3f9400..d4c29ab 100644
--- a/src/inner/powman/intf.rs
+++ b/src/inner/powman/intf.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn vreg_output_low(&mut self) -> VREG_OUTPUT_LOW_W<INTF_SPEC> {
         VREG_OUTPUT_LOW_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn timer(&mut self) -> TIMER_W<INTF_SPEC> {
         TIMER_W::new(self, 1)
     }
     #[doc = "Bit 2 - Source is state.req_ignored"]
     #[inline(always)]
-    #[must_use]
     pub fn state_req_ignored(&mut self) -> STATE_REQ_IGNORED_W<INTF_SPEC> {
         STATE_REQ_IGNORED_W::new(self, 2)
     }
     #[doc = "Bit 3 - Source is state.pwrup_while_waiting"]
     #[inline(always)]
-    #[must_use]
     pub fn pwrup_while_waiting(&mut self) -> PWRUP_WHILE_WAITING_W<INTF_SPEC> {
         PWRUP_WHILE_WAITING_W::new(self, 3)
     }
diff --git a/src/inner/powman/intr.rs b/src/inner/powman/intr.rs
index c27d046..7993639 100644
--- a/src/inner/powman/intr.rs
+++ b/src/inner/powman/intr.rs
@@ -37,7 +37,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn vreg_output_low(&mut self) -> VREG_OUTPUT_LOW_W<INTR_SPEC> {
         VREG_OUTPUT_LOW_W::new(self, 0)
     }
diff --git a/src/inner/powman/ints.rs b/src/inner/powman/ints.rs
index b2219bb..7fe4db2 100644
--- a/src/inner/powman/ints.rs
+++ b/src/inner/powman/ints.rs
@@ -33,7 +33,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/powman/lposc.rs b/src/inner/powman/lposc.rs
index 9abda45..bcc9c8c 100644
--- a/src/inner/powman/lposc.rs
+++ b/src/inner/powman/lposc.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - This feature has been removed"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<LPOSC_SPEC> {
         MODE_W::new(self, 0)
     }
     #[doc = "Bits 4:9 - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"]
     #[inline(always)]
-    #[must_use]
     pub fn trim(&mut self) -> TRIM_W<LPOSC_SPEC> {
         TRIM_W::new(self, 4)
     }
diff --git a/src/inner/powman/lposc_freq_khz_frac.rs b/src/inner/powman/lposc_freq_khz_frac.rs
index 8bbd18a..c14c6d9 100644
--- a/src/inner/powman/lposc_freq_khz_frac.rs
+++ b/src/inner/powman/lposc_freq_khz_frac.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"]
     #[inline(always)]
-    #[must_use]
     pub fn lposc_freq_khz_frac(&mut self) -> LPOSC_FREQ_KHZ_FRAC_W<LPOSC_FREQ_KHZ_FRAC_SPEC> {
         LPOSC_FREQ_KHZ_FRAC_W::new(self, 0)
     }
diff --git a/src/inner/powman/lposc_freq_khz_int.rs b/src/inner/powman/lposc_freq_khz_int.rs
index a5c2f63..e2048a0 100644
--- a/src/inner/powman/lposc_freq_khz_int.rs
+++ b/src/inner/powman/lposc_freq_khz_int.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5 - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"]
     #[inline(always)]
-    #[must_use]
     pub fn lposc_freq_khz_int(&mut self) -> LPOSC_FREQ_KHZ_INT_W<LPOSC_FREQ_KHZ_INT_SPEC> {
         LPOSC_FREQ_KHZ_INT_W::new(self, 0)
     }
diff --git a/src/inner/powman/pow_delay.rs b/src/inner/powman/pow_delay.rs
index f8468b0..33aa333 100644
--- a/src/inner/powman/pow_delay.rs
+++ b/src/inner/powman/pow_delay.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"]
     #[inline(always)]
-    #[must_use]
     pub fn swcore_step(&mut self) -> SWCORE_STEP_W<POW_DELAY_SPEC> {
         SWCORE_STEP_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"]
     #[inline(always)]
-    #[must_use]
     pub fn xip_step(&mut self) -> XIP_STEP_W<POW_DELAY_SPEC> {
         XIP_STEP_W::new(self, 4)
     }
     #[doc = "Bits 8:15 - timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"]
     #[inline(always)]
-    #[must_use]
     pub fn sram_step(&mut self) -> SRAM_STEP_W<POW_DELAY_SPEC> {
         SRAM_STEP_W::new(self, 8)
     }
diff --git a/src/inner/powman/pow_fastdiv.rs b/src/inner/powman/pow_fastdiv.rs
index 6dd8764..8540602 100644
--- a/src/inner/powman/pow_fastdiv.rs
+++ b/src/inner/powman/pow_fastdiv.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:10 - divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"]
     #[inline(always)]
-    #[must_use]
     pub fn pow_fastdiv(&mut self) -> POW_FASTDIV_W<POW_FASTDIV_SPEC> {
         POW_FASTDIV_W::new(self, 0)
     }
diff --git a/src/inner/powman/pwrup0.rs b/src/inner/powman/pwrup0.rs
index eab2354..7c1d69e 100644
--- a/src/inner/powman/pwrup0.rs
+++ b/src/inner/powman/pwrup0.rs
@@ -161,31 +161,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn source(&mut self) -> SOURCE_W<PWRUP0_SPEC> {
         SOURCE_W::new(self, 0)
     }
     #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<PWRUP0_SPEC> {
         ENABLE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn direction(&mut self) -> DIRECTION_W<PWRUP0_SPEC> {
         DIRECTION_W::new(self, 7)
     }
     #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<PWRUP0_SPEC> {
         MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<PWRUP0_SPEC> {
         STATUS_W::new(self, 9)
     }
diff --git a/src/inner/powman/pwrup1.rs b/src/inner/powman/pwrup1.rs
index 633bb27..b4e784d 100644
--- a/src/inner/powman/pwrup1.rs
+++ b/src/inner/powman/pwrup1.rs
@@ -161,31 +161,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn source(&mut self) -> SOURCE_W<PWRUP1_SPEC> {
         SOURCE_W::new(self, 0)
     }
     #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<PWRUP1_SPEC> {
         ENABLE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn direction(&mut self) -> DIRECTION_W<PWRUP1_SPEC> {
         DIRECTION_W::new(self, 7)
     }
     #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<PWRUP1_SPEC> {
         MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<PWRUP1_SPEC> {
         STATUS_W::new(self, 9)
     }
diff --git a/src/inner/powman/pwrup2.rs b/src/inner/powman/pwrup2.rs
index 08083b3..2f48bda 100644
--- a/src/inner/powman/pwrup2.rs
+++ b/src/inner/powman/pwrup2.rs
@@ -161,31 +161,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn source(&mut self) -> SOURCE_W<PWRUP2_SPEC> {
         SOURCE_W::new(self, 0)
     }
     #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<PWRUP2_SPEC> {
         ENABLE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn direction(&mut self) -> DIRECTION_W<PWRUP2_SPEC> {
         DIRECTION_W::new(self, 7)
     }
     #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<PWRUP2_SPEC> {
         MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<PWRUP2_SPEC> {
         STATUS_W::new(self, 9)
     }
diff --git a/src/inner/powman/pwrup3.rs b/src/inner/powman/pwrup3.rs
index 22cf092..cafbd9b 100644
--- a/src/inner/powman/pwrup3.rs
+++ b/src/inner/powman/pwrup3.rs
@@ -161,31 +161,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn source(&mut self) -> SOURCE_W<PWRUP3_SPEC> {
         SOURCE_W::new(self, 0)
     }
     #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<PWRUP3_SPEC> {
         ENABLE_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn direction(&mut self) -> DIRECTION_W<PWRUP3_SPEC> {
         DIRECTION_W::new(self, 7)
     }
     #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<PWRUP3_SPEC> {
         MODE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<PWRUP3_SPEC> {
         STATUS_W::new(self, 9)
     }
diff --git a/src/inner/powman/scratch0.rs b/src/inner/powman/scratch0.rs
index 7f29532..15d8b90 100644
--- a/src/inner/powman/scratch0.rs
+++ b/src/inner/powman/scratch0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch0(&mut self) -> SCRATCH0_W<SCRATCH0_SPEC> {
         SCRATCH0_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch1.rs b/src/inner/powman/scratch1.rs
index 4e19a0c..9b10dc4 100644
--- a/src/inner/powman/scratch1.rs
+++ b/src/inner/powman/scratch1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch1(&mut self) -> SCRATCH1_W<SCRATCH1_SPEC> {
         SCRATCH1_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch2.rs b/src/inner/powman/scratch2.rs
index e7a4024..986b335 100644
--- a/src/inner/powman/scratch2.rs
+++ b/src/inner/powman/scratch2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch2(&mut self) -> SCRATCH2_W<SCRATCH2_SPEC> {
         SCRATCH2_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch3.rs b/src/inner/powman/scratch3.rs
index f7da130..ef4a3a5 100644
--- a/src/inner/powman/scratch3.rs
+++ b/src/inner/powman/scratch3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch3(&mut self) -> SCRATCH3_W<SCRATCH3_SPEC> {
         SCRATCH3_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch4.rs b/src/inner/powman/scratch4.rs
index 20e95d6..91efcdc 100644
--- a/src/inner/powman/scratch4.rs
+++ b/src/inner/powman/scratch4.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch4(&mut self) -> SCRATCH4_W<SCRATCH4_SPEC> {
         SCRATCH4_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch5.rs b/src/inner/powman/scratch5.rs
index 2fb454d..c8abce6 100644
--- a/src/inner/powman/scratch5.rs
+++ b/src/inner/powman/scratch5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch5(&mut self) -> SCRATCH5_W<SCRATCH5_SPEC> {
         SCRATCH5_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch6.rs b/src/inner/powman/scratch6.rs
index 15f8992..353ecdb 100644
--- a/src/inner/powman/scratch6.rs
+++ b/src/inner/powman/scratch6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch6(&mut self) -> SCRATCH6_W<SCRATCH6_SPEC> {
         SCRATCH6_W::new(self, 0)
     }
diff --git a/src/inner/powman/scratch7.rs b/src/inner/powman/scratch7.rs
index 1d87121..b668da4 100644
--- a/src/inner/powman/scratch7.rs
+++ b/src/inner/powman/scratch7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch7(&mut self) -> SCRATCH7_W<SCRATCH7_SPEC> {
         SCRATCH7_W::new(self, 0)
     }
diff --git a/src/inner/powman/seq_cfg.rs b/src/inner/powman/seq_cfg.rs
index 0dc57fa..c5e5e7a 100644
--- a/src/inner/powman/seq_cfg.rs
+++ b/src/inner/powman/seq_cfg.rs
@@ -100,49 +100,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"]
     #[inline(always)]
-    #[must_use]
     pub fn hw_pwrup_sram1(&mut self) -> HW_PWRUP_SRAM1_W<SEQ_CFG_SPEC> {
         HW_PWRUP_SRAM1_W::new(self, 0)
     }
     #[doc = "Bit 1 - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"]
     #[inline(always)]
-    #[must_use]
     pub fn hw_pwrup_sram0(&mut self) -> HW_PWRUP_SRAM0_W<SEQ_CFG_SPEC> {
         HW_PWRUP_SRAM0_W::new(self, 1)
     }
     #[doc = "Bit 4 - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"]
     #[inline(always)]
-    #[must_use]
     pub fn use_vreg_lp(&mut self) -> USE_VREG_LP_W<SEQ_CFG_SPEC> {
         USE_VREG_LP_W::new(self, 4)
     }
     #[doc = "Bit 5 - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"]
     #[inline(always)]
-    #[must_use]
     pub fn use_vreg_hp(&mut self) -> USE_VREG_HP_W<SEQ_CFG_SPEC> {
         USE_VREG_HP_W::new(self, 5)
     }
     #[doc = "Bit 6 - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"]
     #[inline(always)]
-    #[must_use]
     pub fn use_bod_lp(&mut self) -> USE_BOD_LP_W<SEQ_CFG_SPEC> {
         USE_BOD_LP_W::new(self, 6)
     }
     #[doc = "Bit 7 - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"]
     #[inline(always)]
-    #[must_use]
     pub fn use_bod_hp(&mut self) -> USE_BOD_HP_W<SEQ_CFG_SPEC> {
         USE_BOD_HP_W::new(self, 7)
     }
     #[doc = "Bit 8 - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"]
     #[inline(always)]
-    #[must_use]
     pub fn run_lposc_in_lp(&mut self) -> RUN_LPOSC_IN_LP_W<SEQ_CFG_SPEC> {
         RUN_LPOSC_IN_LP_W::new(self, 8)
     }
     #[doc = "Bit 12 - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"]
     #[inline(always)]
-    #[must_use]
     pub fn use_fast_powck(&mut self) -> USE_FAST_POWCK_W<SEQ_CFG_SPEC> {
         USE_FAST_POWCK_W::new(self, 12)
     }
diff --git a/src/inner/powman/set_time_15to0.rs b/src/inner/powman/set_time_15to0.rs
index 75e31ad..df44843 100644
--- a/src/inner/powman/set_time_15to0.rs
+++ b/src/inner/powman/set_time_15to0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
     #[inline(always)]
-    #[must_use]
     pub fn set_time_15to0(&mut self) -> SET_TIME_15TO0_W<SET_TIME_15TO0_SPEC> {
         SET_TIME_15TO0_W::new(self, 0)
     }
diff --git a/src/inner/powman/set_time_31to16.rs b/src/inner/powman/set_time_31to16.rs
index 2c14123..6efe2ff 100644
--- a/src/inner/powman/set_time_31to16.rs
+++ b/src/inner/powman/set_time_31to16.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
     #[inline(always)]
-    #[must_use]
     pub fn set_time_31to16(&mut self) -> SET_TIME_31TO16_W<SET_TIME_31TO16_SPEC> {
         SET_TIME_31TO16_W::new(self, 0)
     }
diff --git a/src/inner/powman/set_time_47to32.rs b/src/inner/powman/set_time_47to32.rs
index 9f73743..f9da001 100644
--- a/src/inner/powman/set_time_47to32.rs
+++ b/src/inner/powman/set_time_47to32.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
     #[inline(always)]
-    #[must_use]
     pub fn set_time_47to32(&mut self) -> SET_TIME_47TO32_W<SET_TIME_47TO32_SPEC> {
         SET_TIME_47TO32_W::new(self, 0)
     }
diff --git a/src/inner/powman/set_time_63to48.rs b/src/inner/powman/set_time_63to48.rs
index 3261a16..9206eda 100644
--- a/src/inner/powman/set_time_63to48.rs
+++ b/src/inner/powman/set_time_63to48.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"]
     #[inline(always)]
-    #[must_use]
     pub fn set_time_63to48(&mut self) -> SET_TIME_63TO48_W<SET_TIME_63TO48_SPEC> {
         SET_TIME_63TO48_W::new(self, 0)
     }
diff --git a/src/inner/powman/state.rs b/src/inner/powman/state.rs
index 9cbfcc8..db454f7 100644
--- a/src/inner/powman/state.rs
+++ b/src/inner/powman/state.rs
@@ -69,24 +69,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7"]
     #[inline(always)]
-    #[must_use]
     pub fn req(&mut self) -> REQ_W<STATE_SPEC> {
         REQ_W::new(self, 4)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn req_ignored(&mut self) -> REQ_IGNORED_W<STATE_SPEC> {
         REQ_IGNORED_W::new(self, 8)
     }
     #[doc = "Bit 9 - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."]
     #[inline(always)]
-    #[must_use]
     pub fn pwrup_while_waiting(&mut self) -> PWRUP_WHILE_WAITING_W<STATE_SPEC> {
         PWRUP_WHILE_WAITING_W::new(self, 9)
     }
 }
-#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT &amp; POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.  
+#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.  
 
 You can [`read`](crate::Reg::read) this register and get [`state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct STATE_SPEC;
diff --git a/src/inner/powman/timer.rs b/src/inner/powman/timer.rs
index 95b132f..2561c44 100644
--- a/src/inner/powman/timer.rs
+++ b/src/inner/powman/timer.rs
@@ -97,61 +97,51 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."]
     #[inline(always)]
-    #[must_use]
     pub fn nonsec_write(&mut self) -> NONSEC_WRITE_W<TIMER_SPEC> {
         NONSEC_WRITE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"]
     #[inline(always)]
-    #[must_use]
     pub fn run(&mut self) -> RUN_W<TIMER_SPEC> {
         RUN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time."]
     #[inline(always)]
-    #[must_use]
     pub fn clear(&mut self) -> CLEAR_W<TIMER_SPEC> {
         CLEAR_W::new(self, 2)
     }
     #[doc = "Bit 4 - Enables the alarm. The alarm must be disabled while writing the alarm time."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_enab(&mut self) -> ALARM_ENAB_W<TIMER_SPEC> {
         ALARM_ENAB_W::new(self, 4)
     }
     #[doc = "Bit 5 - Alarm wakes the chip from low power mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pwrup_on_alarm(&mut self) -> PWRUP_ON_ALARM_W<TIMER_SPEC> {
         PWRUP_ON_ALARM_W::new(self, 5)
     }
     #[doc = "Bit 6 - Alarm has fired. Write to 1 to clear the alarm."]
     #[inline(always)]
-    #[must_use]
     pub fn alarm(&mut self) -> ALARM_W<TIMER_SPEC> {
         ALARM_W::new(self, 6)
     }
     #[doc = "Bit 8 - Switch to lposc as the source of the 1kHz timer tick"]
     #[inline(always)]
-    #[must_use]
     pub fn use_lposc(&mut self) -> USE_LPOSC_W<TIMER_SPEC> {
         USE_LPOSC_W::new(self, 8)
     }
     #[doc = "Bit 9 - switch to xosc as the source of the 1kHz timer tick"]
     #[inline(always)]
-    #[must_use]
     pub fn use_xosc(&mut self) -> USE_XOSC_W<TIMER_SPEC> {
         USE_XOSC_W::new(self, 9)
     }
     #[doc = "Bit 10 - switch to gpio as the source of the 1kHz timer tick"]
     #[inline(always)]
-    #[must_use]
     pub fn use_gpio_1khz(&mut self) -> USE_GPIO_1KHZ_W<TIMER_SPEC> {
         USE_GPIO_1KHZ_W::new(self, 10)
     }
     #[doc = "Bit 13 - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."]
     #[inline(always)]
-    #[must_use]
     pub fn use_gpio_1hz(&mut self) -> USE_GPIO_1HZ_W<TIMER_SPEC> {
         USE_GPIO_1HZ_W::new(self, 13)
     }
diff --git a/src/inner/powman/vreg.rs b/src/inner/powman/vreg.rs
index fe9f70f..b22ca20 100644
--- a/src/inner/powman/vreg.rs
+++ b/src/inner/powman/vreg.rs
@@ -32,13 +32,11 @@ impl R {
 impl W {
     #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
     #[inline(always)]
-    #[must_use]
     pub fn hiz(&mut self) -> HIZ_W<VREG_SPEC> {
         HIZ_W::new(self, 1)
     }
     #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
     #[inline(always)]
-    #[must_use]
     pub fn vsel(&mut self) -> VSEL_W<VREG_SPEC> {
         VSEL_W::new(self, 4)
     }
diff --git a/src/inner/powman/vreg_ctrl.rs b/src/inner/powman/vreg_ctrl.rs
index 251a3be..026550a 100644
--- a/src/inner/powman/vreg_ctrl.rs
+++ b/src/inner/powman/vreg_ctrl.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bits 4:6 - high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"]
     #[inline(always)]
-    #[must_use]
     pub fn ht_th(&mut self) -> HT_TH_W<VREG_CTRL_SPEC> {
         HT_TH_W::new(self, 4)
     }
     #[doc = "Bit 8 - 0=not disabled, 1=enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn disable_voltage_limit(&mut self) -> DISABLE_VOLTAGE_LIMIT_W<VREG_CTRL_SPEC> {
         DISABLE_VOLTAGE_LIMIT_W::new(self, 8)
     }
     #[doc = "Bit 12 - isolates the VREG control interface 0 - not isolated (default) 1 - isolated"]
     #[inline(always)]
-    #[must_use]
     pub fn isolate(&mut self) -> ISOLATE_W<VREG_CTRL_SPEC> {
         ISOLATE_W::new(self, 12)
     }
     #[doc = "Bit 13 - unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."]
     #[inline(always)]
-    #[must_use]
     pub fn unlock(&mut self) -> UNLOCK_W<VREG_CTRL_SPEC> {
         UNLOCK_W::new(self, 13)
     }
     #[doc = "Bit 15 - returns the regulator to its startup settings 0 - reset 1 - not reset (default)"]
     #[inline(always)]
-    #[must_use]
     pub fn rst_n(&mut self) -> RST_N_W<VREG_CTRL_SPEC> {
         RST_N_W::new(self, 15)
     }
diff --git a/src/inner/powman/vreg_lp_entry.rs b/src/inner/powman/vreg_lp_entry.rs
index 6039424..e45462c 100644
--- a/src/inner/powman/vreg_lp_entry.rs
+++ b/src/inner/powman/vreg_lp_entry.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
     #[inline(always)]
-    #[must_use]
     pub fn hiz(&mut self) -> HIZ_W<VREG_LP_ENTRY_SPEC> {
         HIZ_W::new(self, 1)
     }
     #[doc = "Bit 2 - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<VREG_LP_ENTRY_SPEC> {
         MODE_W::new(self, 2)
     }
     #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
     #[inline(always)]
-    #[must_use]
     pub fn vsel(&mut self) -> VSEL_W<VREG_LP_ENTRY_SPEC> {
         VSEL_W::new(self, 4)
     }
diff --git a/src/inner/powman/vreg_lp_exit.rs b/src/inner/powman/vreg_lp_exit.rs
index 513cbb4..09c535c 100644
--- a/src/inner/powman/vreg_lp_exit.rs
+++ b/src/inner/powman/vreg_lp_exit.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"]
     #[inline(always)]
-    #[must_use]
     pub fn hiz(&mut self) -> HIZ_W<VREG_LP_EXIT_SPEC> {
         HIZ_W::new(self, 1)
     }
     #[doc = "Bit 2 - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"]
     #[inline(always)]
-    #[must_use]
     pub fn mode(&mut self) -> MODE_W<VREG_LP_EXIT_SPEC> {
         MODE_W::new(self, 2)
     }
     #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"]
     #[inline(always)]
-    #[must_use]
     pub fn vsel(&mut self) -> VSEL_W<VREG_LP_EXIT_SPEC> {
         VSEL_W::new(self, 4)
     }
diff --git a/src/inner/powman/wdsel.rs b/src/inner/powman/wdsel.rs
index dd24af6..4e8c037 100644
--- a/src/inner/powman/wdsel.rs
+++ b/src/inner/powman/wdsel.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_powman_async(&mut self) -> RESET_POWMAN_ASYNC_W<WDSEL_SPEC> {
         RESET_POWMAN_ASYNC_W::new(self, 0)
     }
     #[doc = "Bit 4 - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_powman(&mut self) -> RESET_POWMAN_W<WDSEL_SPEC> {
         RESET_POWMAN_W::new(self, 4)
     }
     #[doc = "Bit 8 - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_swcore(&mut self) -> RESET_SWCORE_W<WDSEL_SPEC> {
         RESET_SWCORE_W::new(self, 8)
     }
     #[doc = "Bit 12 - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_rsm(&mut self) -> RESET_RSM_W<WDSEL_SPEC> {
         RESET_RSM_W::new(self, 12)
     }
diff --git a/src/inner/powman/xosc_freq_khz_frac.rs b/src/inner/powman/xosc_freq_khz_frac.rs
index e661585..72e9892 100644
--- a/src/inner/powman/xosc_freq_khz_frac.rs
+++ b/src/inner/powman/xosc_freq_khz_frac.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"]
     #[inline(always)]
-    #[must_use]
     pub fn xosc_freq_khz_frac(&mut self) -> XOSC_FREQ_KHZ_FRAC_W<XOSC_FREQ_KHZ_FRAC_SPEC> {
         XOSC_FREQ_KHZ_FRAC_W::new(self, 0)
     }
diff --git a/src/inner/powman/xosc_freq_khz_int.rs b/src/inner/powman/xosc_freq_khz_int.rs
index 7c09a7d..21102c4 100644
--- a/src/inner/powman/xosc_freq_khz_int.rs
+++ b/src/inner/powman/xosc_freq_khz_int.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"]
     #[inline(always)]
-    #[must_use]
     pub fn xosc_freq_khz_int(&mut self) -> XOSC_FREQ_KHZ_INT_W<XOSC_FREQ_KHZ_INT_SPEC> {
         XOSC_FREQ_KHZ_INT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/actlr.rs b/src/inner/ppb/actlr.rs
index d4f0ae5..8136416 100644
--- a/src/inner/ppb/actlr.rs
+++ b/src/inner/ppb/actlr.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Disable dual-issue."]
     #[inline(always)]
-    #[must_use]
     pub fn dismcycint(&mut self) -> DISMCYCINT_W<ACTLR_SPEC> {
         DISMCYCINT_W::new(self, 0)
     }
     #[doc = "Bit 2 - Disable dual-issue."]
     #[inline(always)]
-    #[must_use]
     pub fn disfold(&mut self) -> DISFOLD_W<ACTLR_SPEC> {
         DISFOLD_W::new(self, 2)
     }
     #[doc = "Bit 9 - Disable out-of-order FP instruction completion"]
     #[inline(always)]
-    #[must_use]
     pub fn disoofp(&mut self) -> DISOOFP_W<ACTLR_SPEC> {
         DISOOFP_W::new(self, 9)
     }
     #[doc = "Bit 10 - Disable FPU exception outputs"]
     #[inline(always)]
-    #[must_use]
     pub fn fpexcodis(&mut self) -> FPEXCODIS_W<ACTLR_SPEC> {
         FPEXCODIS_W::new(self, 10)
     }
     #[doc = "Bit 12 - Disable ATB Flush"]
     #[inline(always)]
-    #[must_use]
     pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<ACTLR_SPEC> {
         DISITMATBFLUSH_W::new(self, 12)
     }
     #[doc = "Bit 29 - External Exclusives Allowed with no MPU"]
     #[inline(always)]
-    #[must_use]
     pub fn extexclall(&mut self) -> EXTEXCLALL_W<ACTLR_SPEC> {
         EXTEXCLALL_W::new(self, 29)
     }
diff --git a/src/inner/ppb/aircr.rs b/src/inner/ppb/aircr.rs
index ead3cd2..34bcb2a 100644
--- a/src/inner/ppb/aircr.rs
+++ b/src/inner/ppb/aircr.rs
@@ -77,43 +77,36 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."]
     #[inline(always)]
-    #[must_use]
     pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W<AIRCR_SPEC> {
         VECTCLRACTIVE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."]
     #[inline(always)]
-    #[must_use]
     pub fn sysresetreq(&mut self) -> SYSRESETREQ_W<AIRCR_SPEC> {
         SYSRESETREQ_W::new(self, 2)
     }
     #[doc = "Bit 3 - System reset request, Secure state only. 0 SYSRESETREQ functionality is available to both Security states. 1 SYSRESETREQ functionality is only available to Secure state."]
     #[inline(always)]
-    #[must_use]
     pub fn sysresetreqs(&mut self) -> SYSRESETREQS_W<AIRCR_SPEC> {
         SYSRESETREQS_W::new(self, 3)
     }
     #[doc = "Bits 8:10 - Interrupt priority grouping field. This field determines the split of group priority from subpriority. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en"]
     #[inline(always)]
-    #[must_use]
     pub fn prigroup(&mut self) -> PRIGROUP_W<AIRCR_SPEC> {
         PRIGROUP_W::new(self, 8)
     }
     #[doc = "Bit 13 - BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault."]
     #[inline(always)]
-    #[must_use]
     pub fn bfhfnmins(&mut self) -> BFHFNMINS_W<AIRCR_SPEC> {
         BFHFNMINS_W::new(self, 13)
     }
     #[doc = "Bit 14 - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 0 Priority ranges of Secure and Non-secure exceptions are identical. 1 Non-secure exceptions are de-prioritized."]
     #[inline(always)]
-    #[must_use]
     pub fn pris(&mut self) -> PRIS_W<AIRCR_SPEC> {
         PRIS_W::new(self, 14)
     }
     #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."]
     #[inline(always)]
-    #[must_use]
     pub fn vectkey(&mut self) -> VECTKEY_W<AIRCR_SPEC> {
         VECTKEY_W::new(self, 16)
     }
diff --git a/src/inner/ppb/asicctl.rs b/src/inner/ppb/asicctl.rs
index ac48a45..942a090 100644
--- a/src/inner/ppb/asicctl.rs
+++ b/src/inner/ppb/asicctl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn asicctl(&mut self) -> ASICCTL_W<ASICCTL_SPEC> {
         ASICCTL_W::new(self, 0)
     }
diff --git a/src/inner/ppb/bfar.rs b/src/inner/ppb/bfar.rs
index 35a2cc3..51c6244 100644
--- a/src/inner/ppb/bfar.rs
+++ b/src/inner/ppb/bfar.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN"]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<BFAR_SPEC> {
         ADDRESS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ccr.rs b/src/inner/ppb/ccr.rs
index 4c2331d..70730d4 100644
--- a/src/inner/ppb/ccr.rs
+++ b/src/inner/ppb/ccr.rs
@@ -87,31 +87,26 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR"]
     #[inline(always)]
-    #[must_use]
     pub fn usersetmpend(&mut self) -> USERSETMPEND_W<CCR_SPEC> {
         USERSETMPEND_W::new(self, 1)
     }
     #[doc = "Bit 3 - Controls the trapping of unaligned word or halfword accesses"]
     #[inline(always)]
-    #[must_use]
     pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W<CCR_SPEC> {
         UNALIGN_TRP_W::new(self, 3)
     }
     #[doc = "Bit 4 - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero"]
     #[inline(always)]
-    #[must_use]
     pub fn div_0_trp(&mut self) -> DIV_0_TRP_W<CCR_SPEC> {
         DIV_0_TRP_W::new(self, 4)
     }
     #[doc = "Bit 8 - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0"]
     #[inline(always)]
-    #[must_use]
     pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W<CCR_SPEC> {
         BFHFNMIGN_W::new(self, 8)
     }
     #[doc = "Bit 10 - Controls the effect of a stack limit violation while executing at a requested priority less than 0"]
     #[inline(always)]
-    #[must_use]
     pub fn stkofhfnmign(&mut self) -> STKOFHFNMIGN_W<CCR_SPEC> {
         STKOFHFNMIGN_W::new(self, 10)
     }
diff --git a/src/inner/ppb/cfsr.rs b/src/inner/ppb/cfsr.rs
index 422866d..eb19e43 100644
--- a/src/inner/ppb/cfsr.rs
+++ b/src/inner/ppb/cfsr.rs
@@ -142,91 +142,76 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Provides information on MemManage exceptions"]
     #[inline(always)]
-    #[must_use]
     pub fn mmfsr(&mut self) -> MMFSR_W<CFSR_SPEC> {
         MMFSR_W::new(self, 0)
     }
     #[doc = "Bit 8 - Records whether a BusFault on an instruction prefetch has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_ibuserr(&mut self) -> BFSR_IBUSERR_W<CFSR_SPEC> {
         BFSR_IBUSERR_W::new(self, 8)
     }
     #[doc = "Bit 9 - Records whether a precise data access error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_preciserr(&mut self) -> BFSR_PRECISERR_W<CFSR_SPEC> {
         BFSR_PRECISERR_W::new(self, 9)
     }
     #[doc = "Bit 10 - Records whether an imprecise data access error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_impreciserr(&mut self) -> BFSR_IMPRECISERR_W<CFSR_SPEC> {
         BFSR_IMPRECISERR_W::new(self, 10)
     }
     #[doc = "Bit 11 - Records whether a derived BusFault occurred during exception return unstacking"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_unstkerr(&mut self) -> BFSR_UNSTKERR_W<CFSR_SPEC> {
         BFSR_UNSTKERR_W::new(self, 11)
     }
     #[doc = "Bit 12 - Records whether a derived BusFault occurred during exception entry stacking"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_stkerr(&mut self) -> BFSR_STKERR_W<CFSR_SPEC> {
         BFSR_STKERR_W::new(self, 12)
     }
     #[doc = "Bit 13 - Records whether a BusFault occurred during FP lazy state preservation"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_lsperr(&mut self) -> BFSR_LSPERR_W<CFSR_SPEC> {
         BFSR_LSPERR_W::new(self, 13)
     }
     #[doc = "Bit 15 - Indicates validity of the contents of the BFAR register"]
     #[inline(always)]
-    #[must_use]
     pub fn bfsr_bfarvalid(&mut self) -> BFSR_BFARVALID_W<CFSR_SPEC> {
         BFSR_BFARVALID_W::new(self, 15)
     }
     #[doc = "Bit 16 - Sticky flag indicating whether an undefined instruction error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_undefinstr(&mut self) -> UFSR_UNDEFINSTR_W<CFSR_SPEC> {
         UFSR_UNDEFINSTR_W::new(self, 16)
     }
     #[doc = "Bit 17 - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_invstate(&mut self) -> UFSR_INVSTATE_W<CFSR_SPEC> {
         UFSR_INVSTATE_W::new(self, 17)
     }
     #[doc = "Bit 18 - Sticky flag indicating whether an integrity check error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_invpc(&mut self) -> UFSR_INVPC_W<CFSR_SPEC> {
         UFSR_INVPC_W::new(self, 18)
     }
     #[doc = "Bit 19 - Sticky flag indicating whether a coprocessor disabled or not present error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_nocp(&mut self) -> UFSR_NOCP_W<CFSR_SPEC> {
         UFSR_NOCP_W::new(self, 19)
     }
     #[doc = "Bit 20 - Sticky flag indicating whether a stack overflow error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_stkof(&mut self) -> UFSR_STKOF_W<CFSR_SPEC> {
         UFSR_STKOF_W::new(self, 20)
     }
     #[doc = "Bit 24 - Sticky flag indicating whether an unaligned access error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_unaligned(&mut self) -> UFSR_UNALIGNED_W<CFSR_SPEC> {
         UFSR_UNALIGNED_W::new(self, 24)
     }
     #[doc = "Bit 25 - Sticky flag indicating whether an integer division by zero error has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn ufsr_divbyzero(&mut self) -> UFSR_DIVBYZERO_W<CFSR_SPEC> {
         UFSR_DIVBYZERO_W::new(self, 25)
     }
diff --git a/src/inner/ppb/cpacr.rs b/src/inner/ppb/cpacr.rs
index 7cf91be..e984d5b 100644
--- a/src/inner/ppb/cpacr.rs
+++ b/src/inner/ppb/cpacr.rs
@@ -97,61 +97,51 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Controls access privileges for coprocessor 0"]
     #[inline(always)]
-    #[must_use]
     pub fn cp0(&mut self) -> CP0_W<CPACR_SPEC> {
         CP0_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - Controls access privileges for coprocessor 1"]
     #[inline(always)]
-    #[must_use]
     pub fn cp1(&mut self) -> CP1_W<CPACR_SPEC> {
         CP1_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - Controls access privileges for coprocessor 2"]
     #[inline(always)]
-    #[must_use]
     pub fn cp2(&mut self) -> CP2_W<CPACR_SPEC> {
         CP2_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - Controls access privileges for coprocessor 3"]
     #[inline(always)]
-    #[must_use]
     pub fn cp3(&mut self) -> CP3_W<CPACR_SPEC> {
         CP3_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - Controls access privileges for coprocessor 4"]
     #[inline(always)]
-    #[must_use]
     pub fn cp4(&mut self) -> CP4_W<CPACR_SPEC> {
         CP4_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Controls access privileges for coprocessor 5"]
     #[inline(always)]
-    #[must_use]
     pub fn cp5(&mut self) -> CP5_W<CPACR_SPEC> {
         CP5_W::new(self, 10)
     }
     #[doc = "Bits 12:13 - Controls access privileges for coprocessor 6"]
     #[inline(always)]
-    #[must_use]
     pub fn cp6(&mut self) -> CP6_W<CPACR_SPEC> {
         CP6_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Controls access privileges for coprocessor 7"]
     #[inline(always)]
-    #[must_use]
     pub fn cp7(&mut self) -> CP7_W<CPACR_SPEC> {
         CP7_W::new(self, 14)
     }
     #[doc = "Bits 20:21 - Defines the access rights for the floating-point functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn cp10(&mut self) -> CP10_W<CPACR_SPEC> {
         CP10_W::new(self, 20)
     }
     #[doc = "Bits 22:23 - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN"]
     #[inline(always)]
-    #[must_use]
     pub fn cp11(&mut self) -> CP11_W<CPACR_SPEC> {
         CP11_W::new(self, 22)
     }
diff --git a/src/inner/ppb/ctiappclear.rs b/src/inner/ppb/ctiappclear.rs
index 7816b9e..27fce54 100644
--- a/src/inner/ppb/ctiappclear.rs
+++ b/src/inner/ppb/ctiappclear.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel."]
     #[inline(always)]
-    #[must_use]
     pub fn appclear(&mut self) -> APPCLEAR_W<CTIAPPCLEAR_SPEC> {
         APPCLEAR_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiapppulse.rs b/src/inner/ppb/ctiapppulse.rs
index 7e70bb8..d834c07 100644
--- a/src/inner/ppb/ctiapppulse.rs
+++ b/src/inner/ppb/ctiapppulse.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel."]
     #[inline(always)]
-    #[must_use]
     pub fn appulse(&mut self) -> APPULSE_W<CTIAPPPULSE_SPEC> {
         APPULSE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiappset.rs b/src/inner/ppb/ctiappset.rs
index c17d363..7f12fb8 100644
--- a/src/inner/ppb/ctiappset.rs
+++ b/src/inner/ppb/ctiappset.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel"]
     #[inline(always)]
-    #[must_use]
     pub fn appset(&mut self) -> APPSET_W<CTIAPPSET_SPEC> {
         APPSET_W::new(self, 0)
     }
diff --git a/src/inner/ppb/cticontrol.rs b/src/inner/ppb/cticontrol.rs
index 11ec375..b9f7aaf 100644
--- a/src/inner/ppb/cticontrol.rs
+++ b/src/inner/ppb/cticontrol.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables or disables the CTI"]
     #[inline(always)]
-    #[must_use]
     pub fn glben(&mut self) -> GLBEN_W<CTICONTROL_SPEC> {
         GLBEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctigate.rs b/src/inner/ppb/ctigate.rs
index f818659..043ef00 100644
--- a/src/inner/ppb/ctigate.rs
+++ b/src/inner/ppb/ctigate.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable ctichout0. Set to 0 to disable channel propagation."]
     #[inline(always)]
-    #[must_use]
     pub fn ctigateen0(&mut self) -> CTIGATEEN0_W<CTIGATE_SPEC> {
         CTIGATEEN0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enable ctichout1. Set to 0 to disable channel propagation."]
     #[inline(always)]
-    #[must_use]
     pub fn ctigateen1(&mut self) -> CTIGATEEN1_W<CTIGATE_SPEC> {
         CTIGATEEN1_W::new(self, 1)
     }
     #[doc = "Bit 2 - Enable ctichout2. Set to 0 to disable channel propagation."]
     #[inline(always)]
-    #[must_use]
     pub fn ctigateen2(&mut self) -> CTIGATEEN2_W<CTIGATE_SPEC> {
         CTIGATEEN2_W::new(self, 2)
     }
     #[doc = "Bit 3 - Enable ctichout3. Set to 0 to disable channel propagation."]
     #[inline(always)]
-    #[must_use]
     pub fn ctigateen3(&mut self) -> CTIGATEEN3_W<CTIGATE_SPEC> {
         CTIGATEEN3_W::new(self, 3)
     }
diff --git a/src/inner/ppb/ctiinen0.rs b/src/inner/ppb/ctiinen0.rs
index 6c8d75f..5805359 100644
--- a/src/inner/ppb/ctiinen0.rs
+++ b/src/inner/ppb/ctiinen0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN0_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen1.rs b/src/inner/ppb/ctiinen1.rs
index 192bb5f..f8a1d10 100644
--- a/src/inner/ppb/ctiinen1.rs
+++ b/src/inner/ppb/ctiinen1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN1_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen2.rs b/src/inner/ppb/ctiinen2.rs
index 6300136..dca5dd6 100644
--- a/src/inner/ppb/ctiinen2.rs
+++ b/src/inner/ppb/ctiinen2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN2_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen3.rs b/src/inner/ppb/ctiinen3.rs
index 91060da..0f8b81c 100644
--- a/src/inner/ppb/ctiinen3.rs
+++ b/src/inner/ppb/ctiinen3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN3_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen4.rs b/src/inner/ppb/ctiinen4.rs
index 13b1adf..45191c5 100644
--- a/src/inner/ppb/ctiinen4.rs
+++ b/src/inner/ppb/ctiinen4.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN4_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen5.rs b/src/inner/ppb/ctiinen5.rs
index 6080495..606e9eb 100644
--- a/src/inner/ppb/ctiinen5.rs
+++ b/src/inner/ppb/ctiinen5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN5_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen6.rs b/src/inner/ppb/ctiinen6.rs
index ffe1a54..de5ef05 100644
--- a/src/inner/ppb/ctiinen6.rs
+++ b/src/inner/ppb/ctiinen6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN6_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiinen7.rs b/src/inner/ppb/ctiinen7.rs
index 7afca71..8a90fe4 100644
--- a/src/inner/ppb/ctiinen7.rs
+++ b/src/inner/ppb/ctiinen7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"]
     #[inline(always)]
-    #[must_use]
     pub fn triginen(&mut self) -> TRIGINEN_W<CTIINEN7_SPEC> {
         TRIGINEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiintack.rs b/src/inner/ppb/ctiintack.rs
index 21596cf..885df8c 100644
--- a/src/inner/ppb/ctiintack.rs
+++ b/src/inner/ppb/ctiintack.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared."]
     #[inline(always)]
-    #[must_use]
     pub fn intack(&mut self) -> INTACK_W<CTIINTACK_SPEC> {
         INTACK_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten0.rs b/src/inner/ppb/ctiouten0.rs
index b63b858..0d77c14 100644
--- a/src/inner/ppb/ctiouten0.rs
+++ b/src/inner/ppb/ctiouten0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN0_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten1.rs b/src/inner/ppb/ctiouten1.rs
index 89b634f..7824d6e 100644
--- a/src/inner/ppb/ctiouten1.rs
+++ b/src/inner/ppb/ctiouten1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN1_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten2.rs b/src/inner/ppb/ctiouten2.rs
index ad4124d..b0ddd13 100644
--- a/src/inner/ppb/ctiouten2.rs
+++ b/src/inner/ppb/ctiouten2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN2_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten3.rs b/src/inner/ppb/ctiouten3.rs
index e568820..aabb924 100644
--- a/src/inner/ppb/ctiouten3.rs
+++ b/src/inner/ppb/ctiouten3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN3_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten4.rs b/src/inner/ppb/ctiouten4.rs
index 875a630..6cd99f5 100644
--- a/src/inner/ppb/ctiouten4.rs
+++ b/src/inner/ppb/ctiouten4.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN4_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten5.rs b/src/inner/ppb/ctiouten5.rs
index 74265ca..ea98cfb 100644
--- a/src/inner/ppb/ctiouten5.rs
+++ b/src/inner/ppb/ctiouten5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN5_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten6.rs b/src/inner/ppb/ctiouten6.rs
index 9d3676c..9c54d9b 100644
--- a/src/inner/ppb/ctiouten6.rs
+++ b/src/inner/ppb/ctiouten6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN6_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ctiouten7.rs b/src/inner/ppb/ctiouten7.rs
index d8a5221..5f4b9b1 100644
--- a/src/inner/ppb/ctiouten7.rs
+++ b/src/inner/ppb/ctiouten7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."]
     #[inline(always)]
-    #[must_use]
     pub fn trigouten(&mut self) -> TRIGOUTEN_W<CTIOUTEN7_SPEC> {
         TRIGOUTEN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dcrdr.rs b/src/inner/ppb/dcrdr.rs
index 878a9f5..192f8b8 100644
--- a/src/inner/ppb/dcrdr.rs
+++ b/src/inner/ppb/dcrdr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers"]
     #[inline(always)]
-    #[must_use]
     pub fn dbgtmp(&mut self) -> DBGTMP_W<DCRDR_SPEC> {
         DBGTMP_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dcrsr.rs b/src/inner/ppb/dcrsr.rs
index fd644c2..b50ef22 100644
--- a/src/inner/ppb/dcrsr.rs
+++ b/src/inner/ppb/dcrsr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Specifies the general-purpose register, special-purpose register, or FP register to transfer"]
     #[inline(always)]
-    #[must_use]
     pub fn regsel(&mut self) -> REGSEL_W<DCRSR_SPEC> {
         REGSEL_W::new(self, 0)
     }
     #[doc = "Bit 16 - Specifies the access type for the transfer"]
     #[inline(always)]
-    #[must_use]
     pub fn regwnr(&mut self) -> REGWNR_W<DCRSR_SPEC> {
         REGWNR_W::new(self, 16)
     }
diff --git a/src/inner/ppb/demcr.rs b/src/inner/ppb/demcr.rs
index a409de4..fd1200d 100644
--- a/src/inner/ppb/demcr.rs
+++ b/src/inner/ppb/demcr.rs
@@ -140,85 +140,71 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable Reset Vector Catch. This causes a warm reset to halt a running system"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_corereset(&mut self) -> VC_CORERESET_W<DEMCR_SPEC> {
         VC_CORERESET_W::new(self, 0)
     }
     #[doc = "Bit 4 - Enable halting debug trap on a MemManage exception"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_mmerr(&mut self) -> VC_MMERR_W<DEMCR_SPEC> {
         VC_MMERR_W::new(self, 4)
     }
     #[doc = "Bit 5 - Enable halting debug trap on a UsageFault caused by an access to a coprocessor"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_nocperr(&mut self) -> VC_NOCPERR_W<DEMCR_SPEC> {
         VC_NOCPERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_chkerr(&mut self) -> VC_CHKERR_W<DEMCR_SPEC> {
         VC_CHKERR_W::new(self, 6)
     }
     #[doc = "Bit 7 - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_staterr(&mut self) -> VC_STATERR_W<DEMCR_SPEC> {
         VC_STATERR_W::new(self, 7)
     }
     #[doc = "Bit 8 - BusFault exception halting debug vector catch enable"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_buserr(&mut self) -> VC_BUSERR_W<DEMCR_SPEC> {
         VC_BUSERR_W::new(self, 8)
     }
     #[doc = "Bit 9 - Enable halting debug vector catch for faults during exception entry and return"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_interr(&mut self) -> VC_INTERR_W<DEMCR_SPEC> {
         VC_INTERR_W::new(self, 9)
     }
     #[doc = "Bit 10 - HardFault exception halting debug vector catch enable"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_harderr(&mut self) -> VC_HARDERR_W<DEMCR_SPEC> {
         VC_HARDERR_W::new(self, 10)
     }
     #[doc = "Bit 11 - SecureFault exception halting debug vector catch enable"]
     #[inline(always)]
-    #[must_use]
     pub fn vc_sferr(&mut self) -> VC_SFERR_W<DEMCR_SPEC> {
         VC_SFERR_W::new(self, 11)
     }
     #[doc = "Bit 16 - Enable the DebugMonitor exception"]
     #[inline(always)]
-    #[must_use]
     pub fn mon_en(&mut self) -> MON_EN_W<DEMCR_SPEC> {
         MON_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Sets or clears the pending state of the DebugMonitor exception"]
     #[inline(always)]
-    #[must_use]
     pub fn mon_pend(&mut self) -> MON_PEND_W<DEMCR_SPEC> {
         MON_PEND_W::new(self, 17)
     }
     #[doc = "Bit 18 - Enable DebugMonitor stepping"]
     #[inline(always)]
-    #[must_use]
     pub fn mon_step(&mut self) -> MON_STEP_W<DEMCR_SPEC> {
         MON_STEP_W::new(self, 18)
     }
     #[doc = "Bit 19 - DebugMonitor semaphore bit"]
     #[inline(always)]
-    #[must_use]
     pub fn mon_req(&mut self) -> MON_REQ_W<DEMCR_SPEC> {
         MON_REQ_W::new(self, 19)
     }
     #[doc = "Bit 24 - Global enable for all DWT and ITM features"]
     #[inline(always)]
-    #[must_use]
     pub fn trcena(&mut self) -> TRCENA_W<DEMCR_SPEC> {
         TRCENA_W::new(self, 24)
     }
diff --git a/src/inner/ppb/dfsr.rs b/src/inner/ppb/dfsr.rs
index 7b0b718..7baa7cf 100644
--- a/src/inner/ppb/dfsr.rs
+++ b/src/inner/ppb/dfsr.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Sticky flag indicating that a Halt request debug event or Step debug event has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn halted(&mut self) -> HALTED_W<DFSR_SPEC> {
         HALTED_W::new(self, 0)
     }
     #[doc = "Bit 1 - Sticky flag indicating whether a Breakpoint debug event has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn bkpt(&mut self) -> BKPT_W<DFSR_SPEC> {
         BKPT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Sticky flag indicating whether a Watchpoint debug event has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn dwttrap(&mut self) -> DWTTRAP_W<DFSR_SPEC> {
         DWTTRAP_W::new(self, 2)
     }
     #[doc = "Bit 3 - Sticky flag indicating whether a Vector catch debug event has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn vcatch(&mut self) -> VCATCH_W<DFSR_SPEC> {
         VCATCH_W::new(self, 3)
     }
     #[doc = "Bit 4 - Sticky flag indicating whether an External debug request debug event has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn external(&mut self) -> EXTERNAL_W<DFSR_SPEC> {
         EXTERNAL_W::new(self, 4)
     }
diff --git a/src/inner/ppb/dhcsr.rs b/src/inner/ppb/dhcsr.rs
index 8a47757..1492e9d 100644
--- a/src/inner/ppb/dhcsr.rs
+++ b/src/inner/ppb/dhcsr.rs
@@ -108,31 +108,26 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable Halting debug"]
     #[inline(always)]
-    #[must_use]
     pub fn c_debugen(&mut self) -> C_DEBUGEN_W<DHCSR_SPEC> {
         C_DEBUGEN_W::new(self, 0)
     }
     #[doc = "Bit 1 - PE enter Debug state halt request"]
     #[inline(always)]
-    #[must_use]
     pub fn c_halt(&mut self) -> C_HALT_W<DHCSR_SPEC> {
         C_HALT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Enable single instruction step"]
     #[inline(always)]
-    #[must_use]
     pub fn c_step(&mut self) -> C_STEP_W<DHCSR_SPEC> {
         C_STEP_W::new(self, 2)
     }
     #[doc = "Bit 3 - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts"]
     #[inline(always)]
-    #[must_use]
     pub fn c_maskints(&mut self) -> C_MASKINTS_W<DHCSR_SPEC> {
         C_MASKINTS_W::new(self, 3)
     }
     #[doc = "Bit 5 - Allow imprecise entry to Debug state"]
     #[inline(always)]
-    #[must_use]
     pub fn c_snapstall(&mut self) -> C_SNAPSTALL_W<DHCSR_SPEC> {
         C_SNAPSTALL_W::new(self, 5)
     }
diff --git a/src/inner/ppb/dpidr5.rs b/src/inner/ppb/dpidr5.rs
index 932ae69..61586d4 100644
--- a/src/inner/ppb/dpidr5.rs
+++ b/src/inner/ppb/dpidr5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dpidr5(&mut self) -> DPIDR5_W<DPIDR5_SPEC> {
         DPIDR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dpidr6.rs b/src/inner/ppb/dpidr6.rs
index fa2b77d..6aa18ff 100644
--- a/src/inner/ppb/dpidr6.rs
+++ b/src/inner/ppb/dpidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dpidr6(&mut self) -> DPIDR6_W<DPIDR6_SPEC> {
         DPIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dpidr7.rs b/src/inner/ppb/dpidr7.rs
index 9568183..210c823 100644
--- a/src/inner/ppb/dpidr7.rs
+++ b/src/inner/ppb/dpidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dpidr7(&mut self) -> DPIDR7_W<DPIDR7_SPEC> {
         DPIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dscsr.rs b/src/inner/ppb/dscsr.rs
index 765fe80..6e6ac00 100644
--- a/src/inner/ppb/dscsr.rs
+++ b/src/inner/ppb/dscsr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger"]
     #[inline(always)]
-    #[must_use]
     pub fn sbrselen(&mut self) -> SBRSELEN_W<DSCSR_SPEC> {
         SBRSELEN_W::new(self, 0)
     }
     #[doc = "Bit 1 - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger"]
     #[inline(always)]
-    #[must_use]
     pub fn sbrsel(&mut self) -> SBRSEL_W<DSCSR_SPEC> {
         SBRSEL_W::new(self, 1)
     }
     #[doc = "Bit 16 - This field indicates the current Security state of the processor"]
     #[inline(always)]
-    #[must_use]
     pub fn cds(&mut self) -> CDS_W<DSCSR_SPEC> {
         CDS_W::new(self, 16)
     }
     #[doc = "Bit 17 - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero"]
     #[inline(always)]
-    #[must_use]
     pub fn cdskey(&mut self) -> CDSKEY_W<DSCSR_SPEC> {
         CDSKEY_W::new(self, 17)
     }
diff --git a/src/inner/ppb/dwt_comp0.rs b/src/inner/ppb/dwt_comp0.rs
index dd356fd..9af845e 100644
--- a/src/inner/ppb/dwt_comp0.rs
+++ b/src/inner/ppb/dwt_comp0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_comp0(&mut self) -> DWT_COMP0_W<DWT_COMP0_SPEC> {
         DWT_COMP0_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_comp1.rs b/src/inner/ppb/dwt_comp1.rs
index 5cdc969..cbf34b0 100644
--- a/src/inner/ppb/dwt_comp1.rs
+++ b/src/inner/ppb/dwt_comp1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_comp1(&mut self) -> DWT_COMP1_W<DWT_COMP1_SPEC> {
         DWT_COMP1_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_comp2.rs b/src/inner/ppb/dwt_comp2.rs
index 03038eb..f21c39a 100644
--- a/src/inner/ppb/dwt_comp2.rs
+++ b/src/inner/ppb/dwt_comp2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_comp2(&mut self) -> DWT_COMP2_W<DWT_COMP2_SPEC> {
         DWT_COMP2_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_comp3.rs b/src/inner/ppb/dwt_comp3.rs
index cc023a1..e71215a 100644
--- a/src/inner/ppb/dwt_comp3.rs
+++ b/src/inner/ppb/dwt_comp3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_comp3(&mut self) -> DWT_COMP3_W<DWT_COMP3_SPEC> {
         DWT_COMP3_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_ctrl.rs b/src/inner/ppb/dwt_ctrl.rs
index 2dd45fd..5782a87 100644
--- a/src/inner/ppb/dwt_ctrl.rs
+++ b/src/inner/ppb/dwt_ctrl.rs
@@ -168,85 +168,71 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables CYCCNT"]
     #[inline(always)]
-    #[must_use]
     pub fn cyccntena(&mut self) -> CYCCNTENA_W<DWT_CTRL_SPEC> {
         CYCCNTENA_W::new(self, 0)
     }
     #[doc = "Bits 1:4 - Reload value for the POSTCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn postpreset(&mut self) -> POSTPRESET_W<DWT_CTRL_SPEC> {
         POSTPRESET_W::new(self, 1)
     }
     #[doc = "Bits 5:8 - Initial value for the POSTCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn postinit(&mut self) -> POSTINIT_W<DWT_CTRL_SPEC> {
         POSTINIT_W::new(self, 5)
     }
     #[doc = "Bit 9 - Selects the position of the POSTCNT tap on the CYCCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn cyctap(&mut self) -> CYCTAP_W<DWT_CTRL_SPEC> {
         CYCTAP_W::new(self, 9)
     }
     #[doc = "Bits 10:11 - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate"]
     #[inline(always)]
-    #[must_use]
     pub fn synctap(&mut self) -> SYNCTAP_W<DWT_CTRL_SPEC> {
         SYNCTAP_W::new(self, 10)
     }
     #[doc = "Bit 12 - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation"]
     #[inline(always)]
-    #[must_use]
     pub fn pcsamplena(&mut self) -> PCSAMPLENA_W<DWT_CTRL_SPEC> {
         PCSAMPLENA_W::new(self, 12)
     }
     #[doc = "Bit 16 - Enables generation of Exception Trace packets"]
     #[inline(always)]
-    #[must_use]
     pub fn exttrcena(&mut self) -> EXTTRCENA_W<DWT_CTRL_SPEC> {
         EXTTRCENA_W::new(self, 16)
     }
     #[doc = "Bit 17 - Enables DWT_CPICNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn cpievtena(&mut self) -> CPIEVTENA_W<DWT_CTRL_SPEC> {
         CPIEVTENA_W::new(self, 17)
     }
     #[doc = "Bit 18 - Enables DWT_EXCCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn excevtena(&mut self) -> EXCEVTENA_W<DWT_CTRL_SPEC> {
         EXCEVTENA_W::new(self, 18)
     }
     #[doc = "Bit 19 - Enable DWT_SLEEPCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn sleepevtena(&mut self) -> SLEEPEVTENA_W<DWT_CTRL_SPEC> {
         SLEEPEVTENA_W::new(self, 19)
     }
     #[doc = "Bit 20 - Enables DWT_LSUCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn lsuevtena(&mut self) -> LSUEVTENA_W<DWT_CTRL_SPEC> {
         LSUEVTENA_W::new(self, 20)
     }
     #[doc = "Bit 21 - Enables DWT_FOLDCNT counter"]
     #[inline(always)]
-    #[must_use]
     pub fn foldevtena(&mut self) -> FOLDEVTENA_W<DWT_CTRL_SPEC> {
         FOLDEVTENA_W::new(self, 21)
     }
     #[doc = "Bit 22 - Enables Event Counter packet generation on POSTCNT underflow"]
     #[inline(always)]
-    #[must_use]
     pub fn cycevtena(&mut self) -> CYCEVTENA_W<DWT_CTRL_SPEC> {
         CYCEVTENA_W::new(self, 22)
     }
     #[doc = "Bit 23 - Controls whether the cycle counter is disabled in Secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn cycdiss(&mut self) -> CYCDISS_W<DWT_CTRL_SPEC> {
         CYCDISS_W::new(self, 23)
     }
diff --git a/src/inner/ppb/dwt_cyccnt.rs b/src/inner/ppb/dwt_cyccnt.rs
index 363ba85..643644a 100644
--- a/src/inner/ppb/dwt_cyccnt.rs
+++ b/src/inner/ppb/dwt_cyccnt.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero"]
     #[inline(always)]
-    #[must_use]
     pub fn cyccnt(&mut self) -> CYCCNT_W<DWT_CYCCNT_SPEC> {
         CYCCNT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_exccnt.rs b/src/inner/ppb/dwt_exccnt.rs
index 8266960..ffba353 100644
--- a/src/inner/ppb/dwt_exccnt.rs
+++ b/src/inner/ppb/dwt_exccnt.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."]
     #[inline(always)]
-    #[must_use]
     pub fn exccnt(&mut self) -> EXCCNT_W<DWT_EXCCNT_SPEC> {
         EXCCNT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_foldcnt.rs b/src/inner/ppb/dwt_foldcnt.rs
index 8fcf0d3..ce50eb2 100644
--- a/src/inner/ppb/dwt_foldcnt.rs
+++ b/src/inner/ppb/dwt_foldcnt.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one"]
     #[inline(always)]
-    #[must_use]
     pub fn foldcnt(&mut self) -> FOLDCNT_W<DWT_FOLDCNT_SPEC> {
         FOLDCNT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_function0.rs b/src/inner/ppb/dwt_function0.rs
index fe34123..44575b5 100644
--- a/src/inner/ppb/dwt_function0.rs
+++ b/src/inner/ppb/dwt_function0.rs
@@ -48,19 +48,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"]
     #[inline(always)]
-    #[must_use]
     pub fn match_(&mut self) -> MATCH_W<DWT_FUNCTION0_SPEC> {
         MATCH_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"]
     #[inline(always)]
-    #[must_use]
     pub fn action(&mut self) -> ACTION_W<DWT_FUNCTION0_SPEC> {
         ACTION_W::new(self, 4)
     }
     #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"]
     #[inline(always)]
-    #[must_use]
     pub fn datavsize(&mut self) -> DATAVSIZE_W<DWT_FUNCTION0_SPEC> {
         DATAVSIZE_W::new(self, 10)
     }
diff --git a/src/inner/ppb/dwt_function1.rs b/src/inner/ppb/dwt_function1.rs
index bb3c4ce..6f8614a 100644
--- a/src/inner/ppb/dwt_function1.rs
+++ b/src/inner/ppb/dwt_function1.rs
@@ -48,19 +48,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"]
     #[inline(always)]
-    #[must_use]
     pub fn match_(&mut self) -> MATCH_W<DWT_FUNCTION1_SPEC> {
         MATCH_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"]
     #[inline(always)]
-    #[must_use]
     pub fn action(&mut self) -> ACTION_W<DWT_FUNCTION1_SPEC> {
         ACTION_W::new(self, 4)
     }
     #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"]
     #[inline(always)]
-    #[must_use]
     pub fn datavsize(&mut self) -> DATAVSIZE_W<DWT_FUNCTION1_SPEC> {
         DATAVSIZE_W::new(self, 10)
     }
diff --git a/src/inner/ppb/dwt_function2.rs b/src/inner/ppb/dwt_function2.rs
index 94b5655..df51c3c 100644
--- a/src/inner/ppb/dwt_function2.rs
+++ b/src/inner/ppb/dwt_function2.rs
@@ -48,19 +48,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"]
     #[inline(always)]
-    #[must_use]
     pub fn match_(&mut self) -> MATCH_W<DWT_FUNCTION2_SPEC> {
         MATCH_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"]
     #[inline(always)]
-    #[must_use]
     pub fn action(&mut self) -> ACTION_W<DWT_FUNCTION2_SPEC> {
         ACTION_W::new(self, 4)
     }
     #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"]
     #[inline(always)]
-    #[must_use]
     pub fn datavsize(&mut self) -> DATAVSIZE_W<DWT_FUNCTION2_SPEC> {
         DATAVSIZE_W::new(self, 10)
     }
diff --git a/src/inner/ppb/dwt_function3.rs b/src/inner/ppb/dwt_function3.rs
index 46f5c1c..471a2e5 100644
--- a/src/inner/ppb/dwt_function3.rs
+++ b/src/inner/ppb/dwt_function3.rs
@@ -48,19 +48,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"]
     #[inline(always)]
-    #[must_use]
     pub fn match_(&mut self) -> MATCH_W<DWT_FUNCTION3_SPEC> {
         MATCH_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"]
     #[inline(always)]
-    #[must_use]
     pub fn action(&mut self) -> ACTION_W<DWT_FUNCTION3_SPEC> {
         ACTION_W::new(self, 4)
     }
     #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"]
     #[inline(always)]
-    #[must_use]
     pub fn datavsize(&mut self) -> DATAVSIZE_W<DWT_FUNCTION3_SPEC> {
         DATAVSIZE_W::new(self, 10)
     }
diff --git a/src/inner/ppb/dwt_lsucnt.rs b/src/inner/ppb/dwt_lsucnt.rs
index 26564dc..9b73768 100644
--- a/src/inner/ppb/dwt_lsucnt.rs
+++ b/src/inner/ppb/dwt_lsucnt.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."]
     #[inline(always)]
-    #[must_use]
     pub fn lsucnt(&mut self) -> LSUCNT_W<DWT_LSUCNT_SPEC> {
         LSUCNT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_pidr5.rs b/src/inner/ppb/dwt_pidr5.rs
index 8fc09f1..117b91b 100644
--- a/src/inner/ppb/dwt_pidr5.rs
+++ b/src/inner/ppb/dwt_pidr5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_pidr5(&mut self) -> DWT_PIDR5_W<DWT_PIDR5_SPEC> {
         DWT_PIDR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_pidr6.rs b/src/inner/ppb/dwt_pidr6.rs
index 3fdfc19..01971db 100644
--- a/src/inner/ppb/dwt_pidr6.rs
+++ b/src/inner/ppb/dwt_pidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_pidr6(&mut self) -> DWT_PIDR6_W<DWT_PIDR6_SPEC> {
         DWT_PIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/dwt_pidr7.rs b/src/inner/ppb/dwt_pidr7.rs
index 1e6080a..3bcb4b5 100644
--- a/src/inner/ppb/dwt_pidr7.rs
+++ b/src/inner/ppb/dwt_pidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn dwt_pidr7(&mut self) -> DWT_PIDR7_W<DWT_PIDR7_SPEC> {
         DWT_PIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp0.rs b/src/inner/ppb/fp_comp0.rs
index 7e3e7bb..8527e6e 100644
--- a/src/inner/ppb/fp_comp0.rs
+++ b/src/inner/ppb/fp_comp0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP0_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp1.rs b/src/inner/ppb/fp_comp1.rs
index 195e401..e931188 100644
--- a/src/inner/ppb/fp_comp1.rs
+++ b/src/inner/ppb/fp_comp1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP1_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp2.rs b/src/inner/ppb/fp_comp2.rs
index fd6940b..e4f39ef 100644
--- a/src/inner/ppb/fp_comp2.rs
+++ b/src/inner/ppb/fp_comp2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP2_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp3.rs b/src/inner/ppb/fp_comp3.rs
index a8c5593..36451fe 100644
--- a/src/inner/ppb/fp_comp3.rs
+++ b/src/inner/ppb/fp_comp3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP3_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp4.rs b/src/inner/ppb/fp_comp4.rs
index d7bc42b..ab7f1f8 100644
--- a/src/inner/ppb/fp_comp4.rs
+++ b/src/inner/ppb/fp_comp4.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP4_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp5.rs b/src/inner/ppb/fp_comp5.rs
index af1b951..7e75a8b 100644
--- a/src/inner/ppb/fp_comp5.rs
+++ b/src/inner/ppb/fp_comp5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP5_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp6.rs b/src/inner/ppb/fp_comp6.rs
index 5fb4eb2..46b519d 100644
--- a/src/inner/ppb/fp_comp6.rs
+++ b/src/inner/ppb/fp_comp6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP6_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_comp7.rs b/src/inner/ppb/fp_comp7.rs
index b2bafc4..7daa74b 100644
--- a/src/inner/ppb/fp_comp7.rs
+++ b/src/inner/ppb/fp_comp7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<FP_COMP7_SPEC> {
         BE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_ctrl.rs b/src/inner/ppb/fp_ctrl.rs
index c59a0af..18502cf 100644
--- a/src/inner/ppb/fp_ctrl.rs
+++ b/src/inner/ppb/fp_ctrl.rs
@@ -53,13 +53,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables the FPB"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<FP_CTRL_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one"]
     #[inline(always)]
-    #[must_use]
     pub fn key(&mut self) -> KEY_W<FP_CTRL_SPEC> {
         KEY_W::new(self, 1)
     }
diff --git a/src/inner/ppb/fp_pidr5.rs b/src/inner/ppb/fp_pidr5.rs
index cc0ffbe..f2340f2 100644
--- a/src/inner/ppb/fp_pidr5.rs
+++ b/src/inner/ppb/fp_pidr5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn fp_pidr5(&mut self) -> FP_PIDR5_W<FP_PIDR5_SPEC> {
         FP_PIDR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_pidr6.rs b/src/inner/ppb/fp_pidr6.rs
index 314fc12..a36dbfe 100644
--- a/src/inner/ppb/fp_pidr6.rs
+++ b/src/inner/ppb/fp_pidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn fp_pidr6(&mut self) -> FP_PIDR6_W<FP_PIDR6_SPEC> {
         FP_PIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fp_pidr7.rs b/src/inner/ppb/fp_pidr7.rs
index 54e4915..7c4dca0 100644
--- a/src/inner/ppb/fp_pidr7.rs
+++ b/src/inner/ppb/fp_pidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn fp_pidr7(&mut self) -> FP_PIDR7_W<FP_PIDR7_SPEC> {
         FP_PIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/fpcar.rs b/src/inner/ppb/fpcar.rs
index f2380d7..5eb81c1 100644
--- a/src/inner/ppb/fpcar.rs
+++ b/src/inner/ppb/fpcar.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 3:31 - The location of the unpopulated floating-point register space allocated on an exception stack frame"]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<FPCAR_SPEC> {
         ADDRESS_W::new(self, 3)
     }
diff --git a/src/inner/ppb/fpccr.rs b/src/inner/ppb/fpccr.rs
index 8a59b2c..65244d9 100644
--- a/src/inner/ppb/fpccr.rs
+++ b/src/inner/ppb/fpccr.rs
@@ -160,103 +160,86 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Indicates whether lazy preservation of the floating-point state is active"]
     #[inline(always)]
-    #[must_use]
     pub fn lspact(&mut self) -> LSPACT_W<FPCCR_SPEC> {
         LSPACT_W::new(self, 0)
     }
     #[doc = "Bit 1 - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame"]
     #[inline(always)]
-    #[must_use]
     pub fn user(&mut self) -> USER_W<FPCCR_SPEC> {
         USER_W::new(self, 1)
     }
     #[doc = "Bit 2 - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed"]
     #[inline(always)]
-    #[must_use]
     pub fn s(&mut self) -> S_W<FPCCR_SPEC> {
         S_W::new(self, 2)
     }
     #[doc = "Bit 3 - Indicates the PE mode when it allocated the floating-point stack frame"]
     #[inline(always)]
-    #[must_use]
     pub fn thread(&mut self) -> THREAD_W<FPCCR_SPEC> {
         THREAD_W::new(self, 3)
     }
     #[doc = "Bit 4 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending"]
     #[inline(always)]
-    #[must_use]
     pub fn hfrdy(&mut self) -> HFRDY_W<FPCCR_SPEC> {
         HFRDY_W::new(self, 4)
     }
     #[doc = "Bit 5 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending"]
     #[inline(always)]
-    #[must_use]
     pub fn mmrdy(&mut self) -> MMRDY_W<FPCCR_SPEC> {
         MMRDY_W::new(self, 5)
     }
     #[doc = "Bit 6 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending"]
     #[inline(always)]
-    #[must_use]
     pub fn bfrdy(&mut self) -> BFRDY_W<FPCCR_SPEC> {
         BFRDY_W::new(self, 6)
     }
     #[doc = "Bit 7 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn sfrdy(&mut self) -> SFRDY_W<FPCCR_SPEC> {
         SFRDY_W::new(self, 7)
     }
     #[doc = "Bit 8 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending"]
     #[inline(always)]
-    #[must_use]
     pub fn monrdy(&mut self) -> MONRDY_W<FPCCR_SPEC> {
         MONRDY_W::new(self, 8)
     }
     #[doc = "Bit 9 - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior"]
     #[inline(always)]
-    #[must_use]
     pub fn splimviol(&mut self) -> SPLIMVIOL_W<FPCCR_SPEC> {
         SPLIMVIOL_W::new(self, 9)
     }
     #[doc = "Bit 10 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending"]
     #[inline(always)]
-    #[must_use]
     pub fn ufrdy(&mut self) -> UFRDY_W<FPCCR_SPEC> {
         UFRDY_W::new(self, 10)
     }
     #[doc = "Bit 26 - Treat floating-point registers as Secure enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ts(&mut self) -> TS_W<FPCCR_SPEC> {
         TS_W::new(self, 26)
     }
     #[doc = "Bit 27 - This bit controls whether the CLRONRET bit is writeable from the Non-secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn clronrets(&mut self) -> CLRONRETS_W<FPCCR_SPEC> {
         CLRONRETS_W::new(self, 27)
     }
     #[doc = "Bit 28 - Clear floating-point caller saved registers on exception return"]
     #[inline(always)]
-    #[must_use]
     pub fn clronret(&mut self) -> CLRONRET_W<FPCCR_SPEC> {
         CLRONRET_W::new(self, 28)
     }
     #[doc = "Bit 29 - This bit controls whether the LSPEN bit is writeable from the Non-secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn lspens(&mut self) -> LSPENS_W<FPCCR_SPEC> {
         LSPENS_W::new(self, 29)
     }
     #[doc = "Bit 30 - Enables lazy context save of floating-point state"]
     #[inline(always)]
-    #[must_use]
     pub fn lspen(&mut self) -> LSPEN_W<FPCCR_SPEC> {
         LSPEN_W::new(self, 30)
     }
     #[doc = "Bit 31 - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn aspen(&mut self) -> ASPEN_W<FPCCR_SPEC> {
         ASPEN_W::new(self, 31)
     }
diff --git a/src/inner/ppb/fpdscr.rs b/src/inner/ppb/fpdscr.rs
index 45d312e..95e16b7 100644
--- a/src/inner/ppb/fpdscr.rs
+++ b/src/inner/ppb/fpdscr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 22:23 - Default value for FPSCR.RMode"]
     #[inline(always)]
-    #[must_use]
     pub fn rmode(&mut self) -> RMODE_W<FPDSCR_SPEC> {
         RMODE_W::new(self, 22)
     }
     #[doc = "Bit 24 - Default value for FPSCR.FZ"]
     #[inline(always)]
-    #[must_use]
     pub fn fz(&mut self) -> FZ_W<FPDSCR_SPEC> {
         FZ_W::new(self, 24)
     }
     #[doc = "Bit 25 - Default value for FPSCR.DN"]
     #[inline(always)]
-    #[must_use]
     pub fn dn(&mut self) -> DN_W<FPDSCR_SPEC> {
         DN_W::new(self, 25)
     }
     #[doc = "Bit 26 - Default value for FPSCR.AHP"]
     #[inline(always)]
-    #[must_use]
     pub fn ahp(&mut self) -> AHP_W<FPDSCR_SPEC> {
         AHP_W::new(self, 26)
     }
diff --git a/src/inner/ppb/hfsr.rs b/src/inner/ppb/hfsr.rs
index e52f4ec..1a36e24 100644
--- a/src/inner/ppb/hfsr.rs
+++ b/src/inner/ppb/hfsr.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Indicates when a fault has occurred because of a vector table read error on exception processing"]
     #[inline(always)]
-    #[must_use]
     pub fn vecttbl(&mut self) -> VECTTBL_W<HFSR_SPEC> {
         VECTTBL_W::new(self, 1)
     }
     #[doc = "Bit 30 - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn forced(&mut self) -> FORCED_W<HFSR_SPEC> {
         FORCED_W::new(self, 30)
     }
     #[doc = "Bit 31 - Indicates when a Debug event has occurred"]
     #[inline(always)]
-    #[must_use]
     pub fn debugevt(&mut self) -> DEBUGEVT_W<HFSR_SPEC> {
         DEBUGEVT_W::new(self, 31)
     }
diff --git a/src/inner/ppb/icsr.rs b/src/inner/ppb/icsr.rs
index e84457f..94bc166 100644
--- a/src/inner/ppb/icsr.rs
+++ b/src/inner/ppb/icsr.rs
@@ -99,25 +99,21 @@ impl R {
 impl W {
     #[doc = "Bit 24 - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure"]
     #[inline(always)]
-    #[must_use]
     pub fn sttns(&mut self) -> STTNS_W<ICSR_SPEC> {
         STTNS_W::new(self, 24)
     }
     #[doc = "Bit 25 - Allows the SysTick exception pend state to be cleared `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn pendstclr(&mut self) -> PENDSTCLR_W<ICSR_SPEC> {
         PENDSTCLR_W::new(self, 25)
     }
     #[doc = "Bit 27 - Allows the PendSV exception pend state to be cleared `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn pendsvclr(&mut self) -> PENDSVCLR_W<ICSR_SPEC> {
         PENDSVCLR_W::new(self, 27)
     }
     #[doc = "Bit 30 - Allows the NMI exception pend state to be cleared"]
     #[inline(always)]
-    #[must_use]
     pub fn pendnmiclr(&mut self) -> PENDNMICLR_W<ICSR_SPEC> {
         PENDNMICLR_W::new(self, 30)
     }
diff --git a/src/inner/ppb/id_isar5.rs b/src/inner/ppb/id_isar5.rs
index 6b2fe21..3832239 100644
--- a/src/inner/ppb/id_isar5.rs
+++ b/src/inner/ppb/id_isar5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn id_isar5(&mut self) -> ID_ISAR5_W<ID_ISAR5_SPEC> {
         ID_ISAR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/id_mmfr1.rs b/src/inner/ppb/id_mmfr1.rs
index 90aad4d..651c4ff 100644
--- a/src/inner/ppb/id_mmfr1.rs
+++ b/src/inner/ppb/id_mmfr1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn id_mmfr1(&mut self) -> ID_MMFR1_W<ID_MMFR1_SPEC> {
         ID_MMFR1_W::new(self, 0)
     }
diff --git a/src/inner/ppb/int_atvalid.rs b/src/inner/ppb/int_atvalid.rs
index aa4cf35..79dc6b3 100644
--- a/src/inner/ppb/int_atvalid.rs
+++ b/src/inner/ppb/int_atvalid.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - A write to this bit gives the value of ATVALID"]
     #[inline(always)]
-    #[must_use]
     pub fn atready(&mut self) -> ATREADY_W<INT_ATVALID_SPEC> {
         ATREADY_W::new(self, 0)
     }
     #[doc = "Bit 1 - A write to this bit gives the value of AFREADY"]
     #[inline(always)]
-    #[must_use]
     pub fn afready(&mut self) -> AFREADY_W<INT_ATVALID_SPEC> {
         AFREADY_W::new(self, 1)
     }
diff --git a/src/inner/ppb/itchout.rs b/src/inner/ppb/itchout.rs
index 9e67e9e..54d90b7 100644
--- a/src/inner/ppb/itchout.rs
+++ b/src/inner/ppb/itchout.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Sets the value of the ctichout outputs"]
     #[inline(always)]
-    #[must_use]
     pub fn ctchout(&mut self) -> CTCHOUT_W<ITCHOUT_SPEC> {
         CTCHOUT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itctrl.rs b/src/inner/ppb/itctrl.rs
index cfa7ea8..f44d07b 100644
--- a/src/inner/ppb/itctrl.rs
+++ b/src/inner/ppb/itctrl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Integration Mode Enable"]
     #[inline(always)]
-    #[must_use]
     pub fn ime(&mut self) -> IME_W<ITCTRL_SPEC> {
         IME_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_itctrl.rs b/src/inner/ppb/itm_itctrl.rs
index 7164f7a..7d5f762 100644
--- a/src/inner/ppb/itm_itctrl.rs
+++ b/src/inner/ppb/itm_itctrl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing."]
     #[inline(always)]
-    #[must_use]
     pub fn ime(&mut self) -> IME_W<ITM_ITCTRL_SPEC> {
         IME_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_pidr5.rs b/src/inner/ppb/itm_pidr5.rs
index ae65c3a..890d515 100644
--- a/src/inner/ppb/itm_pidr5.rs
+++ b/src/inner/ppb/itm_pidr5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn itm_pidr5(&mut self) -> ITM_PIDR5_W<ITM_PIDR5_SPEC> {
         ITM_PIDR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_pidr6.rs b/src/inner/ppb/itm_pidr6.rs
index a927533..b83f7bb 100644
--- a/src/inner/ppb/itm_pidr6.rs
+++ b/src/inner/ppb/itm_pidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn itm_pidr6(&mut self) -> ITM_PIDR6_W<ITM_PIDR6_SPEC> {
         ITM_PIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_pidr7.rs b/src/inner/ppb/itm_pidr7.rs
index 765f19e..6fe958c 100644
--- a/src/inner/ppb/itm_pidr7.rs
+++ b/src/inner/ppb/itm_pidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn itm_pidr7(&mut self) -> ITM_PIDR7_W<ITM_PIDR7_SPEC> {
         ITM_PIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim0.rs b/src/inner/ppb/itm_stim0.rs
index dda36a8..29b3c7f 100644
--- a/src/inner/ppb/itm_stim0.rs
+++ b/src/inner/ppb/itm_stim0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM0_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim1.rs b/src/inner/ppb/itm_stim1.rs
index 0b53299..bd421e9 100644
--- a/src/inner/ppb/itm_stim1.rs
+++ b/src/inner/ppb/itm_stim1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM1_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim10.rs b/src/inner/ppb/itm_stim10.rs
index c2e4edf..2fcb638 100644
--- a/src/inner/ppb/itm_stim10.rs
+++ b/src/inner/ppb/itm_stim10.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM10_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim11.rs b/src/inner/ppb/itm_stim11.rs
index 401dd9f..55f9857 100644
--- a/src/inner/ppb/itm_stim11.rs
+++ b/src/inner/ppb/itm_stim11.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM11_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim12.rs b/src/inner/ppb/itm_stim12.rs
index ca7c2cd..1bf24f5 100644
--- a/src/inner/ppb/itm_stim12.rs
+++ b/src/inner/ppb/itm_stim12.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM12_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim13.rs b/src/inner/ppb/itm_stim13.rs
index c4612ee..aeb3cb9 100644
--- a/src/inner/ppb/itm_stim13.rs
+++ b/src/inner/ppb/itm_stim13.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM13_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim14.rs b/src/inner/ppb/itm_stim14.rs
index ec1092d..847b090 100644
--- a/src/inner/ppb/itm_stim14.rs
+++ b/src/inner/ppb/itm_stim14.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM14_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim15.rs b/src/inner/ppb/itm_stim15.rs
index 757f2c4..4ea3cfd 100644
--- a/src/inner/ppb/itm_stim15.rs
+++ b/src/inner/ppb/itm_stim15.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM15_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim16.rs b/src/inner/ppb/itm_stim16.rs
index 9032024..ea40005 100644
--- a/src/inner/ppb/itm_stim16.rs
+++ b/src/inner/ppb/itm_stim16.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM16_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim17.rs b/src/inner/ppb/itm_stim17.rs
index c9be667..5769c02 100644
--- a/src/inner/ppb/itm_stim17.rs
+++ b/src/inner/ppb/itm_stim17.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM17_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim18.rs b/src/inner/ppb/itm_stim18.rs
index 01e35d5..14e8742 100644
--- a/src/inner/ppb/itm_stim18.rs
+++ b/src/inner/ppb/itm_stim18.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM18_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim19.rs b/src/inner/ppb/itm_stim19.rs
index 5ee2bd4..c06383d 100644
--- a/src/inner/ppb/itm_stim19.rs
+++ b/src/inner/ppb/itm_stim19.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM19_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim2.rs b/src/inner/ppb/itm_stim2.rs
index dd19b59..eaab058 100644
--- a/src/inner/ppb/itm_stim2.rs
+++ b/src/inner/ppb/itm_stim2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM2_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim20.rs b/src/inner/ppb/itm_stim20.rs
index b0e295f..e9418d5 100644
--- a/src/inner/ppb/itm_stim20.rs
+++ b/src/inner/ppb/itm_stim20.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM20_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim21.rs b/src/inner/ppb/itm_stim21.rs
index 09ef63f..f2eb8a8 100644
--- a/src/inner/ppb/itm_stim21.rs
+++ b/src/inner/ppb/itm_stim21.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM21_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim22.rs b/src/inner/ppb/itm_stim22.rs
index dd0441a..6e643ec 100644
--- a/src/inner/ppb/itm_stim22.rs
+++ b/src/inner/ppb/itm_stim22.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM22_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim23.rs b/src/inner/ppb/itm_stim23.rs
index 9d1e34c..678b679 100644
--- a/src/inner/ppb/itm_stim23.rs
+++ b/src/inner/ppb/itm_stim23.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM23_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim24.rs b/src/inner/ppb/itm_stim24.rs
index 9f3f26e..fbb37d7 100644
--- a/src/inner/ppb/itm_stim24.rs
+++ b/src/inner/ppb/itm_stim24.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM24_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim25.rs b/src/inner/ppb/itm_stim25.rs
index da45740..eedfbee 100644
--- a/src/inner/ppb/itm_stim25.rs
+++ b/src/inner/ppb/itm_stim25.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM25_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim26.rs b/src/inner/ppb/itm_stim26.rs
index f58d790..207932e 100644
--- a/src/inner/ppb/itm_stim26.rs
+++ b/src/inner/ppb/itm_stim26.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM26_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim27.rs b/src/inner/ppb/itm_stim27.rs
index 7618e8a..58cc1c7 100644
--- a/src/inner/ppb/itm_stim27.rs
+++ b/src/inner/ppb/itm_stim27.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM27_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim28.rs b/src/inner/ppb/itm_stim28.rs
index 4ba4209..bc1ddcc 100644
--- a/src/inner/ppb/itm_stim28.rs
+++ b/src/inner/ppb/itm_stim28.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM28_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim29.rs b/src/inner/ppb/itm_stim29.rs
index 97dd93a..fda0298 100644
--- a/src/inner/ppb/itm_stim29.rs
+++ b/src/inner/ppb/itm_stim29.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM29_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim3.rs b/src/inner/ppb/itm_stim3.rs
index cade7dc..937d2b7 100644
--- a/src/inner/ppb/itm_stim3.rs
+++ b/src/inner/ppb/itm_stim3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM3_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim30.rs b/src/inner/ppb/itm_stim30.rs
index c30f423..e8bbdfa 100644
--- a/src/inner/ppb/itm_stim30.rs
+++ b/src/inner/ppb/itm_stim30.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM30_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim31.rs b/src/inner/ppb/itm_stim31.rs
index 404edd0..bacf508 100644
--- a/src/inner/ppb/itm_stim31.rs
+++ b/src/inner/ppb/itm_stim31.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM31_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim4.rs b/src/inner/ppb/itm_stim4.rs
index bbb1c07..2494b55 100644
--- a/src/inner/ppb/itm_stim4.rs
+++ b/src/inner/ppb/itm_stim4.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM4_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim5.rs b/src/inner/ppb/itm_stim5.rs
index e5ff22b..c3970f0 100644
--- a/src/inner/ppb/itm_stim5.rs
+++ b/src/inner/ppb/itm_stim5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM5_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim6.rs b/src/inner/ppb/itm_stim6.rs
index 1c58269..95a794e 100644
--- a/src/inner/ppb/itm_stim6.rs
+++ b/src/inner/ppb/itm_stim6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM6_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim7.rs b/src/inner/ppb/itm_stim7.rs
index 7d1832e..e99ed12 100644
--- a/src/inner/ppb/itm_stim7.rs
+++ b/src/inner/ppb/itm_stim7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM7_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim8.rs b/src/inner/ppb/itm_stim8.rs
index 08d21f5..740a773 100644
--- a/src/inner/ppb/itm_stim8.rs
+++ b/src/inner/ppb/itm_stim8.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM8_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_stim9.rs b/src/inner/ppb/itm_stim9.rs
index 1284601..0ca85d8 100644
--- a/src/inner/ppb/itm_stim9.rs
+++ b/src/inner/ppb/itm_stim9.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."]
     #[inline(always)]
-    #[must_use]
     pub fn stimulus(&mut self) -> STIMULUS_W<ITM_STIM9_SPEC> {
         STIMULUS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_tcr.rs b/src/inner/ppb/itm_tcr.rs
index fdedf06..5e3539a 100644
--- a/src/inner/ppb/itm_tcr.rs
+++ b/src/inner/ppb/itm_tcr.rs
@@ -95,55 +95,46 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables the ITM"]
     #[inline(always)]
-    #[must_use]
     pub fn itmena(&mut self) -> ITMENA_W<ITM_TCR_SPEC> {
         ITMENA_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enables Local timestamp generation"]
     #[inline(always)]
-    #[must_use]
     pub fn tsena(&mut self) -> TSENA_W<ITM_TCR_SPEC> {
         TSENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - Enables Synchronization packet transmission for a synchronous TPIU"]
     #[inline(always)]
-    #[must_use]
     pub fn syncena(&mut self) -> SYNCENA_W<ITM_TCR_SPEC> {
         SYNCENA_W::new(self, 2)
     }
     #[doc = "Bit 3 - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU"]
     #[inline(always)]
-    #[must_use]
     pub fn txena(&mut self) -> TXENA_W<ITM_TCR_SPEC> {
         TXENA_W::new(self, 3)
     }
     #[doc = "Bit 4 - Enables asynchronous clocking of the timestamp counter"]
     #[inline(always)]
-    #[must_use]
     pub fn swoena(&mut self) -> SWOENA_W<ITM_TCR_SPEC> {
         SWOENA_W::new(self, 4)
     }
     #[doc = "Bit 5 - Stall the PE to guarantee delivery of Data Trace packets."]
     #[inline(always)]
-    #[must_use]
     pub fn stallena(&mut self) -> STALLENA_W<ITM_TCR_SPEC> {
         STALLENA_W::new(self, 5)
     }
     #[doc = "Bits 8:9 - Local timestamp prescaler, used with the trace packet reference clock"]
     #[inline(always)]
-    #[must_use]
     pub fn tsprescale(&mut self) -> TSPRESCALE_W<ITM_TCR_SPEC> {
         TSPRESCALE_W::new(self, 8)
     }
     #[doc = "Bits 10:11 - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps"]
     #[inline(always)]
-    #[must_use]
     pub fn gtsfreq(&mut self) -> GTSFREQ_W<ITM_TCR_SPEC> {
         GTSFREQ_W::new(self, 10)
     }
     #[doc = "Bits 16:22 - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field"]
     #[inline(always)]
-    #[must_use]
     pub fn tracebusid(&mut self) -> TRACEBUSID_W<ITM_TCR_SPEC> {
         TRACEBUSID_W::new(self, 16)
     }
diff --git a/src/inner/ppb/itm_ter0.rs b/src/inner/ppb/itm_ter0.rs
index b1b6e07..6846b1a 100644
--- a/src/inner/ppb/itm_ter0.rs
+++ b/src/inner/ppb/itm_ter0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For STIMENA\\[m\\]
 in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn stimena(&mut self) -> STIMENA_W<ITM_TER0_SPEC> {
         STIMENA_W::new(self, 0)
     }
diff --git a/src/inner/ppb/itm_tpr.rs b/src/inner/ppb/itm_tpr.rs
index 149f217..772938d 100644
--- a/src/inner/ppb/itm_tpr.rs
+++ b/src/inner/ppb/itm_tpr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Bit mask to enable tracing on ITM stimulus ports"]
     #[inline(always)]
-    #[must_use]
     pub fn privmask(&mut self) -> PRIVMASK_W<ITM_TPR_SPEC> {
         PRIVMASK_W::new(self, 0)
     }
diff --git a/src/inner/ppb/ittrigout.rs b/src/inner/ppb/ittrigout.rs
index 394c858..b469421 100644
--- a/src/inner/ppb/ittrigout.rs
+++ b/src/inner/ppb/ittrigout.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Sets the value of the ctitrigout outputs"]
     #[inline(always)]
-    #[must_use]
     pub fn cttrigout(&mut self) -> CTTRIGOUT_W<ITTRIGOUT_SPEC> {
         CTTRIGOUT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/mmfar.rs b/src/inner/ppb/mmfar.rs
index e35f558..26bbf70 100644
--- a/src/inner/ppb/mmfar.rs
+++ b/src/inner/ppb/mmfar.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN"]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<MMFAR_SPEC> {
         ADDRESS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/mpu_ctrl.rs b/src/inner/ppb/mpu_ctrl.rs
index b24bf92..74300e3 100644
--- a/src/inner/ppb/mpu_ctrl.rs
+++ b/src/inner/ppb/mpu_ctrl.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables the MPU"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<MPU_CTRL_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"]
     #[inline(always)]
-    #[must_use]
     pub fn hfnmiena(&mut self) -> HFNMIENA_W<MPU_CTRL_SPEC> {
         HFNMIENA_W::new(self, 1)
     }
     #[doc = "Bit 2 - Controls whether the default memory map is enabled for privileged software"]
     #[inline(always)]
-    #[must_use]
     pub fn privdefena(&mut self) -> PRIVDEFENA_W<MPU_CTRL_SPEC> {
         PRIVDEFENA_W::new(self, 2)
     }
diff --git a/src/inner/ppb/mpu_mair0.rs b/src/inner/ppb/mpu_mair0.rs
index a557403..0d8bd47 100644
--- a/src/inner/ppb/mpu_mair0.rs
+++ b/src/inner/ppb/mpu_mair0.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Memory attribute encoding for MPU regions with an AttrIndex of 0"]
     #[inline(always)]
-    #[must_use]
     pub fn attr0(&mut self) -> ATTR0_W<MPU_MAIR0_SPEC> {
         ATTR0_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - Memory attribute encoding for MPU regions with an AttrIndex of 1"]
     #[inline(always)]
-    #[must_use]
     pub fn attr1(&mut self) -> ATTR1_W<MPU_MAIR0_SPEC> {
         ATTR1_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - Memory attribute encoding for MPU regions with an AttrIndex of 2"]
     #[inline(always)]
-    #[must_use]
     pub fn attr2(&mut self) -> ATTR2_W<MPU_MAIR0_SPEC> {
         ATTR2_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - Memory attribute encoding for MPU regions with an AttrIndex of 3"]
     #[inline(always)]
-    #[must_use]
     pub fn attr3(&mut self) -> ATTR3_W<MPU_MAIR0_SPEC> {
         ATTR3_W::new(self, 24)
     }
diff --git a/src/inner/ppb/mpu_mair1.rs b/src/inner/ppb/mpu_mair1.rs
index 79ae75a..a258d9f 100644
--- a/src/inner/ppb/mpu_mair1.rs
+++ b/src/inner/ppb/mpu_mair1.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Memory attribute encoding for MPU regions with an AttrIndex of 4"]
     #[inline(always)]
-    #[must_use]
     pub fn attr4(&mut self) -> ATTR4_W<MPU_MAIR1_SPEC> {
         ATTR4_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - Memory attribute encoding for MPU regions with an AttrIndex of 5"]
     #[inline(always)]
-    #[must_use]
     pub fn attr5(&mut self) -> ATTR5_W<MPU_MAIR1_SPEC> {
         ATTR5_W::new(self, 8)
     }
     #[doc = "Bits 16:23 - Memory attribute encoding for MPU regions with an AttrIndex of 6"]
     #[inline(always)]
-    #[must_use]
     pub fn attr6(&mut self) -> ATTR6_W<MPU_MAIR1_SPEC> {
         ATTR6_W::new(self, 16)
     }
     #[doc = "Bits 24:31 - Memory attribute encoding for MPU regions with an AttrIndex of 7"]
     #[inline(always)]
-    #[must_use]
     pub fn attr7(&mut self) -> ATTR7_W<MPU_MAIR1_SPEC> {
         ATTR7_W::new(self, 24)
     }
diff --git a/src/inner/ppb/mpu_rbar.rs b/src/inner/ppb/mpu_rbar.rs
index affb63c..c4186e7 100644
--- a/src/inner/ppb/mpu_rbar.rs
+++ b/src/inner/ppb/mpu_rbar.rs
@@ -46,26 +46,22 @@ of the lower inclusive limit of the selected MPU memory region. This value is ze
 impl W {
     #[doc = "Bit 0 - Defines whether code can be executed from this region"]
     #[inline(always)]
-    #[must_use]
     pub fn xn(&mut self) -> XN_W<MPU_RBAR_SPEC> {
         XN_W::new(self, 0)
     }
     #[doc = "Bits 1:2 - Defines the access permissions for this region"]
     #[inline(always)]
-    #[must_use]
     pub fn ap(&mut self) -> AP_W<MPU_RBAR_SPEC> {
         AP_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"]
     #[inline(always)]
-    #[must_use]
     pub fn sh(&mut self) -> SH_W<MPU_RBAR_SPEC> {
         SH_W::new(self, 3)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<MPU_RBAR_SPEC> {
         BASE_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rbar_a1.rs b/src/inner/ppb/mpu_rbar_a1.rs
index 9084426..3edb2db 100644
--- a/src/inner/ppb/mpu_rbar_a1.rs
+++ b/src/inner/ppb/mpu_rbar_a1.rs
@@ -46,26 +46,22 @@ of the lower inclusive limit of the selected MPU memory region. This value is ze
 impl W {
     #[doc = "Bit 0 - Defines whether code can be executed from this region"]
     #[inline(always)]
-    #[must_use]
     pub fn xn(&mut self) -> XN_W<MPU_RBAR_A1_SPEC> {
         XN_W::new(self, 0)
     }
     #[doc = "Bits 1:2 - Defines the access permissions for this region"]
     #[inline(always)]
-    #[must_use]
     pub fn ap(&mut self) -> AP_W<MPU_RBAR_A1_SPEC> {
         AP_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"]
     #[inline(always)]
-    #[must_use]
     pub fn sh(&mut self) -> SH_W<MPU_RBAR_A1_SPEC> {
         SH_W::new(self, 3)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<MPU_RBAR_A1_SPEC> {
         BASE_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rbar_a2.rs b/src/inner/ppb/mpu_rbar_a2.rs
index 0bcd941..abc00b2 100644
--- a/src/inner/ppb/mpu_rbar_a2.rs
+++ b/src/inner/ppb/mpu_rbar_a2.rs
@@ -46,26 +46,22 @@ of the lower inclusive limit of the selected MPU memory region. This value is ze
 impl W {
     #[doc = "Bit 0 - Defines whether code can be executed from this region"]
     #[inline(always)]
-    #[must_use]
     pub fn xn(&mut self) -> XN_W<MPU_RBAR_A2_SPEC> {
         XN_W::new(self, 0)
     }
     #[doc = "Bits 1:2 - Defines the access permissions for this region"]
     #[inline(always)]
-    #[must_use]
     pub fn ap(&mut self) -> AP_W<MPU_RBAR_A2_SPEC> {
         AP_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"]
     #[inline(always)]
-    #[must_use]
     pub fn sh(&mut self) -> SH_W<MPU_RBAR_A2_SPEC> {
         SH_W::new(self, 3)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<MPU_RBAR_A2_SPEC> {
         BASE_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rbar_a3.rs b/src/inner/ppb/mpu_rbar_a3.rs
index 6395feb..34e344d 100644
--- a/src/inner/ppb/mpu_rbar_a3.rs
+++ b/src/inner/ppb/mpu_rbar_a3.rs
@@ -46,26 +46,22 @@ of the lower inclusive limit of the selected MPU memory region. This value is ze
 impl W {
     #[doc = "Bit 0 - Defines whether code can be executed from this region"]
     #[inline(always)]
-    #[must_use]
     pub fn xn(&mut self) -> XN_W<MPU_RBAR_A3_SPEC> {
         XN_W::new(self, 0)
     }
     #[doc = "Bits 1:2 - Defines the access permissions for this region"]
     #[inline(always)]
-    #[must_use]
     pub fn ap(&mut self) -> AP_W<MPU_RBAR_A3_SPEC> {
         AP_W::new(self, 1)
     }
     #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"]
     #[inline(always)]
-    #[must_use]
     pub fn sh(&mut self) -> SH_W<MPU_RBAR_A3_SPEC> {
         SH_W::new(self, 3)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<MPU_RBAR_A3_SPEC> {
         BASE_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rlar.rs b/src/inner/ppb/mpu_rlar.rs
index 3505398..c600a77 100644
--- a/src/inner/ppb/mpu_rlar.rs
+++ b/src/inner/ppb/mpu_rlar.rs
@@ -37,20 +37,17 @@ of the upper inclusive limit of the selected MPU memory region. This value is po
 impl W {
     #[doc = "Bit 0 - Region enable"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_RLAR_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"]
     #[inline(always)]
-    #[must_use]
     pub fn attrindx(&mut self) -> ATTRINDX_W<MPU_RLAR_SPEC> {
         ATTRINDX_W::new(self, 1)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn limit(&mut self) -> LIMIT_W<MPU_RLAR_SPEC> {
         LIMIT_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rlar_a1.rs b/src/inner/ppb/mpu_rlar_a1.rs
index bd37f49..ec9878c 100644
--- a/src/inner/ppb/mpu_rlar_a1.rs
+++ b/src/inner/ppb/mpu_rlar_a1.rs
@@ -37,20 +37,17 @@ of the upper inclusive limit of the selected MPU memory region. This value is po
 impl W {
     #[doc = "Bit 0 - Region enable"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_RLAR_A1_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"]
     #[inline(always)]
-    #[must_use]
     pub fn attrindx(&mut self) -> ATTRINDX_W<MPU_RLAR_A1_SPEC> {
         ATTRINDX_W::new(self, 1)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn limit(&mut self) -> LIMIT_W<MPU_RLAR_A1_SPEC> {
         LIMIT_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rlar_a2.rs b/src/inner/ppb/mpu_rlar_a2.rs
index b272c20..6647b8d 100644
--- a/src/inner/ppb/mpu_rlar_a2.rs
+++ b/src/inner/ppb/mpu_rlar_a2.rs
@@ -37,20 +37,17 @@ of the upper inclusive limit of the selected MPU memory region. This value is po
 impl W {
     #[doc = "Bit 0 - Region enable"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_RLAR_A2_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"]
     #[inline(always)]
-    #[must_use]
     pub fn attrindx(&mut self) -> ATTRINDX_W<MPU_RLAR_A2_SPEC> {
         ATTRINDX_W::new(self, 1)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn limit(&mut self) -> LIMIT_W<MPU_RLAR_A2_SPEC> {
         LIMIT_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rlar_a3.rs b/src/inner/ppb/mpu_rlar_a3.rs
index 4c48ca9..0ac6dc4 100644
--- a/src/inner/ppb/mpu_rlar_a3.rs
+++ b/src/inner/ppb/mpu_rlar_a3.rs
@@ -37,20 +37,17 @@ of the upper inclusive limit of the selected MPU memory region. This value is po
 impl W {
     #[doc = "Bit 0 - Region enable"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MPU_RLAR_A3_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"]
     #[inline(always)]
-    #[must_use]
     pub fn attrindx(&mut self) -> ATTRINDX_W<MPU_RLAR_A3_SPEC> {
         ATTRINDX_W::new(self, 1)
     }
     #[doc = "Bits 5:31 - Contains bits \\[31:5\\]
 of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"]
     #[inline(always)]
-    #[must_use]
     pub fn limit(&mut self) -> LIMIT_W<MPU_RLAR_A3_SPEC> {
         LIMIT_W::new(self, 5)
     }
diff --git a/src/inner/ppb/mpu_rnr.rs b/src/inner/ppb/mpu_rnr.rs
index 9ea1d9c..5a83069 100644
--- a/src/inner/ppb/mpu_rnr.rs
+++ b/src/inner/ppb/mpu_rnr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:2 - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR"]
     #[inline(always)]
-    #[must_use]
     pub fn region(&mut self) -> REGION_W<MPU_RNR_SPEC> {
         REGION_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nsacr.rs b/src/inner/ppb/nsacr.rs
index 0b004c4..feef016 100644
--- a/src/inner/ppb/nsacr.rs
+++ b/src/inner/ppb/nsacr.rs
@@ -97,61 +97,51 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables Non-secure access to coprocessor CP0"]
     #[inline(always)]
-    #[must_use]
     pub fn cp0(&mut self) -> CP0_W<NSACR_SPEC> {
         CP0_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enables Non-secure access to coprocessor CP1"]
     #[inline(always)]
-    #[must_use]
     pub fn cp1(&mut self) -> CP1_W<NSACR_SPEC> {
         CP1_W::new(self, 1)
     }
     #[doc = "Bit 2 - Enables Non-secure access to coprocessor CP2"]
     #[inline(always)]
-    #[must_use]
     pub fn cp2(&mut self) -> CP2_W<NSACR_SPEC> {
         CP2_W::new(self, 2)
     }
     #[doc = "Bit 3 - Enables Non-secure access to coprocessor CP3"]
     #[inline(always)]
-    #[must_use]
     pub fn cp3(&mut self) -> CP3_W<NSACR_SPEC> {
         CP3_W::new(self, 3)
     }
     #[doc = "Bit 4 - Enables Non-secure access to coprocessor CP4"]
     #[inline(always)]
-    #[must_use]
     pub fn cp4(&mut self) -> CP4_W<NSACR_SPEC> {
         CP4_W::new(self, 4)
     }
     #[doc = "Bit 5 - Enables Non-secure access to coprocessor CP5"]
     #[inline(always)]
-    #[must_use]
     pub fn cp5(&mut self) -> CP5_W<NSACR_SPEC> {
         CP5_W::new(self, 5)
     }
     #[doc = "Bit 6 - Enables Non-secure access to coprocessor CP6"]
     #[inline(always)]
-    #[must_use]
     pub fn cp6(&mut self) -> CP6_W<NSACR_SPEC> {
         CP6_W::new(self, 6)
     }
     #[doc = "Bit 7 - Enables Non-secure access to coprocessor CP7"]
     #[inline(always)]
-    #[must_use]
     pub fn cp7(&mut self) -> CP7_W<NSACR_SPEC> {
         CP7_W::new(self, 7)
     }
     #[doc = "Bit 10 - Enables Non-secure access to the Floating-point Extension"]
     #[inline(always)]
-    #[must_use]
     pub fn cp10(&mut self) -> CP10_W<NSACR_SPEC> {
         CP10_W::new(self, 10)
     }
     #[doc = "Bit 11 - Enables Non-secure access to the Floating-point Extension"]
     #[inline(always)]
-    #[must_use]
     pub fn cp11(&mut self) -> CP11_W<NSACR_SPEC> {
         CP11_W::new(self, 11)
     }
diff --git a/src/inner/ppb/nvic_iabr0.rs b/src/inner/ppb/nvic_iabr0.rs
index 74a2c2d..e435c4e 100644
--- a/src/inner/ppb/nvic_iabr0.rs
+++ b/src/inner/ppb/nvic_iabr0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For ACTIVE\\[m\\]
 in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"]
     #[inline(always)]
-    #[must_use]
     pub fn active(&mut self) -> ACTIVE_W<NVIC_IABR0_SPEC> {
         ACTIVE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_iabr1.rs b/src/inner/ppb/nvic_iabr1.rs
index 9723261..f7cedb1 100644
--- a/src/inner/ppb/nvic_iabr1.rs
+++ b/src/inner/ppb/nvic_iabr1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For ACTIVE\\[m\\]
 in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"]
     #[inline(always)]
-    #[must_use]
     pub fn active(&mut self) -> ACTIVE_W<NVIC_IABR1_SPEC> {
         ACTIVE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_icer0.rs b/src/inner/ppb/nvic_icer0.rs
index 7491e29..d79fa88 100644
--- a/src/inner/ppb/nvic_icer0.rs
+++ b/src/inner/ppb/nvic_icer0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For CLRENA\\[m\\]
 in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn clrena(&mut self) -> CLRENA_W<NVIC_ICER0_SPEC> {
         CLRENA_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_icer1.rs b/src/inner/ppb/nvic_icer1.rs
index cb0befd..c0e5081 100644
--- a/src/inner/ppb/nvic_icer1.rs
+++ b/src/inner/ppb/nvic_icer1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For CLRENA\\[m\\]
 in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn clrena(&mut self) -> CLRENA_W<NVIC_ICER1_SPEC> {
         CLRENA_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_icpr0.rs b/src/inner/ppb/nvic_icpr0.rs
index 5f487d9..85e7cb9 100644
--- a/src/inner/ppb/nvic_icpr0.rs
+++ b/src/inner/ppb/nvic_icpr0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For CLRPEND\\[m\\]
 in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"]
     #[inline(always)]
-    #[must_use]
     pub fn clrpend(&mut self) -> CLRPEND_W<NVIC_ICPR0_SPEC> {
         CLRPEND_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_icpr1.rs b/src/inner/ppb/nvic_icpr1.rs
index 7ac911e..c56b1f3 100644
--- a/src/inner/ppb/nvic_icpr1.rs
+++ b/src/inner/ppb/nvic_icpr1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For CLRPEND\\[m\\]
 in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"]
     #[inline(always)]
-    #[must_use]
     pub fn clrpend(&mut self) -> CLRPEND_W<NVIC_ICPR1_SPEC> {
         CLRPEND_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_ipr0.rs b/src/inner/ppb/nvic_ipr0.rs
index 5550bb3..cb853ff 100644
--- a/src/inner/ppb/nvic_ipr0.rs
+++ b/src/inner/ppb/nvic_ipr0.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR0_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR0_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR0_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR0_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr1.rs b/src/inner/ppb/nvic_ipr1.rs
index 6a87e1e..53bbdd0 100644
--- a/src/inner/ppb/nvic_ipr1.rs
+++ b/src/inner/ppb/nvic_ipr1.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR1_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR1_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR1_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR1_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr10.rs b/src/inner/ppb/nvic_ipr10.rs
index 443fe83..fd6c4d0 100644
--- a/src/inner/ppb/nvic_ipr10.rs
+++ b/src/inner/ppb/nvic_ipr10.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR10_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR10_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR10_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR10_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr11.rs b/src/inner/ppb/nvic_ipr11.rs
index 8df0716..82cd5f1 100644
--- a/src/inner/ppb/nvic_ipr11.rs
+++ b/src/inner/ppb/nvic_ipr11.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR11_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR11_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR11_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR11_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr12.rs b/src/inner/ppb/nvic_ipr12.rs
index dad3e70..a6c885f 100644
--- a/src/inner/ppb/nvic_ipr12.rs
+++ b/src/inner/ppb/nvic_ipr12.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR12_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR12_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR12_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR12_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr13.rs b/src/inner/ppb/nvic_ipr13.rs
index bfaadb6..049bfa0 100644
--- a/src/inner/ppb/nvic_ipr13.rs
+++ b/src/inner/ppb/nvic_ipr13.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR13_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR13_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR13_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR13_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr14.rs b/src/inner/ppb/nvic_ipr14.rs
index 830c3c3..f4db469 100644
--- a/src/inner/ppb/nvic_ipr14.rs
+++ b/src/inner/ppb/nvic_ipr14.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR14_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR14_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR14_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR14_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr15.rs b/src/inner/ppb/nvic_ipr15.rs
index bc7e571..1380898 100644
--- a/src/inner/ppb/nvic_ipr15.rs
+++ b/src/inner/ppb/nvic_ipr15.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR15_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR15_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR15_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR15_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr2.rs b/src/inner/ppb/nvic_ipr2.rs
index f1d6c2d..4192293 100644
--- a/src/inner/ppb/nvic_ipr2.rs
+++ b/src/inner/ppb/nvic_ipr2.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR2_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR2_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR2_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR2_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr3.rs b/src/inner/ppb/nvic_ipr3.rs
index a60ed71..14f301a 100644
--- a/src/inner/ppb/nvic_ipr3.rs
+++ b/src/inner/ppb/nvic_ipr3.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR3_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR3_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR3_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR3_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr4.rs b/src/inner/ppb/nvic_ipr4.rs
index 5afe57c..d266ff8 100644
--- a/src/inner/ppb/nvic_ipr4.rs
+++ b/src/inner/ppb/nvic_ipr4.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR4_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR4_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR4_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR4_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr5.rs b/src/inner/ppb/nvic_ipr5.rs
index d093c80..5a43efc 100644
--- a/src/inner/ppb/nvic_ipr5.rs
+++ b/src/inner/ppb/nvic_ipr5.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR5_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR5_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR5_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR5_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr6.rs b/src/inner/ppb/nvic_ipr6.rs
index 92b2005..0452d8f 100644
--- a/src/inner/ppb/nvic_ipr6.rs
+++ b/src/inner/ppb/nvic_ipr6.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR6_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR6_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR6_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR6_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr7.rs b/src/inner/ppb/nvic_ipr7.rs
index a6111fa..01ed369 100644
--- a/src/inner/ppb/nvic_ipr7.rs
+++ b/src/inner/ppb/nvic_ipr7.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR7_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR7_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR7_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR7_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr8.rs b/src/inner/ppb/nvic_ipr8.rs
index 31e8fa0..b9c86b2 100644
--- a/src/inner/ppb/nvic_ipr8.rs
+++ b/src/inner/ppb/nvic_ipr8.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR8_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR8_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR8_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR8_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_ipr9.rs b/src/inner/ppb/nvic_ipr9.rs
index 72fe9e5..44db599 100644
--- a/src/inner/ppb/nvic_ipr9.rs
+++ b/src/inner/ppb/nvic_ipr9.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n0(&mut self) -> PRI_N0_W<NVIC_IPR9_SPEC> {
         PRI_N0_W::new(self, 4)
     }
     #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n1(&mut self) -> PRI_N1_W<NVIC_IPR9_SPEC> {
         PRI_N1_W::new(self, 12)
     }
     #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n2(&mut self) -> PRI_N2_W<NVIC_IPR9_SPEC> {
         PRI_N2_W::new(self, 20)
     }
     #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_n3(&mut self) -> PRI_N3_W<NVIC_IPR9_SPEC> {
         PRI_N3_W::new(self, 28)
     }
diff --git a/src/inner/ppb/nvic_iser0.rs b/src/inner/ppb/nvic_iser0.rs
index 947d5da..bc49025 100644
--- a/src/inner/ppb/nvic_iser0.rs
+++ b/src/inner/ppb/nvic_iser0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For SETENA\\[m\\]
 in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn setena(&mut self) -> SETENA_W<NVIC_ISER0_SPEC> {
         SETENA_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_iser1.rs b/src/inner/ppb/nvic_iser1.rs
index 1ee6135..d7e0fc5 100644
--- a/src/inner/ppb/nvic_iser1.rs
+++ b/src/inner/ppb/nvic_iser1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For SETENA\\[m\\]
 in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn setena(&mut self) -> SETENA_W<NVIC_ISER1_SPEC> {
         SETENA_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_ispr0.rs b/src/inner/ppb/nvic_ispr0.rs
index 71aee7b..0602840 100644
--- a/src/inner/ppb/nvic_ispr0.rs
+++ b/src/inner/ppb/nvic_ispr0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For SETPEND\\[m\\]
 in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"]
     #[inline(always)]
-    #[must_use]
     pub fn setpend(&mut self) -> SETPEND_W<NVIC_ISPR0_SPEC> {
         SETPEND_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_ispr1.rs b/src/inner/ppb/nvic_ispr1.rs
index 031fbad..6675698 100644
--- a/src/inner/ppb/nvic_ispr1.rs
+++ b/src/inner/ppb/nvic_ispr1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For SETPEND\\[m\\]
 in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"]
     #[inline(always)]
-    #[must_use]
     pub fn setpend(&mut self) -> SETPEND_W<NVIC_ISPR1_SPEC> {
         SETPEND_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_itns0.rs b/src/inner/ppb/nvic_itns0.rs
index 00cfc77..a1fe7a8 100644
--- a/src/inner/ppb/nvic_itns0.rs
+++ b/src/inner/ppb/nvic_itns0.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For ITNS\\[m\\]
 in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"]
     #[inline(always)]
-    #[must_use]
     pub fn itns(&mut self) -> ITNS_W<NVIC_ITNS0_SPEC> {
         ITNS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/nvic_itns1.rs b/src/inner/ppb/nvic_itns1.rs
index 9809a3e..2dbc96b 100644
--- a/src/inner/ppb/nvic_itns1.rs
+++ b/src/inner/ppb/nvic_itns1.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:31 - For ITNS\\[m\\]
 in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"]
     #[inline(always)]
-    #[must_use]
     pub fn itns(&mut self) -> ITNS_W<NVIC_ITNS1_SPEC> {
         ITNS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/pidr5.rs b/src/inner/ppb/pidr5.rs
index 00dec17..2aa4a3a 100644
--- a/src/inner/ppb/pidr5.rs
+++ b/src/inner/ppb/pidr5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn pidr5(&mut self) -> PIDR5_W<PIDR5_SPEC> {
         PIDR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/pidr6.rs b/src/inner/ppb/pidr6.rs
index b661863..070c06f 100644
--- a/src/inner/ppb/pidr6.rs
+++ b/src/inner/ppb/pidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn pidr6(&mut self) -> PIDR6_W<PIDR6_SPEC> {
         PIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/pidr7.rs b/src/inner/ppb/pidr7.rs
index a4af7c7..42add8c 100644
--- a/src/inner/ppb/pidr7.rs
+++ b/src/inner/ppb/pidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn pidr7(&mut self) -> PIDR7_W<PIDR7_SPEC> {
         PIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/sau_ctrl.rs b/src/inner/ppb/sau_ctrl.rs
index 2207005..4bf12fa 100644
--- a/src/inner/ppb/sau_ctrl.rs
+++ b/src/inner/ppb/sau_ctrl.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enables the SAU"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<SAU_CTRL_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure"]
     #[inline(always)]
-    #[must_use]
     pub fn allns(&mut self) -> ALLNS_W<SAU_CTRL_SPEC> {
         ALLNS_W::new(self, 1)
     }
diff --git a/src/inner/ppb/sau_rbar.rs b/src/inner/ppb/sau_rbar.rs
index 111eec9..9727332 100644
--- a/src/inner/ppb/sau_rbar.rs
+++ b/src/inner/ppb/sau_rbar.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 5:31 - Holds bits \\[31:5\\]
 of the base address for the selected SAU region"]
     #[inline(always)]
-    #[must_use]
     pub fn baddr(&mut self) -> BADDR_W<SAU_RBAR_SPEC> {
         BADDR_W::new(self, 5)
     }
diff --git a/src/inner/ppb/sau_rlar.rs b/src/inner/ppb/sau_rlar.rs
index ec94fec..1bbcd46 100644
--- a/src/inner/ppb/sau_rlar.rs
+++ b/src/inner/ppb/sau_rlar.rs
@@ -37,20 +37,17 @@ of the limit address for the selected SAU region"]
 impl W {
     #[doc = "Bit 0 - SAU region enable"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<SAU_RLAR_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Controls whether Non-secure state is permitted to execute an SG instruction from this region"]
     #[inline(always)]
-    #[must_use]
     pub fn nsc(&mut self) -> NSC_W<SAU_RLAR_SPEC> {
         NSC_W::new(self, 1)
     }
     #[doc = "Bits 5:31 - Holds bits \\[31:5\\]
 of the limit address for the selected SAU region"]
     #[inline(always)]
-    #[must_use]
     pub fn laddr(&mut self) -> LADDR_W<SAU_RLAR_SPEC> {
         LADDR_W::new(self, 5)
     }
diff --git a/src/inner/ppb/sau_rnr.rs b/src/inner/ppb/sau_rnr.rs
index 1e73e5e..66357cd 100644
--- a/src/inner/ppb/sau_rnr.rs
+++ b/src/inner/ppb/sau_rnr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"]
     #[inline(always)]
-    #[must_use]
     pub fn region(&mut self) -> REGION_W<SAU_RNR_SPEC> {
         REGION_W::new(self, 0)
     }
diff --git a/src/inner/ppb/scr.rs b/src/inner/ppb/scr.rs
index 6e64e2f..a5a3ddb 100644
--- a/src/inner/ppb/scr.rs
+++ b/src/inner/ppb/scr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."]
     #[inline(always)]
-    #[must_use]
     pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W<SCR_SPEC> {
         SLEEPONEXIT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."]
     #[inline(always)]
-    #[must_use]
     pub fn sleepdeep(&mut self) -> SLEEPDEEP_W<SCR_SPEC> {
         SLEEPDEEP_W::new(self, 2)
     }
     #[doc = "Bit 3 - 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only available to Secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn sleepdeeps(&mut self) -> SLEEPDEEPS_W<SCR_SPEC> {
         SLEEPDEEPS_W::new(self, 3)
     }
     #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."]
     #[inline(always)]
-    #[must_use]
     pub fn sevonpend(&mut self) -> SEVONPEND_W<SCR_SPEC> {
         SEVONPEND_W::new(self, 4)
     }
diff --git a/src/inner/ppb/sfar.rs b/src/inner/ppb/sfar.rs
index 9b38b45..01e09d8 100644
--- a/src/inner/ppb/sfar.rs
+++ b/src/inner/ppb/sfar.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<SFAR_SPEC> {
         ADDRESS_W::new(self, 0)
     }
diff --git a/src/inner/ppb/sfsr.rs b/src/inner/ppb/sfsr.rs
index 76b63b8..5910682 100644
--- a/src/inner/ppb/sfsr.rs
+++ b/src/inner/ppb/sfsr.rs
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bit 0 - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set"]
     #[inline(always)]
-    #[must_use]
     pub fn invep(&mut self) -> INVEP_W<SFSR_SPEC> {
         INVEP_W::new(self, 0)
     }
     #[doc = "Bit 1 - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation"]
     #[inline(always)]
-    #[must_use]
     pub fn invis(&mut self) -> INVIS_W<SFSR_SPEC> {
         INVIS_W::new(self, 1)
     }
     #[doc = "Bit 2 - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state"]
     #[inline(always)]
-    #[must_use]
     pub fn inver(&mut self) -> INVER_W<SFSR_SPEC> {
         INVER_W::new(self, 2)
     }
     #[doc = "Bit 3 - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR"]
     #[inline(always)]
-    #[must_use]
     pub fn auviol(&mut self) -> AUVIOL_W<SFSR_SPEC> {
         AUVIOL_W::new(self, 3)
     }
     #[doc = "Bit 4 - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory"]
     #[inline(always)]
-    #[must_use]
     pub fn invtran(&mut self) -> INVTRAN_W<SFSR_SPEC> {
         INVTRAN_W::new(self, 4)
     }
     #[doc = "Bit 5 - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state"]
     #[inline(always)]
-    #[must_use]
     pub fn lsperr(&mut self) -> LSPERR_W<SFSR_SPEC> {
         LSPERR_W::new(self, 5)
     }
     #[doc = "Bit 6 - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault"]
     #[inline(always)]
-    #[must_use]
     pub fn sfarvalid(&mut self) -> SFARVALID_W<SFSR_SPEC> {
         SFARVALID_W::new(self, 6)
     }
     #[doc = "Bit 7 - Sticky flag indicating that an error occurred during lazy state activation or deactivation"]
     #[inline(always)]
-    #[must_use]
     pub fn lserr(&mut self) -> LSERR_W<SFSR_SPEC> {
         LSERR_W::new(self, 7)
     }
diff --git a/src/inner/ppb/shcsr.rs b/src/inner/ppb/shcsr.rs
index 8a341c3..514f295 100644
--- a/src/inner/ppb/shcsr.rs
+++ b/src/inner/ppb/shcsr.rs
@@ -187,121 +187,101 @@ impl R {
 impl W {
     #[doc = "Bit 0 - `IAAMO the active state of the MemManage exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn memfaultact(&mut self) -> MEMFAULTACT_W<SHCSR_SPEC> {
         MEMFAULTACT_W::new(self, 0)
     }
     #[doc = "Bit 1 - `IAAMO the active state of the BusFault exception"]
     #[inline(always)]
-    #[must_use]
     pub fn busfaultact(&mut self) -> BUSFAULTACT_W<SHCSR_SPEC> {
         BUSFAULTACT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn hardfaultact(&mut self) -> HARDFAULTACT_W<SHCSR_SPEC> {
         HARDFAULTACT_W::new(self, 2)
     }
     #[doc = "Bit 3 - `IAAMO the active state of the UsageFault exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn usgfaultact(&mut self) -> USGFAULTACT_W<SHCSR_SPEC> {
         USGFAULTACT_W::new(self, 3)
     }
     #[doc = "Bit 4 - `IAAMO the active state of the SecureFault exception"]
     #[inline(always)]
-    #[must_use]
     pub fn securefaultact(&mut self) -> SECUREFAULTACT_W<SHCSR_SPEC> {
         SECUREFAULTACT_W::new(self, 4)
     }
     #[doc = "Bit 5 - `IAAMO the active state of the NMI exception"]
     #[inline(always)]
-    #[must_use]
     pub fn nmiact(&mut self) -> NMIACT_W<SHCSR_SPEC> {
         NMIACT_W::new(self, 5)
     }
     #[doc = "Bit 7 - `IAAMO the active state of the SVCall exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn svcallact(&mut self) -> SVCALLACT_W<SHCSR_SPEC> {
         SVCALLACT_W::new(self, 7)
     }
     #[doc = "Bit 8 - `IAAMO the active state of the DebugMonitor exception"]
     #[inline(always)]
-    #[must_use]
     pub fn monitoract(&mut self) -> MONITORACT_W<SHCSR_SPEC> {
         MONITORACT_W::new(self, 8)
     }
     #[doc = "Bit 10 - `IAAMO the active state of the PendSV exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn pendsvact(&mut self) -> PENDSVACT_W<SHCSR_SPEC> {
         PENDSVACT_W::new(self, 10)
     }
     #[doc = "Bit 11 - `IAAMO the active state of the SysTick exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn systickact(&mut self) -> SYSTICKACT_W<SHCSR_SPEC> {
         SYSTICKACT_W::new(self, 11)
     }
     #[doc = "Bit 12 - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn usgfaultpended(&mut self) -> USGFAULTPENDED_W<SHCSR_SPEC> {
         USGFAULTPENDED_W::new(self, 12)
     }
     #[doc = "Bit 13 - `IAAMO the pending state of the MemManage exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn memfaultpended(&mut self) -> MEMFAULTPENDED_W<SHCSR_SPEC> {
         MEMFAULTPENDED_W::new(self, 13)
     }
     #[doc = "Bit 14 - `IAAMO the pending state of the BusFault exception"]
     #[inline(always)]
-    #[must_use]
     pub fn busfaultpended(&mut self) -> BUSFAULTPENDED_W<SHCSR_SPEC> {
         BUSFAULTPENDED_W::new(self, 14)
     }
     #[doc = "Bit 15 - `IAAMO the pending state of the SVCall exception `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn svcallpended(&mut self) -> SVCALLPENDED_W<SHCSR_SPEC> {
         SVCALLPENDED_W::new(self, 15)
     }
     #[doc = "Bit 16 - `DW the MemManage exception is enabled `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn memfaultena(&mut self) -> MEMFAULTENA_W<SHCSR_SPEC> {
         MEMFAULTENA_W::new(self, 16)
     }
     #[doc = "Bit 17 - `DW the BusFault exception is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn busfaultena(&mut self) -> BUSFAULTENA_W<SHCSR_SPEC> {
         BUSFAULTENA_W::new(self, 17)
     }
     #[doc = "Bit 18 - `DW the UsageFault exception is enabled `FTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn usgfaultena(&mut self) -> USGFAULTENA_W<SHCSR_SPEC> {
         USGFAULTENA_W::new(self, 18)
     }
     #[doc = "Bit 19 - `DW the SecureFault exception is enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn securefaultena(&mut self) -> SECUREFAULTENA_W<SHCSR_SPEC> {
         SECUREFAULTENA_W::new(self, 19)
     }
     #[doc = "Bit 20 - `IAAMO the pending state of the SecureFault exception"]
     #[inline(always)]
-    #[must_use]
     pub fn securefaultpended(&mut self) -> SECUREFAULTPENDED_W<SHCSR_SPEC> {
         SECUREFAULTPENDED_W::new(self, 20)
     }
     #[doc = "Bit 21 - `IAAMO the pending state of the HardFault exception `CTTSSS"]
     #[inline(always)]
-    #[must_use]
     pub fn hardfaultpended(&mut self) -> HARDFAULTPENDED_W<SHCSR_SPEC> {
         HARDFAULTPENDED_W::new(self, 21)
     }
diff --git a/src/inner/ppb/shpr1.rs b/src/inner/ppb/shpr1.rs
index a6f9e08..6127ef7 100644
--- a/src/inner/ppb/shpr1.rs
+++ b/src/inner/ppb/shpr1.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 5:7 - Priority of system handler 4, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_4_3(&mut self) -> PRI_4_3_W<SHPR1_SPEC> {
         PRI_4_3_W::new(self, 5)
     }
     #[doc = "Bits 13:15 - Priority of system handler 5, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_5_3(&mut self) -> PRI_5_3_W<SHPR1_SPEC> {
         PRI_5_3_W::new(self, 13)
     }
     #[doc = "Bits 21:23 - Priority of system handler 6, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_6_3(&mut self) -> PRI_6_3_W<SHPR1_SPEC> {
         PRI_6_3_W::new(self, 21)
     }
     #[doc = "Bits 29:31 - Priority of system handler 7, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_7_3(&mut self) -> PRI_7_3_W<SHPR1_SPEC> {
         PRI_7_3_W::new(self, 29)
     }
diff --git a/src/inner/ppb/shpr2.rs b/src/inner/ppb/shpr2.rs
index 072149d..814541f 100644
--- a/src/inner/ppb/shpr2.rs
+++ b/src/inner/ppb/shpr2.rs
@@ -37,7 +37,6 @@ impl R {
 impl W {
     #[doc = "Bits 29:31 - Priority of system handler 11, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_11_3(&mut self) -> PRI_11_3_W<SHPR2_SPEC> {
         PRI_11_3_W::new(self, 29)
     }
diff --git a/src/inner/ppb/shpr3.rs b/src/inner/ppb/shpr3.rs
index 9f95c51..fc18b01 100644
--- a/src/inner/ppb/shpr3.rs
+++ b/src/inner/ppb/shpr3.rs
@@ -41,19 +41,16 @@ impl R {
 impl W {
     #[doc = "Bits 5:7 - Priority of system handler 12, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_12_3(&mut self) -> PRI_12_3_W<SHPR3_SPEC> {
         PRI_12_3_W::new(self, 5)
     }
     #[doc = "Bits 21:23 - Priority of system handler 14, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_14_3(&mut self) -> PRI_14_3_W<SHPR3_SPEC> {
         PRI_14_3_W::new(self, 21)
     }
     #[doc = "Bits 29:31 - Priority of system handler 15, SecureFault"]
     #[inline(always)]
-    #[must_use]
     pub fn pri_15_3(&mut self) -> PRI_15_3_W<SHPR3_SPEC> {
         PRI_15_3_W::new(self, 29)
     }
diff --git a/src/inner/ppb/stir.rs b/src/inner/ppb/stir.rs
index 5dc12cd..86ba9fe 100644
--- a/src/inner/ppb/stir.rs
+++ b/src/inner/ppb/stir.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:8 - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)"]
     #[inline(always)]
-    #[must_use]
     pub fn intid(&mut self) -> INTID_W<STIR_SPEC> {
         INTID_W::new(self, 0)
     }
diff --git a/src/inner/ppb/syst_csr.rs b/src/inner/ppb/syst_csr.rs
index 25fc79b..8ea411e 100644
--- a/src/inner/ppb/syst_csr.rs
+++ b/src/inner/ppb/syst_csr.rs
@@ -41,19 +41,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<SYST_CSR_SPEC> {
         ENABLE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."]
     #[inline(always)]
-    #[must_use]
     pub fn tickint(&mut self) -> TICKINT_W<SYST_CSR_SPEC> {
         TICKINT_W::new(self, 1)
     }
     #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."]
     #[inline(always)]
-    #[must_use]
     pub fn clksource(&mut self) -> CLKSOURCE_W<SYST_CSR_SPEC> {
         CLKSOURCE_W::new(self, 2)
     }
diff --git a/src/inner/ppb/syst_cvr.rs b/src/inner/ppb/syst_cvr.rs
index 43cdb56..2552afc 100644
--- a/src/inner/ppb/syst_cvr.rs
+++ b/src/inner/ppb/syst_cvr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."]
     #[inline(always)]
-    #[must_use]
     pub fn current(&mut self) -> CURRENT_W<SYST_CVR_SPEC> {
         CURRENT_W::new(self, 0)
     }
diff --git a/src/inner/ppb/syst_rvr.rs b/src/inner/ppb/syst_rvr.rs
index 70c34b0..26b9360 100644
--- a/src/inner/ppb/syst_rvr.rs
+++ b/src/inner/ppb/syst_rvr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0."]
     #[inline(always)]
-    #[must_use]
     pub fn reload(&mut self) -> RELOAD_W<SYST_RVR_SPEC> {
         RELOAD_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcccctlr.rs b/src/inner/ppb/trcccctlr.rs
index ab81549..17f92b9 100644
--- a/src/inner/ppb/trcccctlr.rs
+++ b/src/inner/ppb/trcccctlr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Instruction trace cycle count threshold"]
     #[inline(always)]
-    #[must_use]
     pub fn threshold(&mut self) -> THRESHOLD_W<TRCCCCTLR_SPEC> {
         THRESHOLD_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcclaimclr.rs b/src/inner/ppb/trcclaimclr.rs
index 0164683..168fccd 100644
--- a/src/inner/ppb/trcclaimclr.rs
+++ b/src/inner/ppb/trcclaimclr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn clr0(&mut self) -> CLR0_W<TRCCLAIMCLR_SPEC> {
         CLR0_W::new(self, 0)
     }
     #[doc = "Bit 1 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn clr1(&mut self) -> CLR1_W<TRCCLAIMCLR_SPEC> {
         CLR1_W::new(self, 1)
     }
     #[doc = "Bit 2 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn clr2(&mut self) -> CLR2_W<TRCCLAIMCLR_SPEC> {
         CLR2_W::new(self, 2)
     }
     #[doc = "Bit 3 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn clr3(&mut self) -> CLR3_W<TRCCLAIMCLR_SPEC> {
         CLR3_W::new(self, 3)
     }
diff --git a/src/inner/ppb/trcclaimset.rs b/src/inner/ppb/trcclaimset.rs
index 5020f84..ad695e4 100644
--- a/src/inner/ppb/trcclaimset.rs
+++ b/src/inner/ppb/trcclaimset.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn set0(&mut self) -> SET0_W<TRCCLAIMSET_SPEC> {
         SET0_W::new(self, 0)
     }
     #[doc = "Bit 1 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn set1(&mut self) -> SET1_W<TRCCLAIMSET_SPEC> {
         SET1_W::new(self, 1)
     }
     #[doc = "Bit 2 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn set2(&mut self) -> SET2_W<TRCCLAIMSET_SPEC> {
         SET2_W::new(self, 2)
     }
     #[doc = "Bit 3 - When a write to one of these bits occurs, with the value:"]
     #[inline(always)]
-    #[must_use]
     pub fn set3(&mut self) -> SET3_W<TRCCLAIMSET_SPEC> {
         SET3_W::new(self, 3)
     }
diff --git a/src/inner/ppb/trccntrldvr0.rs b/src/inner/ppb/trccntrldvr0.rs
index 85d1e91..ad27f95 100644
--- a/src/inner/ppb/trccntrldvr0.rs
+++ b/src/inner/ppb/trccntrldvr0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs"]
     #[inline(always)]
-    #[must_use]
     pub fn value(&mut self) -> VALUE_W<TRCCNTRLDVR0_SPEC> {
         VALUE_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcconfigr.rs b/src/inner/ppb/trcconfigr.rs
index 100a637..e279c66 100644
--- a/src/inner/ppb/trcconfigr.rs
+++ b/src/inner/ppb/trcconfigr.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 3 - Branch broadcast mode"]
     #[inline(always)]
-    #[must_use]
     pub fn bb(&mut self) -> BB_W<TRCCONFIGR_SPEC> {
         BB_W::new(self, 3)
     }
     #[doc = "Bit 4 - Cycle counting in instruction trace"]
     #[inline(always)]
-    #[must_use]
     pub fn cci(&mut self) -> CCI_W<TRCCONFIGR_SPEC> {
         CCI_W::new(self, 4)
     }
     #[doc = "Bits 5:10 - Conditional instruction tracing"]
     #[inline(always)]
-    #[must_use]
     pub fn cond(&mut self) -> COND_W<TRCCONFIGR_SPEC> {
         COND_W::new(self, 5)
     }
     #[doc = "Bit 11 - Global timestamp tracing"]
     #[inline(always)]
-    #[must_use]
     pub fn ts(&mut self) -> TS_W<TRCCONFIGR_SPEC> {
         TS_W::new(self, 11)
     }
     #[doc = "Bit 12 - Return stack enable"]
     #[inline(always)]
-    #[must_use]
     pub fn rs(&mut self) -> RS_W<TRCCONFIGR_SPEC> {
         RS_W::new(self, 12)
     }
diff --git a/src/inner/ppb/trcdevid.rs b/src/inner/ppb/trcdevid.rs
index f30f3d6..c90d267 100644
--- a/src/inner/ppb/trcdevid.rs
+++ b/src/inner/ppb/trcdevid.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn trcdevid(&mut self) -> TRCDEVID_W<TRCDEVID_SPEC> {
         TRCDEVID_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trceventctl0r.rs b/src/inner/ppb/trceventctl0r.rs
index 71fc3c3..80ddec8 100644
--- a/src/inner/ppb/trceventctl0r.rs
+++ b/src/inner/ppb/trceventctl0r.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:2 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn sel0(&mut self) -> SEL0_W<TRCEVENTCTL0R_SPEC> {
         SEL0_W::new(self, 0)
     }
     #[doc = "Bit 7 - Selects the resource type for event 0"]
     #[inline(always)]
-    #[must_use]
     pub fn type0(&mut self) -> TYPE0_W<TRCEVENTCTL0R_SPEC> {
         TYPE0_W::new(self, 7)
     }
     #[doc = "Bits 8:10 - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1\\[2:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn sel1(&mut self) -> SEL1_W<TRCEVENTCTL0R_SPEC> {
         SEL1_W::new(self, 8)
     }
     #[doc = "Bit 15 - Selects the resource type for event 1"]
     #[inline(always)]
-    #[must_use]
     pub fn type1(&mut self) -> TYPE1_W<TRCEVENTCTL0R_SPEC> {
         TYPE1_W::new(self, 15)
     }
diff --git a/src/inner/ppb/trceventctl1r.rs b/src/inner/ppb/trceventctl1r.rs
index f15bd4d..722e90d 100644
--- a/src/inner/ppb/trceventctl1r.rs
+++ b/src/inner/ppb/trceventctl1r.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"]
     #[inline(always)]
-    #[must_use]
     pub fn insten0(&mut self) -> INSTEN0_W<TRCEVENTCTL1R_SPEC> {
         INSTEN0_W::new(self, 0)
     }
     #[doc = "Bit 1 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"]
     #[inline(always)]
-    #[must_use]
     pub fn insten1(&mut self) -> INSTEN1_W<TRCEVENTCTL1R_SPEC> {
         INSTEN1_W::new(self, 1)
     }
     #[doc = "Bit 11 - ATB enabled"]
     #[inline(always)]
-    #[must_use]
     pub fn atb(&mut self) -> ATB_W<TRCEVENTCTL1R_SPEC> {
         ATB_W::new(self, 11)
     }
     #[doc = "Bit 12 - Low power state behavior override"]
     #[inline(always)]
-    #[must_use]
     pub fn lpoverride(&mut self) -> LPOVERRIDE_W<TRCEVENTCTL1R_SPEC> {
         LPOVERRIDE_W::new(self, 12)
     }
diff --git a/src/inner/ppb/trcidr6.rs b/src/inner/ppb/trcidr6.rs
index 4551c76..e865ae8 100644
--- a/src/inner/ppb/trcidr6.rs
+++ b/src/inner/ppb/trcidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn trcidr6(&mut self) -> TRCIDR6_W<TRCIDR6_SPEC> {
         TRCIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcidr7.rs b/src/inner/ppb/trcidr7.rs
index 3193e53..414edbf 100644
--- a/src/inner/ppb/trcidr7.rs
+++ b/src/inner/ppb/trcidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn trcidr7(&mut self) -> TRCIDR7_W<TRCIDR7_SPEC> {
         TRCIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcitatbidr.rs b/src/inner/ppb/trcitatbidr.rs
index 90d4d7c..c854f4a 100644
--- a/src/inner/ppb/trcitatbidr.rs
+++ b/src/inner/ppb/trcitatbidr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Trace ID"]
     #[inline(always)]
-    #[must_use]
     pub fn id(&mut self) -> ID_W<TRCITATBIDR_SPEC> {
         ID_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcitiatbinr.rs b/src/inner/ppb/trcitiatbinr.rs
index 8199a4d..56de4db 100644
--- a/src/inner/ppb/trcitiatbinr.rs
+++ b/src/inner/ppb/trcitiatbinr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Integration Mode instruction ATREADYM in"]
     #[inline(always)]
-    #[must_use]
     pub fn atreadym(&mut self) -> ATREADYM_W<TRCITIATBINR_SPEC> {
         ATREADYM_W::new(self, 0)
     }
     #[doc = "Bit 1 - Integration Mode instruction AFVALIDM in"]
     #[inline(always)]
-    #[must_use]
     pub fn afvalidm(&mut self) -> AFVALIDM_W<TRCITIATBINR_SPEC> {
         AFVALIDM_W::new(self, 1)
     }
diff --git a/src/inner/ppb/trcitiatboutr.rs b/src/inner/ppb/trcitiatboutr.rs
index 85a10fa..c6b1425 100644
--- a/src/inner/ppb/trcitiatboutr.rs
+++ b/src/inner/ppb/trcitiatboutr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Integration Mode instruction ATVALID out"]
     #[inline(always)]
-    #[must_use]
     pub fn atvalid(&mut self) -> ATVALID_W<TRCITIATBOUTR_SPEC> {
         ATVALID_W::new(self, 0)
     }
     #[doc = "Bit 1 - Integration Mode instruction AFREADY out"]
     #[inline(always)]
-    #[must_use]
     pub fn afready(&mut self) -> AFREADY_W<TRCITIATBOUTR_SPEC> {
         AFREADY_W::new(self, 1)
     }
diff --git a/src/inner/ppb/trcpdcr.rs b/src/inner/ppb/trcpdcr.rs
index 3dca530..b86ae59 100644
--- a/src/inner/ppb/trcpdcr.rs
+++ b/src/inner/ppb/trcpdcr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 3 - Powerup request bit:"]
     #[inline(always)]
-    #[must_use]
     pub fn pu(&mut self) -> PU_W<TRCPDCR_SPEC> {
         PU_W::new(self, 3)
     }
diff --git a/src/inner/ppb/trcpidr5.rs b/src/inner/ppb/trcpidr5.rs
index fc3766a..0d512b3 100644
--- a/src/inner/ppb/trcpidr5.rs
+++ b/src/inner/ppb/trcpidr5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn trcpidr5(&mut self) -> TRCPIDR5_W<TRCPIDR5_SPEC> {
         TRCPIDR5_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcpidr6.rs b/src/inner/ppb/trcpidr6.rs
index 0f30c68..aabb88a 100644
--- a/src/inner/ppb/trcpidr6.rs
+++ b/src/inner/ppb/trcpidr6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn trcpidr6(&mut self) -> TRCPIDR6_W<TRCPIDR6_SPEC> {
         TRCPIDR6_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcpidr7.rs b/src/inner/ppb/trcpidr7.rs
index 8025a4d..ae7660e 100644
--- a/src/inner/ppb/trcpidr7.rs
+++ b/src/inner/ppb/trcpidr7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn trcpidr7(&mut self) -> TRCPIDR7_W<TRCPIDR7_SPEC> {
         TRCPIDR7_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcprgctlr.rs b/src/inner/ppb/trcprgctlr.rs
index 3928146..2ec1060 100644
--- a/src/inner/ppb/trcprgctlr.rs
+++ b/src/inner/ppb/trcprgctlr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Trace Unit Enable"]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<TRCPRGCTLR_SPEC> {
         EN_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcrsctlr2.rs b/src/inner/ppb/trcrsctlr2.rs
index d7f5281..9531a6a 100644
--- a/src/inner/ppb/trcrsctlr2.rs
+++ b/src/inner/ppb/trcrsctlr2.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Selects one or more resources from the wanted group. One bit is provided per resource from the group"]
     #[inline(always)]
-    #[must_use]
     pub fn select(&mut self) -> SELECT_W<TRCRSCTLR2_SPEC> {
         SELECT_W::new(self, 0)
     }
     #[doc = "Bits 16:18 - Selects a group of resource"]
     #[inline(always)]
-    #[must_use]
     pub fn group(&mut self) -> GROUP_W<TRCRSCTLR2_SPEC> {
         GROUP_W::new(self, 16)
     }
     #[doc = "Bit 20 - Inverts the selected resources"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<TRCRSCTLR2_SPEC> {
         INV_W::new(self, 20)
     }
     #[doc = "Bit 21 - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"]
     #[inline(always)]
-    #[must_use]
     pub fn pairinv(&mut self) -> PAIRINV_W<TRCRSCTLR2_SPEC> {
         PAIRINV_W::new(self, 21)
     }
diff --git a/src/inner/ppb/trcrsctlr3.rs b/src/inner/ppb/trcrsctlr3.rs
index 29a7d10..1d510da 100644
--- a/src/inner/ppb/trcrsctlr3.rs
+++ b/src/inner/ppb/trcrsctlr3.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Selects one or more resources from the wanted group. One bit is provided per resource from the group"]
     #[inline(always)]
-    #[must_use]
     pub fn select(&mut self) -> SELECT_W<TRCRSCTLR3_SPEC> {
         SELECT_W::new(self, 0)
     }
     #[doc = "Bits 16:18 - Selects a group of resource"]
     #[inline(always)]
-    #[must_use]
     pub fn group(&mut self) -> GROUP_W<TRCRSCTLR3_SPEC> {
         GROUP_W::new(self, 16)
     }
     #[doc = "Bit 20 - Inverts the selected resources"]
     #[inline(always)]
-    #[must_use]
     pub fn inv(&mut self) -> INV_W<TRCRSCTLR3_SPEC> {
         INV_W::new(self, 20)
     }
     #[doc = "Bit 21 - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"]
     #[inline(always)]
-    #[must_use]
     pub fn pairinv(&mut self) -> PAIRINV_W<TRCRSCTLR3_SPEC> {
         PAIRINV_W::new(self, 21)
     }
diff --git a/src/inner/ppb/trcsscsr.rs b/src/inner/ppb/trcsscsr.rs
index ab45685..15a3751 100644
--- a/src/inner/ppb/trcsscsr.rs
+++ b/src/inner/ppb/trcsscsr.rs
@@ -44,7 +44,6 @@ impl R {
 impl W {
     #[doc = "Bit 31 - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched"]
     #[inline(always)]
-    #[must_use]
     pub fn status(&mut self) -> STATUS_W<TRCSSCSR_SPEC> {
         STATUS_W::new(self, 31)
     }
diff --git a/src/inner/ppb/trcsspcicr.rs b/src/inner/ppb/trcsspcicr.rs
index d73f252..85e00a1 100644
--- a/src/inner/ppb/trcsspcicr.rs
+++ b/src/inner/ppb/trcsspcicr.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 0:3 - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit\\[1\\]
 == 1 this selects PE comparator input 1 for Single-shot control"]
     #[inline(always)]
-    #[must_use]
     pub fn pc(&mut self) -> PC_W<TRCSSPCICR_SPEC> {
         PC_W::new(self, 0)
     }
diff --git a/src/inner/ppb/trcstallctlr.rs b/src/inner/ppb/trcstallctlr.rs
index 8f55cb2..791c348 100644
--- a/src/inner/ppb/trcstallctlr.rs
+++ b/src/inner/ppb/trcstallctlr.rs
@@ -32,13 +32,11 @@ impl R {
 impl W {
     #[doc = "Bits 2:3 - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow"]
     #[inline(always)]
-    #[must_use]
     pub fn level(&mut self) -> LEVEL_W<TRCSTALLCTLR_SPEC> {
         LEVEL_W::new(self, 2)
     }
     #[doc = "Bit 8 - Stall processor based on instruction trace buffer space"]
     #[inline(always)]
-    #[must_use]
     pub fn istall(&mut self) -> ISTALL_W<TRCSTALLCTLR_SPEC> {
         ISTALL_W::new(self, 8)
     }
diff --git a/src/inner/ppb/trctsctlr.rs b/src/inner/ppb/trctsctlr.rs
index 6704a32..25e7e3c 100644
--- a/src/inner/ppb/trctsctlr.rs
+++ b/src/inner/ppb/trctsctlr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn sel0(&mut self) -> SEL0_W<TRCTSCTLR_SPEC> {
         SEL0_W::new(self, 0)
     }
     #[doc = "Bit 7 - Selects the resource type for event 0"]
     #[inline(always)]
-    #[must_use]
     pub fn type0(&mut self) -> TYPE0_W<TRCTSCTLR_SPEC> {
         TYPE0_W::new(self, 7)
     }
diff --git a/src/inner/ppb/trcvictlr.rs b/src/inner/ppb/trcvictlr.rs
index 8cabe63..7e31c30 100644
--- a/src/inner/ppb/trcvictlr.rs
+++ b/src/inner/ppb/trcvictlr.rs
@@ -70,43 +70,36 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"]
     #[inline(always)]
-    #[must_use]
     pub fn sel0(&mut self) -> SEL0_W<TRCVICTLR_SPEC> {
         SEL0_W::new(self, 0)
     }
     #[doc = "Bit 7 - Selects the resource type for event 0"]
     #[inline(always)]
-    #[must_use]
     pub fn type0(&mut self) -> TYPE0_W<TRCVICTLR_SPEC> {
         TYPE0_W::new(self, 7)
     }
     #[doc = "Bit 9 - Indicates the current status of the start/stop logic"]
     #[inline(always)]
-    #[must_use]
     pub fn ssstatus(&mut self) -> SSSTATUS_W<TRCVICTLR_SPEC> {
         SSSTATUS_W::new(self, 9)
     }
     #[doc = "Bit 10 - Selects whether a reset exception must always be traced"]
     #[inline(always)]
-    #[must_use]
     pub fn trcreset(&mut self) -> TRCRESET_W<TRCVICTLR_SPEC> {
         TRCRESET_W::new(self, 10)
     }
     #[doc = "Bit 11 - Selects whether a system error exception must always be traced"]
     #[inline(always)]
-    #[must_use]
     pub fn trcerr(&mut self) -> TRCERR_W<TRCVICTLR_SPEC> {
         TRCERR_W::new(self, 11)
     }
     #[doc = "Bit 16 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"]
     #[inline(always)]
-    #[must_use]
     pub fn exlevel_s0(&mut self) -> EXLEVEL_S0_W<TRCVICTLR_SPEC> {
         EXLEVEL_S0_W::new(self, 16)
     }
     #[doc = "Bit 19 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"]
     #[inline(always)]
-    #[must_use]
     pub fn exlevel_s3(&mut self) -> EXLEVEL_S3_W<TRCVICTLR_SPEC> {
         EXLEVEL_S3_W::new(self, 19)
     }
diff --git a/src/inner/ppb/vtor.rs b/src/inner/ppb/vtor.rs
index df7b633..c7bf275 100644
--- a/src/inner/ppb/vtor.rs
+++ b/src/inner/ppb/vtor.rs
@@ -20,7 +20,6 @@ impl W {
     #[doc = "Bits 7:31 - Vector table base offset field. It contains bits\\[31:7\\]
 of the offset of the table base from the bottom of the memory map."]
     #[inline(always)]
-    #[must_use]
     pub fn tbloff(&mut self) -> TBLOFF_W<VTOR_SPEC> {
         TBLOFF_W::new(self, 7)
     }
diff --git a/src/inner/psm/frce_off.rs b/src/inner/psm/frce_off.rs
index 8255dd1..0b5523d 100644
--- a/src/inner/psm/frce_off.rs
+++ b/src/inner/psm/frce_off.rs
@@ -232,151 +232,126 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn proc_cold(&mut self) -> PROC_COLD_W<FRCE_OFF_SPEC> {
         PROC_COLD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn otp(&mut self) -> OTP_W<FRCE_OFF_SPEC> {
         OTP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rosc(&mut self) -> ROSC_W<FRCE_OFF_SPEC> {
         ROSC_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn xosc(&mut self) -> XOSC_W<FRCE_OFF_SPEC> {
         XOSC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn resets(&mut self) -> RESETS_W<FRCE_OFF_SPEC> {
         RESETS_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clocks(&mut self) -> CLOCKS_W<FRCE_OFF_SPEC> {
         CLOCKS_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn psm_ready(&mut self) -> PSM_READY_W<FRCE_OFF_SPEC> {
         PSM_READY_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn busfabric(&mut self) -> BUSFABRIC_W<FRCE_OFF_SPEC> {
         BUSFABRIC_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn rom(&mut self) -> ROM_W<FRCE_OFF_SPEC> {
         ROM_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bootram(&mut self) -> BOOTRAM_W<FRCE_OFF_SPEC> {
         BOOTRAM_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sram0(&mut self) -> SRAM0_W<FRCE_OFF_SPEC> {
         SRAM0_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn sram1(&mut self) -> SRAM1_W<FRCE_OFF_SPEC> {
         SRAM1_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sram2(&mut self) -> SRAM2_W<FRCE_OFF_SPEC> {
         SRAM2_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn sram3(&mut self) -> SRAM3_W<FRCE_OFF_SPEC> {
         SRAM3_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn sram4(&mut self) -> SRAM4_W<FRCE_OFF_SPEC> {
         SRAM4_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram5(&mut self) -> SRAM5_W<FRCE_OFF_SPEC> {
         SRAM5_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sram6(&mut self) -> SRAM6_W<FRCE_OFF_SPEC> {
         SRAM6_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sram7(&mut self) -> SRAM7_W<FRCE_OFF_SPEC> {
         SRAM7_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sram8(&mut self) -> SRAM8_W<FRCE_OFF_SPEC> {
         SRAM8_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn sram9(&mut self) -> SRAM9_W<FRCE_OFF_SPEC> {
         SRAM9_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn xip(&mut self) -> XIP_W<FRCE_OFF_SPEC> {
         XIP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn sio(&mut self) -> SIO_W<FRCE_OFF_SPEC> {
         SIO_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn accessctrl(&mut self) -> ACCESSCTRL_W<FRCE_OFF_SPEC> {
         ACCESSCTRL_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn proc0(&mut self) -> PROC0_W<FRCE_OFF_SPEC> {
         PROC0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn proc1(&mut self) -> PROC1_W<FRCE_OFF_SPEC> {
         PROC1_W::new(self, 24)
     }
diff --git a/src/inner/psm/frce_on.rs b/src/inner/psm/frce_on.rs
index 7b6e53e..2f92378 100644
--- a/src/inner/psm/frce_on.rs
+++ b/src/inner/psm/frce_on.rs
@@ -232,151 +232,126 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn proc_cold(&mut self) -> PROC_COLD_W<FRCE_ON_SPEC> {
         PROC_COLD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn otp(&mut self) -> OTP_W<FRCE_ON_SPEC> {
         OTP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rosc(&mut self) -> ROSC_W<FRCE_ON_SPEC> {
         ROSC_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn xosc(&mut self) -> XOSC_W<FRCE_ON_SPEC> {
         XOSC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn resets(&mut self) -> RESETS_W<FRCE_ON_SPEC> {
         RESETS_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clocks(&mut self) -> CLOCKS_W<FRCE_ON_SPEC> {
         CLOCKS_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn psm_ready(&mut self) -> PSM_READY_W<FRCE_ON_SPEC> {
         PSM_READY_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn busfabric(&mut self) -> BUSFABRIC_W<FRCE_ON_SPEC> {
         BUSFABRIC_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn rom(&mut self) -> ROM_W<FRCE_ON_SPEC> {
         ROM_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bootram(&mut self) -> BOOTRAM_W<FRCE_ON_SPEC> {
         BOOTRAM_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sram0(&mut self) -> SRAM0_W<FRCE_ON_SPEC> {
         SRAM0_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn sram1(&mut self) -> SRAM1_W<FRCE_ON_SPEC> {
         SRAM1_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sram2(&mut self) -> SRAM2_W<FRCE_ON_SPEC> {
         SRAM2_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn sram3(&mut self) -> SRAM3_W<FRCE_ON_SPEC> {
         SRAM3_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn sram4(&mut self) -> SRAM4_W<FRCE_ON_SPEC> {
         SRAM4_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram5(&mut self) -> SRAM5_W<FRCE_ON_SPEC> {
         SRAM5_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sram6(&mut self) -> SRAM6_W<FRCE_ON_SPEC> {
         SRAM6_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sram7(&mut self) -> SRAM7_W<FRCE_ON_SPEC> {
         SRAM7_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sram8(&mut self) -> SRAM8_W<FRCE_ON_SPEC> {
         SRAM8_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn sram9(&mut self) -> SRAM9_W<FRCE_ON_SPEC> {
         SRAM9_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn xip(&mut self) -> XIP_W<FRCE_ON_SPEC> {
         XIP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn sio(&mut self) -> SIO_W<FRCE_ON_SPEC> {
         SIO_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn accessctrl(&mut self) -> ACCESSCTRL_W<FRCE_ON_SPEC> {
         ACCESSCTRL_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn proc0(&mut self) -> PROC0_W<FRCE_ON_SPEC> {
         PROC0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn proc1(&mut self) -> PROC1_W<FRCE_ON_SPEC> {
         PROC1_W::new(self, 24)
     }
diff --git a/src/inner/psm/wdsel.rs b/src/inner/psm/wdsel.rs
index 0f62463..972e3ad 100644
--- a/src/inner/psm/wdsel.rs
+++ b/src/inner/psm/wdsel.rs
@@ -232,151 +232,126 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn proc_cold(&mut self) -> PROC_COLD_W<WDSEL_SPEC> {
         PROC_COLD_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn otp(&mut self) -> OTP_W<WDSEL_SPEC> {
         OTP_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn rosc(&mut self) -> ROSC_W<WDSEL_SPEC> {
         ROSC_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn xosc(&mut self) -> XOSC_W<WDSEL_SPEC> {
         XOSC_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn resets(&mut self) -> RESETS_W<WDSEL_SPEC> {
         RESETS_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn clocks(&mut self) -> CLOCKS_W<WDSEL_SPEC> {
         CLOCKS_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn psm_ready(&mut self) -> PSM_READY_W<WDSEL_SPEC> {
         PSM_READY_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn busfabric(&mut self) -> BUSFABRIC_W<WDSEL_SPEC> {
         BUSFABRIC_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn rom(&mut self) -> ROM_W<WDSEL_SPEC> {
         ROM_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn bootram(&mut self) -> BOOTRAM_W<WDSEL_SPEC> {
         BOOTRAM_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn sram0(&mut self) -> SRAM0_W<WDSEL_SPEC> {
         SRAM0_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn sram1(&mut self) -> SRAM1_W<WDSEL_SPEC> {
         SRAM1_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn sram2(&mut self) -> SRAM2_W<WDSEL_SPEC> {
         SRAM2_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn sram3(&mut self) -> SRAM3_W<WDSEL_SPEC> {
         SRAM3_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn sram4(&mut self) -> SRAM4_W<WDSEL_SPEC> {
         SRAM4_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn sram5(&mut self) -> SRAM5_W<WDSEL_SPEC> {
         SRAM5_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn sram6(&mut self) -> SRAM6_W<WDSEL_SPEC> {
         SRAM6_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sram7(&mut self) -> SRAM7_W<WDSEL_SPEC> {
         SRAM7_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn sram8(&mut self) -> SRAM8_W<WDSEL_SPEC> {
         SRAM8_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn sram9(&mut self) -> SRAM9_W<WDSEL_SPEC> {
         SRAM9_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn xip(&mut self) -> XIP_W<WDSEL_SPEC> {
         XIP_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn sio(&mut self) -> SIO_W<WDSEL_SPEC> {
         SIO_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn accessctrl(&mut self) -> ACCESSCTRL_W<WDSEL_SPEC> {
         ACCESSCTRL_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn proc0(&mut self) -> PROC0_W<WDSEL_SPEC> {
         PROC0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn proc1(&mut self) -> PROC1_W<WDSEL_SPEC> {
         PROC1_W::new(self, 24)
     }
diff --git a/src/inner/pwm.rs b/src/inner/pwm.rs
index 45a9a25..94de08b 100644
--- a/src/inner/pwm.rs
+++ b/src/inner/pwm.rs
@@ -43,7 +43,7 @@ impl RegisterBlock {
     pub const fn irq0_intf(&self) -> &IRQ0_INTF {
         &self.irq0_intf
     }
-    #[doc = "0x100 - Interrupt status after masking &amp; forcing for irq0"]
+    #[doc = "0x100 - Interrupt status after masking & forcing for irq0"]
     #[inline(always)]
     pub const fn irq0_ints(&self) -> &IRQ0_INTS {
         &self.irq0_ints
@@ -58,7 +58,7 @@ impl RegisterBlock {
     pub const fn irq1_intf(&self) -> &IRQ1_INTF {
         &self.irq1_intf
     }
-    #[doc = "0x10c - Interrupt status after masking &amp; forcing for irq1"]
+    #[doc = "0x10c - Interrupt status after masking & forcing for irq1"]
     #[inline(always)]
     pub const fn irq1_ints(&self) -> &IRQ1_INTS {
         &self.irq1_ints
@@ -105,14 +105,14 @@ module"]
 pub type IRQ0_INTF = crate::Reg<irq0_intf::IRQ0_INTF_SPEC>;
 #[doc = "Interrupt Force for irq0"]
 pub mod irq0_intf;
-#[doc = "IRQ0_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for irq0  
+#[doc = "IRQ0_INTS (rw) register accessor: Interrupt status after masking & forcing for irq0  
 
 You can [`read`](crate::Reg::read) this register and get [`irq0_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq0_ints`]
 module"]
 pub type IRQ0_INTS = crate::Reg<irq0_ints::IRQ0_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for irq0"]
+#[doc = "Interrupt status after masking & forcing for irq0"]
 pub mod irq0_ints;
 #[doc = "IRQ1_INTE (rw) register accessor: Interrupt Enable for irq1  
 
@@ -132,12 +132,12 @@ module"]
 pub type IRQ1_INTF = crate::Reg<irq1_intf::IRQ1_INTF_SPEC>;
 #[doc = "Interrupt Force for irq1"]
 pub mod irq1_intf;
-#[doc = "IRQ1_INTS (rw) register accessor: Interrupt status after masking &amp; forcing for irq1  
+#[doc = "IRQ1_INTS (rw) register accessor: Interrupt status after masking & forcing for irq1  
 
 You can [`read`](crate::Reg::read) this register and get [`irq1_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@irq1_ints`]
 module"]
 pub type IRQ1_INTS = crate::Reg<irq1_ints::IRQ1_INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing for irq1"]
+#[doc = "Interrupt status after masking & forcing for irq1"]
 pub mod irq1_ints;
diff --git a/src/inner/pwm/ch/cc.rs b/src/inner/pwm/ch/cc.rs
index 9239b42..603285f 100644
--- a/src/inner/pwm/ch/cc.rs
+++ b/src/inner/pwm/ch/cc.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn a(&mut self) -> A_W<CC_SPEC> {
         A_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn b(&mut self) -> B_W<CC_SPEC> {
         B_W::new(self, 16)
     }
diff --git a/src/inner/pwm/ch/csr.rs b/src/inner/pwm/ch/csr.rs
index 65ef37d..48fadc9 100644
--- a/src/inner/pwm/ch/csr.rs
+++ b/src/inner/pwm/ch/csr.rs
@@ -140,43 +140,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable the PWM channel."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<CSR_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge"]
     #[inline(always)]
-    #[must_use]
     pub fn ph_correct(&mut self) -> PH_CORRECT_W<CSR_SPEC> {
         PH_CORRECT_W::new(self, 1)
     }
     #[doc = "Bit 2 - Invert output A"]
     #[inline(always)]
-    #[must_use]
     pub fn a_inv(&mut self) -> A_INV_W<CSR_SPEC> {
         A_INV_W::new(self, 2)
     }
     #[doc = "Bit 3 - Invert output B"]
     #[inline(always)]
-    #[must_use]
     pub fn b_inv(&mut self) -> B_INV_W<CSR_SPEC> {
         B_INV_W::new(self, 3)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn divmode(&mut self) -> DIVMODE_W<CSR_SPEC> {
         DIVMODE_W::new(self, 4)
     }
     #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."]
     #[inline(always)]
-    #[must_use]
     pub fn ph_ret(&mut self) -> PH_RET_W<CSR_SPEC> {
         PH_RET_W::new(self, 6)
     }
     #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"]
     #[inline(always)]
-    #[must_use]
     pub fn ph_adv(&mut self) -> PH_ADV_W<CSR_SPEC> {
         PH_ADV_W::new(self, 7)
     }
diff --git a/src/inner/pwm/ch/ctr.rs b/src/inner/pwm/ch/ctr.rs
index a470fac..ff691d9 100644
--- a/src/inner/pwm/ch/ctr.rs
+++ b/src/inner/pwm/ch/ctr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn ctr(&mut self) -> CTR_W<CTR_SPEC> {
         CTR_W::new(self, 0)
     }
diff --git a/src/inner/pwm/ch/div.rs b/src/inner/pwm/ch/div.rs
index 27ec8e0..388f4b1 100644
--- a/src/inner/pwm/ch/div.rs
+++ b/src/inner/pwm/ch/div.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn frac(&mut self) -> FRAC_W<DIV_SPEC> {
         FRAC_W::new(self, 0)
     }
     #[doc = "Bits 4:11"]
     #[inline(always)]
-    #[must_use]
     pub fn int(&mut self) -> INT_W<DIV_SPEC> {
         INT_W::new(self, 4)
     }
diff --git a/src/inner/pwm/ch/top.rs b/src/inner/pwm/ch/top.rs
index 7cede61..34572fb 100644
--- a/src/inner/pwm/ch/top.rs
+++ b/src/inner/pwm/ch/top.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn top(&mut self) -> TOP_W<TOP_SPEC> {
         TOP_W::new(self, 0)
     }
diff --git a/src/inner/pwm/en.rs b/src/inner/pwm/en.rs
index a05053d..5090462 100644
--- a/src/inner/pwm/en.rs
+++ b/src/inner/pwm/en.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<EN_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<EN_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<EN_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<EN_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH4_W<EN_SPEC> {
         CH4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH5_W<EN_SPEC> {
         CH5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH6_W<EN_SPEC> {
         CH6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH7_W<EN_SPEC> {
         CH7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8(&mut self) -> CH8_W<EN_SPEC> {
         CH8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9(&mut self) -> CH9_W<EN_SPEC> {
         CH9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10(&mut self) -> CH10_W<EN_SPEC> {
         CH10_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11(&mut self) -> CH11_W<EN_SPEC> {
         CH11_W::new(self, 11)
     }
diff --git a/src/inner/pwm/intr.rs b/src/inner/pwm/intr.rs
index 3e3575f..aac2e9f 100644
--- a/src/inner/pwm/intr.rs
+++ b/src/inner/pwm/intr.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<INTR_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<INTR_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<INTR_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<INTR_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH4_W<INTR_SPEC> {
         CH4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH5_W<INTR_SPEC> {
         CH5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH6_W<INTR_SPEC> {
         CH6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH7_W<INTR_SPEC> {
         CH7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8(&mut self) -> CH8_W<INTR_SPEC> {
         CH8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9(&mut self) -> CH9_W<INTR_SPEC> {
         CH9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10(&mut self) -> CH10_W<INTR_SPEC> {
         CH10_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11(&mut self) -> CH11_W<INTR_SPEC> {
         CH11_W::new(self, 11)
     }
diff --git a/src/inner/pwm/irq0_inte.rs b/src/inner/pwm/irq0_inte.rs
index 2d13b71..edf0c96 100644
--- a/src/inner/pwm/irq0_inte.rs
+++ b/src/inner/pwm/irq0_inte.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<IRQ0_INTE_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<IRQ0_INTE_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<IRQ0_INTE_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<IRQ0_INTE_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH4_W<IRQ0_INTE_SPEC> {
         CH4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH5_W<IRQ0_INTE_SPEC> {
         CH5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH6_W<IRQ0_INTE_SPEC> {
         CH6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH7_W<IRQ0_INTE_SPEC> {
         CH7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8(&mut self) -> CH8_W<IRQ0_INTE_SPEC> {
         CH8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9(&mut self) -> CH9_W<IRQ0_INTE_SPEC> {
         CH9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10(&mut self) -> CH10_W<IRQ0_INTE_SPEC> {
         CH10_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11(&mut self) -> CH11_W<IRQ0_INTE_SPEC> {
         CH11_W::new(self, 11)
     }
diff --git a/src/inner/pwm/irq0_intf.rs b/src/inner/pwm/irq0_intf.rs
index 7cb85a2..77a7280 100644
--- a/src/inner/pwm/irq0_intf.rs
+++ b/src/inner/pwm/irq0_intf.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<IRQ0_INTF_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<IRQ0_INTF_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<IRQ0_INTF_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<IRQ0_INTF_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH4_W<IRQ0_INTF_SPEC> {
         CH4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH5_W<IRQ0_INTF_SPEC> {
         CH5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH6_W<IRQ0_INTF_SPEC> {
         CH6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH7_W<IRQ0_INTF_SPEC> {
         CH7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8(&mut self) -> CH8_W<IRQ0_INTF_SPEC> {
         CH8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9(&mut self) -> CH9_W<IRQ0_INTF_SPEC> {
         CH9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10(&mut self) -> CH10_W<IRQ0_INTF_SPEC> {
         CH10_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11(&mut self) -> CH11_W<IRQ0_INTF_SPEC> {
         CH11_W::new(self, 11)
     }
diff --git a/src/inner/pwm/irq0_ints.rs b/src/inner/pwm/irq0_ints.rs
index 638c77a..5332ec1 100644
--- a/src/inner/pwm/irq0_ints.rs
+++ b/src/inner/pwm/irq0_ints.rs
@@ -89,7 +89,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for irq0  
+#[doc = "Interrupt status after masking & forcing for irq0  
 
 You can [`read`](crate::Reg::read) this register and get [`irq0_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ0_INTS_SPEC;
diff --git a/src/inner/pwm/irq1_inte.rs b/src/inner/pwm/irq1_inte.rs
index df88c57..2dbff1f 100644
--- a/src/inner/pwm/irq1_inte.rs
+++ b/src/inner/pwm/irq1_inte.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<IRQ1_INTE_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<IRQ1_INTE_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<IRQ1_INTE_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<IRQ1_INTE_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH4_W<IRQ1_INTE_SPEC> {
         CH4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH5_W<IRQ1_INTE_SPEC> {
         CH5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH6_W<IRQ1_INTE_SPEC> {
         CH6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH7_W<IRQ1_INTE_SPEC> {
         CH7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8(&mut self) -> CH8_W<IRQ1_INTE_SPEC> {
         CH8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9(&mut self) -> CH9_W<IRQ1_INTE_SPEC> {
         CH9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10(&mut self) -> CH10_W<IRQ1_INTE_SPEC> {
         CH10_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11(&mut self) -> CH11_W<IRQ1_INTE_SPEC> {
         CH11_W::new(self, 11)
     }
diff --git a/src/inner/pwm/irq1_intf.rs b/src/inner/pwm/irq1_intf.rs
index df9a479..a65a28d 100644
--- a/src/inner/pwm/irq1_intf.rs
+++ b/src/inner/pwm/irq1_intf.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ch0(&mut self) -> CH0_W<IRQ1_INTF_SPEC> {
         CH0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ch1(&mut self) -> CH1_W<IRQ1_INTF_SPEC> {
         CH1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ch2(&mut self) -> CH2_W<IRQ1_INTF_SPEC> {
         CH2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ch3(&mut self) -> CH3_W<IRQ1_INTF_SPEC> {
         CH3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ch4(&mut self) -> CH4_W<IRQ1_INTF_SPEC> {
         CH4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ch5(&mut self) -> CH5_W<IRQ1_INTF_SPEC> {
         CH5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ch6(&mut self) -> CH6_W<IRQ1_INTF_SPEC> {
         CH6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ch7(&mut self) -> CH7_W<IRQ1_INTF_SPEC> {
         CH7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ch8(&mut self) -> CH8_W<IRQ1_INTF_SPEC> {
         CH8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ch9(&mut self) -> CH9_W<IRQ1_INTF_SPEC> {
         CH9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ch10(&mut self) -> CH10_W<IRQ1_INTF_SPEC> {
         CH10_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ch11(&mut self) -> CH11_W<IRQ1_INTF_SPEC> {
         CH11_W::new(self, 11)
     }
diff --git a/src/inner/pwm/irq1_ints.rs b/src/inner/pwm/irq1_ints.rs
index 82ae7fc..9f82b21 100644
--- a/src/inner/pwm/irq1_ints.rs
+++ b/src/inner/pwm/irq1_ints.rs
@@ -89,7 +89,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing for irq1  
+#[doc = "Interrupt status after masking & forcing for irq1  
 
 You can [`read`](crate::Reg::read) this register and get [`irq1_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IRQ1_INTS_SPEC;
diff --git a/src/inner/qmi/atrans0.rs b/src/inner/qmi/atrans0.rs
index 66591d1..5af8225 100644
--- a/src/inner/qmi/atrans0.rs
+++ b/src/inner/qmi/atrans0.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS0_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS0_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans1.rs b/src/inner/qmi/atrans1.rs
index 3f1fecb..022b6c1 100644
--- a/src/inner/qmi/atrans1.rs
+++ b/src/inner/qmi/atrans1.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS1_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS1_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans2.rs b/src/inner/qmi/atrans2.rs
index 37034b3..1bef1de 100644
--- a/src/inner/qmi/atrans2.rs
+++ b/src/inner/qmi/atrans2.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS2_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS2_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans3.rs b/src/inner/qmi/atrans3.rs
index bc74f71..bc6e0cc 100644
--- a/src/inner/qmi/atrans3.rs
+++ b/src/inner/qmi/atrans3.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS3_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS3_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans4.rs b/src/inner/qmi/atrans4.rs
index 1c953ce..3a13aac 100644
--- a/src/inner/qmi/atrans4.rs
+++ b/src/inner/qmi/atrans4.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS4_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS4_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans5.rs b/src/inner/qmi/atrans5.rs
index d0ef89a..e6e5278 100644
--- a/src/inner/qmi/atrans5.rs
+++ b/src/inner/qmi/atrans5.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS5_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS5_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans6.rs b/src/inner/qmi/atrans6.rs
index f071b04..192858b 100644
--- a/src/inner/qmi/atrans6.rs
+++ b/src/inner/qmi/atrans6.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS6_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS6_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/atrans7.rs b/src/inner/qmi/atrans7.rs
index f10b607..ad1743d 100644
--- a/src/inner/qmi/atrans7.rs
+++ b/src/inner/qmi/atrans7.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."]
     #[inline(always)]
-    #[must_use]
     pub fn base(&mut self) -> BASE_W<ATRANS7_SPEC> {
         BASE_W::new(self, 0)
     }
     #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."]
     #[inline(always)]
-    #[must_use]
     pub fn size(&mut self) -> SIZE_W<ATRANS7_SPEC> {
         SIZE_W::new(self, 16)
     }
diff --git a/src/inner/qmi/direct_csr.rs b/src/inner/qmi/direct_csr.rs
index f2993d6..c8b51db 100644
--- a/src/inner/qmi/direct_csr.rs
+++ b/src/inner/qmi/direct_csr.rs
@@ -119,43 +119,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<DIRECT_CSR_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 2 - When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."]
     #[inline(always)]
-    #[must_use]
     pub fn assert_cs0n(&mut self) -> ASSERT_CS0N_W<DIRECT_CSR_SPEC> {
         ASSERT_CS0N_W::new(self, 2)
     }
     #[doc = "Bit 3 - When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."]
     #[inline(always)]
-    #[must_use]
     pub fn assert_cs1n(&mut self) -> ASSERT_CS1N_W<DIRECT_CSR_SPEC> {
         ASSERT_CS1N_W::new(self, 3)
     }
     #[doc = "Bit 6 - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."]
     #[inline(always)]
-    #[must_use]
     pub fn auto_cs0n(&mut self) -> AUTO_CS0N_W<DIRECT_CSR_SPEC> {
         AUTO_CS0N_W::new(self, 6)
     }
     #[doc = "Bit 7 - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."]
     #[inline(always)]
-    #[must_use]
     pub fn auto_cs1n(&mut self) -> AUTO_CS1N_W<DIRECT_CSR_SPEC> {
         AUTO_CS1N_W::new(self, 7)
     }
     #[doc = "Bits 22:29 - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<DIRECT_CSR_SPEC> {
         CLKDIV_W::new(self, 22)
     }
     #[doc = "Bits 30:31 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"]
     #[inline(always)]
-    #[must_use]
     pub fn rxdelay(&mut self) -> RXDELAY_W<DIRECT_CSR_SPEC> {
         RXDELAY_W::new(self, 30)
     }
diff --git a/src/inner/qmi/direct_tx.rs b/src/inner/qmi/direct_tx.rs
index b2cc38b..e4f3dbc 100644
--- a/src/inner/qmi/direct_tx.rs
+++ b/src/inner/qmi/direct_tx.rs
@@ -59,31 +59,26 @@ pub type NOPUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bits 0:15 - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<DIRECT_TX_SPEC> {
         DATA_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."]
     #[inline(always)]
-    #[must_use]
     pub fn iwidth(&mut self) -> IWIDTH_W<DIRECT_TX_SPEC> {
         IWIDTH_W::new(self, 16)
     }
     #[doc = "Bit 18 - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."]
     #[inline(always)]
-    #[must_use]
     pub fn dwidth(&mut self) -> DWIDTH_W<DIRECT_TX_SPEC> {
         DWIDTH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn oe(&mut self) -> OE_W<DIRECT_TX_SPEC> {
         OE_W::new(self, 19)
     }
     #[doc = "Bit 20 - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn nopush(&mut self) -> NOPUSH_W<DIRECT_TX_SPEC> {
         NOPUSH_W::new(self, 20)
     }
diff --git a/src/inner/qmi/m0_rcmd.rs b/src/inner/qmi/m0_rcmd.rs
index de8823a..32fb155 100644
--- a/src/inner/qmi/m0_rcmd.rs
+++ b/src/inner/qmi/m0_rcmd.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn prefix(&mut self) -> PREFIX_W<M0_RCMD_SPEC> {
         PREFIX_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix(&mut self) -> SUFFIX_W<M0_RCMD_SPEC> {
         SUFFIX_W::new(self, 8)
     }
diff --git a/src/inner/qmi/m0_rfmt.rs b/src/inner/qmi/m0_rfmt.rs
index 0fa0bcb..bf4ff53 100644
--- a/src/inner/qmi/m0_rfmt.rs
+++ b/src/inner/qmi/m0_rfmt.rs
@@ -688,55 +688,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W<M0_RFMT_SPEC> {
         PREFIX_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_width(&mut self) -> ADDR_WIDTH_W<M0_RFMT_SPEC> {
         ADDR_WIDTH_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W<M0_RFMT_SPEC> {
         SUFFIX_WIDTH_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W<M0_RFMT_SPEC> {
         DUMMY_WIDTH_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - The width used for the data transfer"]
     #[inline(always)]
-    #[must_use]
     pub fn data_width(&mut self) -> DATA_WIDTH_W<M0_RFMT_SPEC> {
         DATA_WIDTH_W::new(self, 8)
     }
     #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_len(&mut self) -> PREFIX_LEN_W<M0_RFMT_SPEC> {
         PREFIX_LEN_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_len(&mut self) -> SUFFIX_LEN_W<M0_RFMT_SPEC> {
         SUFFIX_LEN_W::new(self, 14)
     }
     #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_len(&mut self) -> DUMMY_LEN_W<M0_RFMT_SPEC> {
         DUMMY_LEN_W::new(self, 16)
     }
     #[doc = "Bit 28 - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr(&mut self) -> DTR_W<M0_RFMT_SPEC> {
         DTR_W::new(self, 28)
     }
diff --git a/src/inner/qmi/m0_timing.rs b/src/inner/qmi/m0_timing.rs
index d51fbb2..8f7283e 100644
--- a/src/inner/qmi/m0_timing.rs
+++ b/src/inner/qmi/m0_timing.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<M0_TIMING_SPEC> {
         CLKDIV_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."]
     #[inline(always)]
-    #[must_use]
     pub fn rxdelay(&mut self) -> RXDELAY_W<M0_TIMING_SPEC> {
         RXDELAY_W::new(self, 8)
     }
     #[doc = "Bits 12:16 - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."]
     #[inline(always)]
-    #[must_use]
     pub fn min_deselect(&mut self) -> MIN_DESELECT_W<M0_TIMING_SPEC> {
         MIN_DESELECT_W::new(self, 12)
     }
     #[doc = "Bits 17:22 - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."]
     #[inline(always)]
-    #[must_use]
     pub fn max_select(&mut self) -> MAX_SELECT_W<M0_TIMING_SPEC> {
         MAX_SELECT_W::new(self, 17)
     }
     #[doc = "Bits 23:24 - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn select_hold(&mut self) -> SELECT_HOLD_W<M0_TIMING_SPEC> {
         SELECT_HOLD_W::new(self, 23)
     }
     #[doc = "Bit 25 - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."]
     #[inline(always)]
-    #[must_use]
     pub fn select_setup(&mut self) -> SELECT_SETUP_W<M0_TIMING_SPEC> {
         SELECT_SETUP_W::new(self, 25)
     }
     #[doc = "Bits 28:29 - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn pagebreak(&mut self) -> PAGEBREAK_W<M0_TIMING_SPEC> {
         PAGEBREAK_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."]
     #[inline(always)]
-    #[must_use]
     pub fn cooldown(&mut self) -> COOLDOWN_W<M0_TIMING_SPEC> {
         COOLDOWN_W::new(self, 30)
     }
diff --git a/src/inner/qmi/m0_wcmd.rs b/src/inner/qmi/m0_wcmd.rs
index 2856b43..59a4569 100644
--- a/src/inner/qmi/m0_wcmd.rs
+++ b/src/inner/qmi/m0_wcmd.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn prefix(&mut self) -> PREFIX_W<M0_WCMD_SPEC> {
         PREFIX_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix(&mut self) -> SUFFIX_W<M0_WCMD_SPEC> {
         SUFFIX_W::new(self, 8)
     }
diff --git a/src/inner/qmi/m0_wfmt.rs b/src/inner/qmi/m0_wfmt.rs
index 8a2cb2e..491bdea 100644
--- a/src/inner/qmi/m0_wfmt.rs
+++ b/src/inner/qmi/m0_wfmt.rs
@@ -688,55 +688,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W<M0_WFMT_SPEC> {
         PREFIX_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_width(&mut self) -> ADDR_WIDTH_W<M0_WFMT_SPEC> {
         ADDR_WIDTH_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W<M0_WFMT_SPEC> {
         SUFFIX_WIDTH_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W<M0_WFMT_SPEC> {
         DUMMY_WIDTH_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - The width used for the data transfer"]
     #[inline(always)]
-    #[must_use]
     pub fn data_width(&mut self) -> DATA_WIDTH_W<M0_WFMT_SPEC> {
         DATA_WIDTH_W::new(self, 8)
     }
     #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_len(&mut self) -> PREFIX_LEN_W<M0_WFMT_SPEC> {
         PREFIX_LEN_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_len(&mut self) -> SUFFIX_LEN_W<M0_WFMT_SPEC> {
         SUFFIX_LEN_W::new(self, 14)
     }
     #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_len(&mut self) -> DUMMY_LEN_W<M0_WFMT_SPEC> {
         DUMMY_LEN_W::new(self, 16)
     }
     #[doc = "Bit 28 - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr(&mut self) -> DTR_W<M0_WFMT_SPEC> {
         DTR_W::new(self, 28)
     }
diff --git a/src/inner/qmi/m1_rcmd.rs b/src/inner/qmi/m1_rcmd.rs
index 07e5f43..3046c8b 100644
--- a/src/inner/qmi/m1_rcmd.rs
+++ b/src/inner/qmi/m1_rcmd.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn prefix(&mut self) -> PREFIX_W<M1_RCMD_SPEC> {
         PREFIX_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix(&mut self) -> SUFFIX_W<M1_RCMD_SPEC> {
         SUFFIX_W::new(self, 8)
     }
diff --git a/src/inner/qmi/m1_rfmt.rs b/src/inner/qmi/m1_rfmt.rs
index 9870360..ff6261c 100644
--- a/src/inner/qmi/m1_rfmt.rs
+++ b/src/inner/qmi/m1_rfmt.rs
@@ -688,55 +688,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W<M1_RFMT_SPEC> {
         PREFIX_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_width(&mut self) -> ADDR_WIDTH_W<M1_RFMT_SPEC> {
         ADDR_WIDTH_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W<M1_RFMT_SPEC> {
         SUFFIX_WIDTH_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W<M1_RFMT_SPEC> {
         DUMMY_WIDTH_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - The width used for the data transfer"]
     #[inline(always)]
-    #[must_use]
     pub fn data_width(&mut self) -> DATA_WIDTH_W<M1_RFMT_SPEC> {
         DATA_WIDTH_W::new(self, 8)
     }
     #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_len(&mut self) -> PREFIX_LEN_W<M1_RFMT_SPEC> {
         PREFIX_LEN_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_len(&mut self) -> SUFFIX_LEN_W<M1_RFMT_SPEC> {
         SUFFIX_LEN_W::new(self, 14)
     }
     #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_len(&mut self) -> DUMMY_LEN_W<M1_RFMT_SPEC> {
         DUMMY_LEN_W::new(self, 16)
     }
     #[doc = "Bit 28 - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr(&mut self) -> DTR_W<M1_RFMT_SPEC> {
         DTR_W::new(self, 28)
     }
diff --git a/src/inner/qmi/m1_timing.rs b/src/inner/qmi/m1_timing.rs
index af948bf..9284815 100644
--- a/src/inner/qmi/m1_timing.rs
+++ b/src/inner/qmi/m1_timing.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."]
     #[inline(always)]
-    #[must_use]
     pub fn clkdiv(&mut self) -> CLKDIV_W<M1_TIMING_SPEC> {
         CLKDIV_W::new(self, 0)
     }
     #[doc = "Bits 8:10 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."]
     #[inline(always)]
-    #[must_use]
     pub fn rxdelay(&mut self) -> RXDELAY_W<M1_TIMING_SPEC> {
         RXDELAY_W::new(self, 8)
     }
     #[doc = "Bits 12:16 - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."]
     #[inline(always)]
-    #[must_use]
     pub fn min_deselect(&mut self) -> MIN_DESELECT_W<M1_TIMING_SPEC> {
         MIN_DESELECT_W::new(self, 12)
     }
     #[doc = "Bits 17:22 - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."]
     #[inline(always)]
-    #[must_use]
     pub fn max_select(&mut self) -> MAX_SELECT_W<M1_TIMING_SPEC> {
         MAX_SELECT_W::new(self, 17)
     }
     #[doc = "Bits 23:24 - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn select_hold(&mut self) -> SELECT_HOLD_W<M1_TIMING_SPEC> {
         SELECT_HOLD_W::new(self, 23)
     }
     #[doc = "Bit 25 - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."]
     #[inline(always)]
-    #[must_use]
     pub fn select_setup(&mut self) -> SELECT_SETUP_W<M1_TIMING_SPEC> {
         SELECT_SETUP_W::new(self, 25)
     }
     #[doc = "Bits 28:29 - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."]
     #[inline(always)]
-    #[must_use]
     pub fn pagebreak(&mut self) -> PAGEBREAK_W<M1_TIMING_SPEC> {
         PAGEBREAK_W::new(self, 28)
     }
     #[doc = "Bits 30:31 - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."]
     #[inline(always)]
-    #[must_use]
     pub fn cooldown(&mut self) -> COOLDOWN_W<M1_TIMING_SPEC> {
         COOLDOWN_W::new(self, 30)
     }
diff --git a/src/inner/qmi/m1_wcmd.rs b/src/inner/qmi/m1_wcmd.rs
index 981ad1a..d5a993d 100644
--- a/src/inner/qmi/m1_wcmd.rs
+++ b/src/inner/qmi/m1_wcmd.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn prefix(&mut self) -> PREFIX_W<M1_WCMD_SPEC> {
         PREFIX_W::new(self, 0)
     }
     #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix(&mut self) -> SUFFIX_W<M1_WCMD_SPEC> {
         SUFFIX_W::new(self, 8)
     }
diff --git a/src/inner/qmi/m1_wfmt.rs b/src/inner/qmi/m1_wfmt.rs
index 2184764..75e0b29 100644
--- a/src/inner/qmi/m1_wfmt.rs
+++ b/src/inner/qmi/m1_wfmt.rs
@@ -688,55 +688,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W<M1_WFMT_SPEC> {
         PREFIX_WIDTH_W::new(self, 0)
     }
     #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."]
     #[inline(always)]
-    #[must_use]
     pub fn addr_width(&mut self) -> ADDR_WIDTH_W<M1_WFMT_SPEC> {
         ADDR_WIDTH_W::new(self, 2)
     }
     #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W<M1_WFMT_SPEC> {
         SUFFIX_WIDTH_W::new(self, 4)
     }
     #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W<M1_WFMT_SPEC> {
         DUMMY_WIDTH_W::new(self, 6)
     }
     #[doc = "Bits 8:9 - The width used for the data transfer"]
     #[inline(always)]
-    #[must_use]
     pub fn data_width(&mut self) -> DATA_WIDTH_W<M1_WFMT_SPEC> {
         DATA_WIDTH_W::new(self, 8)
     }
     #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn prefix_len(&mut self) -> PREFIX_LEN_W<M1_WFMT_SPEC> {
         PREFIX_LEN_W::new(self, 12)
     }
     #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."]
     #[inline(always)]
-    #[must_use]
     pub fn suffix_len(&mut self) -> SUFFIX_LEN_W<M1_WFMT_SPEC> {
         SUFFIX_LEN_W::new(self, 14)
     }
     #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"]
     #[inline(always)]
-    #[must_use]
     pub fn dummy_len(&mut self) -> DUMMY_LEN_W<M1_WFMT_SPEC> {
         DUMMY_LEN_W::new(self, 16)
     }
     #[doc = "Bit 28 - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr(&mut self) -> DTR_W<M1_WFMT_SPEC> {
         DTR_W::new(self, 28)
     }
diff --git a/src/inner/resets/reset.rs b/src/inner/resets/reset.rs
index 898655a..bae384d 100644
--- a/src/inner/resets/reset.rs
+++ b/src/inner/resets/reset.rs
@@ -268,175 +268,146 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn adc(&mut self) -> ADC_W<RESET_SPEC> {
         ADC_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn busctrl(&mut self) -> BUSCTRL_W<RESET_SPEC> {
         BUSCTRL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<RESET_SPEC> {
         DMA_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn hstx(&mut self) -> HSTX_W<RESET_SPEC> {
         HSTX_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c0(&mut self) -> I2C0_W<RESET_SPEC> {
         I2C0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c1(&mut self) -> I2C1_W<RESET_SPEC> {
         I2C1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn io_bank0(&mut self) -> IO_BANK0_W<RESET_SPEC> {
         IO_BANK0_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn io_qspi(&mut self) -> IO_QSPI_W<RESET_SPEC> {
         IO_QSPI_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn jtag(&mut self) -> JTAG_W<RESET_SPEC> {
         JTAG_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn pads_bank0(&mut self) -> PADS_BANK0_W<RESET_SPEC> {
         PADS_BANK0_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pads_qspi(&mut self) -> PADS_QSPI_W<RESET_SPEC> {
         PADS_QSPI_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pio0(&mut self) -> PIO0_W<RESET_SPEC> {
         PIO0_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn pio1(&mut self) -> PIO1_W<RESET_SPEC> {
         PIO1_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn pio2(&mut self) -> PIO2_W<RESET_SPEC> {
         PIO2_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_sys(&mut self) -> PLL_SYS_W<RESET_SPEC> {
         PLL_SYS_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_usb(&mut self) -> PLL_USB_W<RESET_SPEC> {
         PLL_USB_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm(&mut self) -> PWM_W<RESET_SPEC> {
         PWM_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sha256(&mut self) -> SHA256_W<RESET_SPEC> {
         SHA256_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn spi0(&mut self) -> SPI0_W<RESET_SPEC> {
         SPI0_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn spi1(&mut self) -> SPI1_W<RESET_SPEC> {
         SPI1_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn syscfg(&mut self) -> SYSCFG_W<RESET_SPEC> {
         SYSCFG_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn sysinfo(&mut self) -> SYSINFO_W<RESET_SPEC> {
         SYSINFO_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn tbman(&mut self) -> TBMAN_W<RESET_SPEC> {
         TBMAN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0(&mut self) -> TIMER0_W<RESET_SPEC> {
         TIMER0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1(&mut self) -> TIMER1_W<RESET_SPEC> {
         TIMER1_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn trng(&mut self) -> TRNG_W<RESET_SPEC> {
         TRNG_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn uart0(&mut self) -> UART0_W<RESET_SPEC> {
         UART0_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1(&mut self) -> UART1_W<RESET_SPEC> {
         UART1_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn usbctrl(&mut self) -> USBCTRL_W<RESET_SPEC> {
         USBCTRL_W::new(self, 28)
     }
diff --git a/src/inner/resets/wdsel.rs b/src/inner/resets/wdsel.rs
index 0c73ec6..3b805bc 100644
--- a/src/inner/resets/wdsel.rs
+++ b/src/inner/resets/wdsel.rs
@@ -268,175 +268,146 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn adc(&mut self) -> ADC_W<WDSEL_SPEC> {
         ADC_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn busctrl(&mut self) -> BUSCTRL_W<WDSEL_SPEC> {
         BUSCTRL_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn dma(&mut self) -> DMA_W<WDSEL_SPEC> {
         DMA_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn hstx(&mut self) -> HSTX_W<WDSEL_SPEC> {
         HSTX_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c0(&mut self) -> I2C0_W<WDSEL_SPEC> {
         I2C0_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn i2c1(&mut self) -> I2C1_W<WDSEL_SPEC> {
         I2C1_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn io_bank0(&mut self) -> IO_BANK0_W<WDSEL_SPEC> {
         IO_BANK0_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn io_qspi(&mut self) -> IO_QSPI_W<WDSEL_SPEC> {
         IO_QSPI_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn jtag(&mut self) -> JTAG_W<WDSEL_SPEC> {
         JTAG_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn pads_bank0(&mut self) -> PADS_BANK0_W<WDSEL_SPEC> {
         PADS_BANK0_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn pads_qspi(&mut self) -> PADS_QSPI_W<WDSEL_SPEC> {
         PADS_QSPI_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn pio0(&mut self) -> PIO0_W<WDSEL_SPEC> {
         PIO0_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn pio1(&mut self) -> PIO1_W<WDSEL_SPEC> {
         PIO1_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn pio2(&mut self) -> PIO2_W<WDSEL_SPEC> {
         PIO2_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_sys(&mut self) -> PLL_SYS_W<WDSEL_SPEC> {
         PLL_SYS_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn pll_usb(&mut self) -> PLL_USB_W<WDSEL_SPEC> {
         PLL_USB_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn pwm(&mut self) -> PWM_W<WDSEL_SPEC> {
         PWM_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn sha256(&mut self) -> SHA256_W<WDSEL_SPEC> {
         SHA256_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn spi0(&mut self) -> SPI0_W<WDSEL_SPEC> {
         SPI0_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn spi1(&mut self) -> SPI1_W<WDSEL_SPEC> {
         SPI1_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn syscfg(&mut self) -> SYSCFG_W<WDSEL_SPEC> {
         SYSCFG_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn sysinfo(&mut self) -> SYSINFO_W<WDSEL_SPEC> {
         SYSINFO_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn tbman(&mut self) -> TBMAN_W<WDSEL_SPEC> {
         TBMAN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn timer0(&mut self) -> TIMER0_W<WDSEL_SPEC> {
         TIMER0_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn timer1(&mut self) -> TIMER1_W<WDSEL_SPEC> {
         TIMER1_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn trng(&mut self) -> TRNG_W<WDSEL_SPEC> {
         TRNG_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn uart0(&mut self) -> UART0_W<WDSEL_SPEC> {
         UART0_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn uart1(&mut self) -> UART1_W<WDSEL_SPEC> {
         UART1_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn usbctrl(&mut self) -> USBCTRL_W<WDSEL_SPEC> {
         USBCTRL_W::new(self, 28)
     }
diff --git a/src/inner/rosc.rs b/src/inner/rosc.rs
index ad6cbd1..cc08cfc 100644
--- a/src/inner/rosc.rs
+++ b/src/inner/rosc.rs
@@ -18,7 +18,7 @@ impl RegisterBlock {
     pub const fn ctrl(&self) -> &CTRL {
         &self.ctrl
     }
-    #[doc = "0x04 - The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 &amp; DS1_RANDOM=1"]
+    #[doc = "0x04 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"]
     #[inline(always)]
     pub const fn freqa(&self) -> &FREQA {
         &self.freqa
@@ -73,14 +73,14 @@ module"]
 pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
 #[doc = "Ring Oscillator control"]
 pub mod ctrl;
-#[doc = "FREQA (rw) register accessor: The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 &amp; DS1_RANDOM=1  
+#[doc = "FREQA (rw) register accessor: The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1  
 
 You can [`read`](crate::Reg::read) this register and get [`freqa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@freqa`]
 module"]
 pub type FREQA = crate::Reg<freqa::FREQA_SPEC>;
-#[doc = "The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 &amp; DS1_RANDOM=1"]
+#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"]
 pub mod freqa;
 #[doc = "FREQB (rw) register accessor: For a detailed description see freqa register  
 
diff --git a/src/inner/rosc/count.rs b/src/inner/rosc/count.rs
index ae40e23..dbba292 100644
--- a/src/inner/rosc/count.rs
+++ b/src/inner/rosc/count.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn count(&mut self) -> COUNT_W<COUNT_SPEC> {
         COUNT_W::new(self, 0)
     }
diff --git a/src/inner/rosc/ctrl.rs b/src/inner/rosc/ctrl.rs
index 63436d4..9154954 100644
--- a/src/inner/rosc/ctrl.rs
+++ b/src/inner/rosc/ctrl.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"]
     #[inline(always)]
-    #[must_use]
     pub fn freq_range(&mut self) -> FREQ_RANGE_W<CTRL_SPEC> {
         FREQ_RANGE_W::new(self, 0)
     }
     #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CTRL_SPEC> {
         ENABLE_W::new(self, 12)
     }
diff --git a/src/inner/rosc/div.rs b/src/inner/rosc/div.rs
index 8a7d148..02e7916 100644
--- a/src/inner/rosc/div.rs
+++ b/src/inner/rosc/div.rs
@@ -61,7 +61,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"]
     #[inline(always)]
-    #[must_use]
     pub fn div(&mut self) -> DIV_W<DIV_SPEC> {
         DIV_W::new(self, 0)
     }
diff --git a/src/inner/rosc/dormant.rs b/src/inner/rosc/dormant.rs
index 041aea3..5589914 100644
--- a/src/inner/rosc/dormant.rs
+++ b/src/inner/rosc/dormant.rs
@@ -74,7 +74,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"]
     #[inline(always)]
-    #[must_use]
     pub fn dormant(&mut self) -> DORMANT_W<DORMANT_SPEC> {
         DORMANT_W::new(self, 0)
     }
diff --git a/src/inner/rosc/freqa.rs b/src/inner/rosc/freqa.rs
index 292de68..ddef6b8 100644
--- a/src/inner/rosc/freqa.rs
+++ b/src/inner/rosc/freqa.rs
@@ -115,48 +115,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:2 - Stage 0 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds0(&mut self) -> DS0_W<FREQA_SPEC> {
         DS0_W::new(self, 0)
     }
     #[doc = "Bit 3 - Randomises the stage 0 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds0_random(&mut self) -> DS0_RANDOM_W<FREQA_SPEC> {
         DS0_RANDOM_W::new(self, 3)
     }
     #[doc = "Bits 4:6 - Stage 1 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds1(&mut self) -> DS1_W<FREQA_SPEC> {
         DS1_W::new(self, 4)
     }
     #[doc = "Bit 7 - Randomises the stage 1 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds1_random(&mut self) -> DS1_RANDOM_W<FREQA_SPEC> {
         DS1_RANDOM_W::new(self, 7)
     }
     #[doc = "Bits 8:10 - Stage 2 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds2(&mut self) -> DS2_W<FREQA_SPEC> {
         DS2_W::new(self, 8)
     }
     #[doc = "Bits 12:14 - Stage 3 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds3(&mut self) -> DS3_W<FREQA_SPEC> {
         DS3_W::new(self, 12)
     }
     #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
     #[inline(always)]
-    #[must_use]
     pub fn passwd(&mut self) -> PASSWD_W<FREQA_SPEC> {
         PASSWD_W::new(self, 16)
     }
 }
-#[doc = "The FREQA &amp; FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 &amp; DS1_RANDOM=1  
+#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1  
 
 You can [`read`](crate::Reg::read) this register and get [`freqa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FREQA_SPEC;
diff --git a/src/inner/rosc/freqb.rs b/src/inner/rosc/freqb.rs
index b747ed4..830c1d2 100644
--- a/src/inner/rosc/freqb.rs
+++ b/src/inner/rosc/freqb.rs
@@ -97,31 +97,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:2 - Stage 4 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds4(&mut self) -> DS4_W<FREQB_SPEC> {
         DS4_W::new(self, 0)
     }
     #[doc = "Bits 4:6 - Stage 5 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds5(&mut self) -> DS5_W<FREQB_SPEC> {
         DS5_W::new(self, 4)
     }
     #[doc = "Bits 8:10 - Stage 6 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds6(&mut self) -> DS6_W<FREQB_SPEC> {
         DS6_W::new(self, 8)
     }
     #[doc = "Bits 12:14 - Stage 7 drive strength"]
     #[inline(always)]
-    #[must_use]
     pub fn ds7(&mut self) -> DS7_W<FREQB_SPEC> {
         DS7_W::new(self, 12)
     }
     #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"]
     #[inline(always)]
-    #[must_use]
     pub fn passwd(&mut self) -> PASSWD_W<FREQB_SPEC> {
         PASSWD_W::new(self, 16)
     }
diff --git a/src/inner/rosc/phase.rs b/src/inner/rosc/phase.rs
index 11f24eb..68a8827 100644
--- a/src/inner/rosc/phase.rs
+++ b/src/inner/rosc/phase.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<PHASE_SPEC> {
         SHIFT_W::new(self, 0)
     }
     #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"]
     #[inline(always)]
-    #[must_use]
     pub fn flip(&mut self) -> FLIP_W<PHASE_SPEC> {
         FLIP_W::new(self, 2)
     }
     #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<PHASE_SPEC> {
         ENABLE_W::new(self, 3)
     }
     #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"]
     #[inline(always)]
-    #[must_use]
     pub fn passwd(&mut self) -> PASSWD_W<PHASE_SPEC> {
         PASSWD_W::new(self, 4)
     }
diff --git a/src/inner/rosc/random.rs b/src/inner/rosc/random.rs
index 54dff0d..8e5f297 100644
--- a/src/inner/rosc/random.rs
+++ b/src/inner/rosc/random.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn seed(&mut self) -> SEED_W<RANDOM_SPEC> {
         SEED_W::new(self, 0)
     }
diff --git a/src/inner/rosc/status.rs b/src/inner/rosc/status.rs
index b27f57b..2d8efcd 100644
--- a/src/inner/rosc/status.rs
+++ b/src/inner/rosc/status.rs
@@ -37,7 +37,6 @@ impl R {
 impl W {
     #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"]
     #[inline(always)]
-    #[must_use]
     pub fn badwrite(&mut self) -> BADWRITE_W<STATUS_SPEC> {
         BADWRITE_W::new(self, 24)
     }
diff --git a/src/inner/sha256/csr.rs b/src/inner/sha256/csr.rs
index 22eca7a..a4904ad 100644
--- a/src/inner/sha256/csr.rs
+++ b/src/inner/sha256/csr.rs
@@ -121,25 +121,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers."]
     #[inline(always)]
-    #[must_use]
     pub fn start(&mut self) -> START_W<CSR_SPEC> {
         START_W::new(self, 0)
     }
     #[doc = "Bit 4 - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn err_wdata_not_rdy(&mut self) -> ERR_WDATA_NOT_RDY_W<CSR_SPEC> {
         ERR_WDATA_NOT_RDY_W::new(self, 4)
     }
     #[doc = "Bits 8:9 - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."]
     #[inline(always)]
-    #[must_use]
     pub fn dma_size(&mut self) -> DMA_SIZE_W<CSR_SPEC> {
         DMA_SIZE_W::new(self, 8)
     }
     #[doc = "Bit 12 - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."]
     #[inline(always)]
-    #[must_use]
     pub fn bswap(&mut self) -> BSWAP_W<CSR_SPEC> {
         BSWAP_W::new(self, 12)
     }
diff --git a/src/inner/sha256/wdata.rs b/src/inner/sha256/wdata.rs
index be15620..014cbb0 100644
--- a/src/inner/sha256/wdata.rs
+++ b/src/inner/sha256/wdata.rs
@@ -7,7 +7,6 @@ pub type WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31 - After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. After this, WDATA_RDY will return high, and more data can be written (if any). This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block."]
     #[inline(always)]
-    #[must_use]
     pub fn wdata(&mut self) -> WDATA_W<WDATA_SPEC> {
         WDATA_W::new(self, 0)
     }
diff --git a/src/inner/sio.rs b/src/inner/sio.rs
index c403bcf..b8f46d2 100644
--- a/src/inner/sio.rs
+++ b/src/inner/sio.rs
@@ -124,7 +124,7 @@ impl RegisterBlock {
     pub const fn gpio_out_clr(&self) -> &GPIO_OUT_CLR {
         &self.gpio_out_clr
     }
-    #[doc = "0x24 - Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`"]
+    #[doc = "0x24 - Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"]
     #[inline(always)]
     pub const fn gpio_hi_out_clr(&self) -> &GPIO_HI_OUT_CLR {
         &self.gpio_hi_out_clr
@@ -164,7 +164,7 @@ impl RegisterBlock {
     pub const fn gpio_oe_clr(&self) -> &GPIO_OE_CLR {
         &self.gpio_oe_clr
     }
-    #[doc = "0x44 - Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`"]
+    #[doc = "0x44 - Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"]
     #[inline(always)]
     pub const fn gpio_hi_oe_clr(&self) -> &GPIO_HI_OE_CLR {
         &self.gpio_hi_oe_clr
@@ -359,13 +359,13 @@ impl RegisterBlock {
     pub const fn interp1_base_1and0(&self) -> &INTERP1_BASE_1AND0 {
         &self.interp1_base_1and0
     }
-    #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 &lt;&lt; lock number."]
+    #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."]
     #[inline(always)]
     pub const fn spinlock(&self, n: usize) -> &SPINLOCK {
         &self.spinlock[n]
     }
     #[doc = "Iterator for array of:"]
-    #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 &lt;&lt; lock number."]
+    #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."]
     #[inline(always)]
     pub fn spinlock_iter(&self) -> impl Iterator<Item = &SPINLOCK> {
         self.spinlock.iter()
@@ -548,14 +548,14 @@ module"]
 pub type GPIO_OUT_CLR = crate::Reg<gpio_out_clr::GPIO_OUT_CLR_SPEC>;
 #[doc = "GPIO0...31 output value clear"]
 pub mod gpio_out_clr;
-#[doc = "GPIO_HI_OUT_CLR (rw) register accessor: Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`  
+#[doc = "GPIO_HI_OUT_CLR (rw) register accessor: Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`  
 
 You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_out_clr`]
 module"]
 pub type GPIO_HI_OUT_CLR = crate::Reg<gpio_hi_out_clr::GPIO_HI_OUT_CLR_SPEC>;
-#[doc = "Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`"]
+#[doc = "Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"]
 pub mod gpio_hi_out_clr;
 #[doc = "GPIO_OUT_XOR (rw) register accessor: GPIO0...31 output value XOR  
 
@@ -620,14 +620,14 @@ module"]
 pub type GPIO_OE_CLR = crate::Reg<gpio_oe_clr::GPIO_OE_CLR_SPEC>;
 #[doc = "GPIO0...31 output enable clear"]
 pub mod gpio_oe_clr;
-#[doc = "GPIO_HI_OE_CLR (rw) register accessor: Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`  
+#[doc = "GPIO_HI_OE_CLR (rw) register accessor: Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`  
 
 You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@gpio_hi_oe_clr`]
 module"]
 pub type GPIO_HI_OE_CLR = crate::Reg<gpio_hi_oe_clr::GPIO_HI_OE_CLR_SPEC>;
-#[doc = "Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`"]
+#[doc = "Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"]
 pub mod gpio_hi_oe_clr;
 #[doc = "GPIO_OE_XOR (rw) register accessor: GPIO0...31 output enable XOR  
 
@@ -971,14 +971,14 @@ module"]
 pub type INTERP1_BASE_1AND0 = crate::Reg<interp1_base_1and0::INTERP1_BASE_1AND0_SPEC>;
 #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."]
 pub mod interp1_base_1and0;
-#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 &lt;&lt; lock number.  
+#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.  
 
 You can [`read`](crate::Reg::read) this register and get [`spinlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@spinlock`]
 module"]
 pub type SPINLOCK = crate::Reg<spinlock::SPINLOCK_SPEC>;
-#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 &lt;&lt; lock number."]
+#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."]
 pub mod spinlock;
 #[doc = "DOORBELL_OUT_SET (rw) register accessor: Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status.  
 
diff --git a/src/inner/sio/doorbell_in_clr.rs b/src/inner/sio/doorbell_in_clr.rs
index 085f48d..a0809c4 100644
--- a/src/inner/sio/doorbell_in_clr.rs
+++ b/src/inner/sio/doorbell_in_clr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn doorbell_in_clr(&mut self) -> DOORBELL_IN_CLR_W<DOORBELL_IN_CLR_SPEC> {
         DOORBELL_IN_CLR_W::new(self, 0)
     }
diff --git a/src/inner/sio/doorbell_in_set.rs b/src/inner/sio/doorbell_in_set.rs
index c66cbb9..c126f54 100644
--- a/src/inner/sio/doorbell_in_set.rs
+++ b/src/inner/sio/doorbell_in_set.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn doorbell_in_set(&mut self) -> DOORBELL_IN_SET_W<DOORBELL_IN_SET_SPEC> {
         DOORBELL_IN_SET_W::new(self, 0)
     }
diff --git a/src/inner/sio/doorbell_out_clr.rs b/src/inner/sio/doorbell_out_clr.rs
index 237ae5f..fcb14b6 100644
--- a/src/inner/sio/doorbell_out_clr.rs
+++ b/src/inner/sio/doorbell_out_clr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn doorbell_out_clr(&mut self) -> DOORBELL_OUT_CLR_W<DOORBELL_OUT_CLR_SPEC> {
         DOORBELL_OUT_CLR_W::new(self, 0)
     }
diff --git a/src/inner/sio/doorbell_out_set.rs b/src/inner/sio/doorbell_out_set.rs
index 18e2612..5692e3e 100644
--- a/src/inner/sio/doorbell_out_set.rs
+++ b/src/inner/sio/doorbell_out_set.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn doorbell_out_set(&mut self) -> DOORBELL_OUT_SET_W<DOORBELL_OUT_SET_SPEC> {
         DOORBELL_OUT_SET_W::new(self, 0)
     }
diff --git a/src/inner/sio/fifo_st.rs b/src/inner/sio/fifo_st.rs
index da98203..f2ccc87 100644
--- a/src/inner/sio/fifo_st.rs
+++ b/src/inner/sio/fifo_st.rs
@@ -39,13 +39,11 @@ impl R {
 impl W {
     #[doc = "Bit 2 - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn wof(&mut self) -> WOF_W<FIFO_ST_SPEC> {
         WOF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn roe(&mut self) -> ROE_W<FIFO_ST_SPEC> {
         ROE_W::new(self, 3)
     }
diff --git a/src/inner/sio/fifo_wr.rs b/src/inner/sio/fifo_wr.rs
index 262b0b4..d82080a 100644
--- a/src/inner/sio/fifo_wr.rs
+++ b/src/inner/sio/fifo_wr.rs
@@ -7,7 +7,6 @@ pub type FIFO_WR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn fifo_wr(&mut self) -> FIFO_WR_W<FIFO_WR_SPEC> {
         FIFO_WR_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_hi_oe.rs b/src/inner/sio/gpio_hi_oe.rs
index 746beba..29d2a71 100644
--- a/src/inner/sio/gpio_hi_oe.rs
+++ b/src/inner/sio/gpio_hi_oe.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Output enable value for GPIO32...47"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OE_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24 - Output enable value for USB D+ pin"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OE_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25 - Output enable value for USB D- pin"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OE_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26 - Output enable value for QSPI SCK pin"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OE_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27 - Output enable value for QSPI CSn pin"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OE_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31 - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OE_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/sio/gpio_hi_oe_clr.rs b/src/inner/sio/gpio_hi_oe_clr.rs
index 21270a0..c8e4cdc 100644
--- a/src/inner/sio/gpio_hi_oe_clr.rs
+++ b/src/inner/sio/gpio_hi_oe_clr.rs
@@ -17,42 +17,36 @@ pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OE_CLR_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OE_CLR_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OE_CLR_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OE_CLR_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OE_CLR_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OE_CLR_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
 }
-#[doc = "Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &amp;= ~wdata`  
+#[doc = "Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`  
 
 You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OE_CLR_SPEC;
diff --git a/src/inner/sio/gpio_hi_oe_set.rs b/src/inner/sio/gpio_hi_oe_set.rs
index 2418655..013279f 100644
--- a/src/inner/sio/gpio_hi_oe_set.rs
+++ b/src/inner/sio/gpio_hi_oe_set.rs
@@ -17,37 +17,31 @@ pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OE_SET_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OE_SET_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OE_SET_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OE_SET_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OE_SET_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OE_SET_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/sio/gpio_hi_oe_xor.rs b/src/inner/sio/gpio_hi_oe_xor.rs
index cb4965e..cf5d557 100644
--- a/src/inner/sio/gpio_hi_oe_xor.rs
+++ b/src/inner/sio/gpio_hi_oe_xor.rs
@@ -17,37 +17,31 @@ pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OE_XOR_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OE_XOR_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OE_XOR_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OE_XOR_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OE_XOR_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OE_XOR_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/sio/gpio_hi_out.rs b/src/inner/sio/gpio_hi_out.rs
index 252b8e2..781c55e 100644
--- a/src/inner/sio/gpio_hi_out.rs
+++ b/src/inner/sio/gpio_hi_out.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Output value for GPIO32...47"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OUT_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24 - Output value for USB D+ pin"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OUT_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25 - Output value for USB D- pin"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OUT_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26 - Output value for QSPI SCK pin"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OUT_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27 - Output value for QSPI CSn pin"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OUT_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31 - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OUT_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/sio/gpio_hi_out_clr.rs b/src/inner/sio/gpio_hi_out_clr.rs
index c443f6b..932f51f 100644
--- a/src/inner/sio/gpio_hi_out_clr.rs
+++ b/src/inner/sio/gpio_hi_out_clr.rs
@@ -17,42 +17,36 @@ pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OUT_CLR_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OUT_CLR_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OUT_CLR_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OUT_CLR_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OUT_CLR_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OUT_CLR_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
 }
-#[doc = "Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &amp;= ~wdata`  
+#[doc = "Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`  
 
 You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct GPIO_HI_OUT_CLR_SPEC;
diff --git a/src/inner/sio/gpio_hi_out_set.rs b/src/inner/sio/gpio_hi_out_set.rs
index c736c70..cba2e7a 100644
--- a/src/inner/sio/gpio_hi_out_set.rs
+++ b/src/inner/sio/gpio_hi_out_set.rs
@@ -17,37 +17,31 @@ pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OUT_SET_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OUT_SET_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OUT_SET_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OUT_SET_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OUT_SET_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OUT_SET_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/sio/gpio_hi_out_xor.rs b/src/inner/sio/gpio_hi_out_xor.rs
index 22ca85a..b790f90 100644
--- a/src/inner/sio/gpio_hi_out_xor.rs
+++ b/src/inner/sio/gpio_hi_out_xor.rs
@@ -17,37 +17,31 @@ pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<GPIO_HI_OUT_XOR_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<GPIO_HI_OUT_XOR_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<GPIO_HI_OUT_XOR_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<GPIO_HI_OUT_XOR_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<GPIO_HI_OUT_XOR_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<GPIO_HI_OUT_XOR_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/sio/gpio_oe.rs b/src/inner/sio/gpio_oe.rs
index 1ff3bf5..4f730bb 100644
--- a/src/inner/sio/gpio_oe.rs
+++ b/src/inner/sio/gpio_oe.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_oe(&mut self) -> GPIO_OE_W<GPIO_OE_SPEC> {
         GPIO_OE_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_oe_clr.rs b/src/inner/sio/gpio_oe_clr.rs
index aecb563..4367f51 100644
--- a/src/inner/sio/gpio_oe_clr.rs
+++ b/src/inner/sio/gpio_oe_clr.rs
@@ -2,12 +2,11 @@
 pub type R = crate::R<GPIO_OE_CLR_SPEC>;
 #[doc = "Register `GPIO_OE_CLR` writer"]
 pub type W = crate::W<GPIO_OE_CLR_SPEC>;
-#[doc = "Field `GPIO_OE_CLR` writer - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`"]
+#[doc = "Field `GPIO_OE_CLR` writer - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"]
 pub type GPIO_OE_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
-    #[doc = "Bits 0:31 - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &amp;= ~wdata`"]
+    #[doc = "Bits 0:31 - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_oe_clr(&mut self) -> GPIO_OE_CLR_W<GPIO_OE_CLR_SPEC> {
         GPIO_OE_CLR_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_oe_set.rs b/src/inner/sio/gpio_oe_set.rs
index 6ee555e..66b6f73 100644
--- a/src/inner/sio/gpio_oe_set.rs
+++ b/src/inner/sio/gpio_oe_set.rs
@@ -7,7 +7,6 @@ pub type GPIO_OE_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31 - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_oe_set(&mut self) -> GPIO_OE_SET_W<GPIO_OE_SET_SPEC> {
         GPIO_OE_SET_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_oe_xor.rs b/src/inner/sio/gpio_oe_xor.rs
index 5c9a7cf..3d5e869 100644
--- a/src/inner/sio/gpio_oe_xor.rs
+++ b/src/inner/sio/gpio_oe_xor.rs
@@ -7,7 +7,6 @@ pub type GPIO_OE_XOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31 - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_oe_xor(&mut self) -> GPIO_OE_XOR_W<GPIO_OE_XOR_SPEC> {
         GPIO_OE_XOR_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_out.rs b/src/inner/sio/gpio_out.rs
index 325499a..2272c40 100644
--- a/src/inner/sio/gpio_out.rs
+++ b/src/inner/sio/gpio_out.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_out(&mut self) -> GPIO_OUT_W<GPIO_OUT_SPEC> {
         GPIO_OUT_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_out_clr.rs b/src/inner/sio/gpio_out_clr.rs
index b5d0c71..974a846 100644
--- a/src/inner/sio/gpio_out_clr.rs
+++ b/src/inner/sio/gpio_out_clr.rs
@@ -2,12 +2,11 @@
 pub type R = crate::R<GPIO_OUT_CLR_SPEC>;
 #[doc = "Register `GPIO_OUT_CLR` writer"]
 pub type W = crate::W<GPIO_OUT_CLR_SPEC>;
-#[doc = "Field `GPIO_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`"]
+#[doc = "Field `GPIO_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"]
 pub type GPIO_OUT_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
-    #[doc = "Bits 0:31 - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &amp;= ~wdata`"]
+    #[doc = "Bits 0:31 - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_out_clr(&mut self) -> GPIO_OUT_CLR_W<GPIO_OUT_CLR_SPEC> {
         GPIO_OUT_CLR_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_out_set.rs b/src/inner/sio/gpio_out_set.rs
index 81e9a8e..1525417 100644
--- a/src/inner/sio/gpio_out_set.rs
+++ b/src/inner/sio/gpio_out_set.rs
@@ -7,7 +7,6 @@ pub type GPIO_OUT_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31 - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_out_set(&mut self) -> GPIO_OUT_SET_W<GPIO_OUT_SET_SPEC> {
         GPIO_OUT_SET_W::new(self, 0)
     }
diff --git a/src/inner/sio/gpio_out_xor.rs b/src/inner/sio/gpio_out_xor.rs
index 736047e..d8a885c 100644
--- a/src/inner/sio/gpio_out_xor.rs
+++ b/src/inner/sio/gpio_out_xor.rs
@@ -7,7 +7,6 @@ pub type GPIO_OUT_XOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31 - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio_out_xor(&mut self) -> GPIO_OUT_XOR_W<GPIO_OUT_XOR_SPEC> {
         GPIO_OUT_XOR_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_accum0.rs b/src/inner/sio/interp0_accum0.rs
index d171b7c..f6b26ba 100644
--- a/src/inner/sio/interp0_accum0.rs
+++ b/src/inner/sio/interp0_accum0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_accum0(&mut self) -> INTERP0_ACCUM0_W<INTERP0_ACCUM0_SPEC> {
         INTERP0_ACCUM0_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_accum0_add.rs b/src/inner/sio/interp0_accum0_add.rs
index a062c7f..a855017 100644
--- a/src/inner/sio/interp0_accum0_add.rs
+++ b/src/inner/sio/interp0_accum0_add.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_accum0_add(&mut self) -> INTERP0_ACCUM0_ADD_W<INTERP0_ACCUM0_ADD_SPEC> {
         INTERP0_ACCUM0_ADD_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_accum1.rs b/src/inner/sio/interp0_accum1.rs
index 2337f6a..ce06a3f 100644
--- a/src/inner/sio/interp0_accum1.rs
+++ b/src/inner/sio/interp0_accum1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_accum1(&mut self) -> INTERP0_ACCUM1_W<INTERP0_ACCUM1_SPEC> {
         INTERP0_ACCUM1_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_accum1_add.rs b/src/inner/sio/interp0_accum1_add.rs
index 7c73da4..a650db0 100644
--- a/src/inner/sio/interp0_accum1_add.rs
+++ b/src/inner/sio/interp0_accum1_add.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_accum1_add(&mut self) -> INTERP0_ACCUM1_ADD_W<INTERP0_ACCUM1_ADD_SPEC> {
         INTERP0_ACCUM1_ADD_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_base0.rs b/src/inner/sio/interp0_base0.rs
index 25d266e..0497035 100644
--- a/src/inner/sio/interp0_base0.rs
+++ b/src/inner/sio/interp0_base0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_base0(&mut self) -> INTERP0_BASE0_W<INTERP0_BASE0_SPEC> {
         INTERP0_BASE0_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_base1.rs b/src/inner/sio/interp0_base1.rs
index 7c6649c..efec100 100644
--- a/src/inner/sio/interp0_base1.rs
+++ b/src/inner/sio/interp0_base1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_base1(&mut self) -> INTERP0_BASE1_W<INTERP0_BASE1_SPEC> {
         INTERP0_BASE1_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_base2.rs b/src/inner/sio/interp0_base2.rs
index eefb4cd..948e6aa 100644
--- a/src/inner/sio/interp0_base2.rs
+++ b/src/inner/sio/interp0_base2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_base2(&mut self) -> INTERP0_BASE2_W<INTERP0_BASE2_SPEC> {
         INTERP0_BASE2_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_base_1and0.rs b/src/inner/sio/interp0_base_1and0.rs
index d4ba5e9..9a63b7c 100644
--- a/src/inner/sio/interp0_base_1and0.rs
+++ b/src/inner/sio/interp0_base_1and0.rs
@@ -7,7 +7,6 @@ pub type INTERP0_BASE_1AND0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp0_base_1and0(&mut self) -> INTERP0_BASE_1AND0_W<INTERP0_BASE_1AND0_SPEC> {
         INTERP0_BASE_1AND0_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp0_ctrl_lane0.rs b/src/inner/sio/interp0_ctrl_lane0.rs
index bf9bd86..9436941 100644
--- a/src/inner/sio/interp0_ctrl_lane0.rs
+++ b/src/inner/sio/interp0_ctrl_lane0.rs
@@ -10,9 +10,9 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 pub type MASK_LSB_R = crate::FieldReader;
 #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
 pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
-#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_R = crate::FieldReader;
-#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
 pub type SIGNED_R = crate::BitReader;
@@ -55,7 +55,7 @@ impl R {
     pub fn mask_lsb(&self) -> MASK_LSB_R {
         MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
     pub fn mask_msb(&self) -> MASK_MSB_R {
         MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
@@ -109,55 +109,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<INTERP0_CTRL_LANE0_SPEC> {
         SHIFT_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP0_CTRL_LANE0_SPEC> {
         MASK_LSB_W::new(self, 5)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP0_CTRL_LANE0_SPEC> {
         MASK_MSB_W::new(self, 10)
     }
     #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
     #[inline(always)]
-    #[must_use]
     pub fn signed(&mut self) -> SIGNED_W<INTERP0_CTRL_LANE0_SPEC> {
         SIGNED_W::new(self, 15)
     }
     #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
     #[inline(always)]
-    #[must_use]
     pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP0_CTRL_LANE0_SPEC> {
         CROSS_INPUT_W::new(self, 16)
     }
     #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
     #[inline(always)]
-    #[must_use]
     pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP0_CTRL_LANE0_SPEC> {
         CROSS_RESULT_W::new(self, 17)
     }
     #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
     #[inline(always)]
-    #[must_use]
     pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP0_CTRL_LANE0_SPEC> {
         ADD_RAW_W::new(self, 18)
     }
     #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP0_CTRL_LANE0_SPEC> {
         FORCE_MSB_W::new(self, 19)
     }
     #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."]
     #[inline(always)]
-    #[must_use]
     pub fn blend(&mut self) -> BLEND_W<INTERP0_CTRL_LANE0_SPEC> {
         BLEND_W::new(self, 21)
     }
diff --git a/src/inner/sio/interp0_ctrl_lane1.rs b/src/inner/sio/interp0_ctrl_lane1.rs
index 2e4c8ba..6a81ec2 100644
--- a/src/inner/sio/interp0_ctrl_lane1.rs
+++ b/src/inner/sio/interp0_ctrl_lane1.rs
@@ -10,9 +10,9 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 pub type MASK_LSB_R = crate::FieldReader;
 #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
 pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
-#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_R = crate::FieldReader;
-#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
 pub type SIGNED_R = crate::BitReader;
@@ -45,7 +45,7 @@ impl R {
     pub fn mask_lsb(&self) -> MASK_LSB_R {
         MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
     pub fn mask_msb(&self) -> MASK_MSB_R {
         MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<INTERP0_CTRL_LANE1_SPEC> {
         SHIFT_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP0_CTRL_LANE1_SPEC> {
         MASK_LSB_W::new(self, 5)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP0_CTRL_LANE1_SPEC> {
         MASK_MSB_W::new(self, 10)
     }
     #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
     #[inline(always)]
-    #[must_use]
     pub fn signed(&mut self) -> SIGNED_W<INTERP0_CTRL_LANE1_SPEC> {
         SIGNED_W::new(self, 15)
     }
     #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
     #[inline(always)]
-    #[must_use]
     pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP0_CTRL_LANE1_SPEC> {
         CROSS_INPUT_W::new(self, 16)
     }
     #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
     #[inline(always)]
-    #[must_use]
     pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP0_CTRL_LANE1_SPEC> {
         CROSS_RESULT_W::new(self, 17)
     }
     #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
     #[inline(always)]
-    #[must_use]
     pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP0_CTRL_LANE1_SPEC> {
         ADD_RAW_W::new(self, 18)
     }
     #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP0_CTRL_LANE1_SPEC> {
         FORCE_MSB_W::new(self, 19)
     }
diff --git a/src/inner/sio/interp1_accum0.rs b/src/inner/sio/interp1_accum0.rs
index a437aee..01218f5 100644
--- a/src/inner/sio/interp1_accum0.rs
+++ b/src/inner/sio/interp1_accum0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_accum0(&mut self) -> INTERP1_ACCUM0_W<INTERP1_ACCUM0_SPEC> {
         INTERP1_ACCUM0_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_accum0_add.rs b/src/inner/sio/interp1_accum0_add.rs
index 1d058bd..da5e981 100644
--- a/src/inner/sio/interp1_accum0_add.rs
+++ b/src/inner/sio/interp1_accum0_add.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_accum0_add(&mut self) -> INTERP1_ACCUM0_ADD_W<INTERP1_ACCUM0_ADD_SPEC> {
         INTERP1_ACCUM0_ADD_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_accum1.rs b/src/inner/sio/interp1_accum1.rs
index 609c1a8..0a219e7 100644
--- a/src/inner/sio/interp1_accum1.rs
+++ b/src/inner/sio/interp1_accum1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_accum1(&mut self) -> INTERP1_ACCUM1_W<INTERP1_ACCUM1_SPEC> {
         INTERP1_ACCUM1_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_accum1_add.rs b/src/inner/sio/interp1_accum1_add.rs
index 1a3ab99..7416194 100644
--- a/src/inner/sio/interp1_accum1_add.rs
+++ b/src/inner/sio/interp1_accum1_add.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_accum1_add(&mut self) -> INTERP1_ACCUM1_ADD_W<INTERP1_ACCUM1_ADD_SPEC> {
         INTERP1_ACCUM1_ADD_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_base0.rs b/src/inner/sio/interp1_base0.rs
index 171ec97..c21d2d0 100644
--- a/src/inner/sio/interp1_base0.rs
+++ b/src/inner/sio/interp1_base0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_base0(&mut self) -> INTERP1_BASE0_W<INTERP1_BASE0_SPEC> {
         INTERP1_BASE0_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_base1.rs b/src/inner/sio/interp1_base1.rs
index 950c845..f883eec 100644
--- a/src/inner/sio/interp1_base1.rs
+++ b/src/inner/sio/interp1_base1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_base1(&mut self) -> INTERP1_BASE1_W<INTERP1_BASE1_SPEC> {
         INTERP1_BASE1_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_base2.rs b/src/inner/sio/interp1_base2.rs
index 4292075..bd8ba28 100644
--- a/src/inner/sio/interp1_base2.rs
+++ b/src/inner/sio/interp1_base2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_base2(&mut self) -> INTERP1_BASE2_W<INTERP1_BASE2_SPEC> {
         INTERP1_BASE2_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_base_1and0.rs b/src/inner/sio/interp1_base_1and0.rs
index 737399e..6aa85b5 100644
--- a/src/inner/sio/interp1_base_1and0.rs
+++ b/src/inner/sio/interp1_base_1and0.rs
@@ -7,7 +7,6 @@ pub type INTERP1_BASE_1AND0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn interp1_base_1and0(&mut self) -> INTERP1_BASE_1AND0_W<INTERP1_BASE_1AND0_SPEC> {
         INTERP1_BASE_1AND0_W::new(self, 0)
     }
diff --git a/src/inner/sio/interp1_ctrl_lane0.rs b/src/inner/sio/interp1_ctrl_lane0.rs
index d001571..3834db8 100644
--- a/src/inner/sio/interp1_ctrl_lane0.rs
+++ b/src/inner/sio/interp1_ctrl_lane0.rs
@@ -10,9 +10,9 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 pub type MASK_LSB_R = crate::FieldReader;
 #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
 pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
-#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_R = crate::FieldReader;
-#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
 pub type SIGNED_R = crate::BitReader;
@@ -55,7 +55,7 @@ impl R {
     pub fn mask_lsb(&self) -> MASK_LSB_R {
         MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
     pub fn mask_msb(&self) -> MASK_MSB_R {
         MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
@@ -109,55 +109,46 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<INTERP1_CTRL_LANE0_SPEC> {
         SHIFT_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP1_CTRL_LANE0_SPEC> {
         MASK_LSB_W::new(self, 5)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP1_CTRL_LANE0_SPEC> {
         MASK_MSB_W::new(self, 10)
     }
     #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."]
     #[inline(always)]
-    #[must_use]
     pub fn signed(&mut self) -> SIGNED_W<INTERP1_CTRL_LANE0_SPEC> {
         SIGNED_W::new(self, 15)
     }
     #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
     #[inline(always)]
-    #[must_use]
     pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP1_CTRL_LANE0_SPEC> {
         CROSS_INPUT_W::new(self, 16)
     }
     #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
     #[inline(always)]
-    #[must_use]
     pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP1_CTRL_LANE0_SPEC> {
         CROSS_RESULT_W::new(self, 17)
     }
     #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."]
     #[inline(always)]
-    #[must_use]
     pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP1_CTRL_LANE0_SPEC> {
         ADD_RAW_W::new(self, 18)
     }
     #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP1_CTRL_LANE0_SPEC> {
         FORCE_MSB_W::new(self, 19)
     }
     #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"]
     #[inline(always)]
-    #[must_use]
     pub fn clamp(&mut self) -> CLAMP_W<INTERP1_CTRL_LANE0_SPEC> {
         CLAMP_W::new(self, 22)
     }
diff --git a/src/inner/sio/interp1_ctrl_lane1.rs b/src/inner/sio/interp1_ctrl_lane1.rs
index f79758f..7989604 100644
--- a/src/inner/sio/interp1_ctrl_lane1.rs
+++ b/src/inner/sio/interp1_ctrl_lane1.rs
@@ -10,9 +10,9 @@ pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 pub type MASK_LSB_R = crate::FieldReader;
 #[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"]
 pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
-#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_R = crate::FieldReader;
-#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
 pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 #[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
 pub type SIGNED_R = crate::BitReader;
@@ -45,7 +45,7 @@ impl R {
     pub fn mask_lsb(&self) -> MASK_LSB_R {
         MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
     pub fn mask_msb(&self) -> MASK_MSB_R {
         MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8)
@@ -79,49 +79,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."]
     #[inline(always)]
-    #[must_use]
     pub fn shift(&mut self) -> SHIFT_W<INTERP1_CTRL_LANE1_SPEC> {
         SHIFT_W::new(self, 0)
     }
     #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_lsb(&mut self) -> MASK_LSB_W<INTERP1_CTRL_LANE1_SPEC> {
         MASK_LSB_W::new(self, 5)
     }
-    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB &lt; LSB may cause chip to turn inside-out"]
+    #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"]
     #[inline(always)]
-    #[must_use]
     pub fn mask_msb(&mut self) -> MASK_MSB_W<INTERP1_CTRL_LANE1_SPEC> {
         MASK_MSB_W::new(self, 10)
     }
     #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."]
     #[inline(always)]
-    #[must_use]
     pub fn signed(&mut self) -> SIGNED_W<INTERP1_CTRL_LANE1_SPEC> {
         SIGNED_W::new(self, 15)
     }
     #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"]
     #[inline(always)]
-    #[must_use]
     pub fn cross_input(&mut self) -> CROSS_INPUT_W<INTERP1_CTRL_LANE1_SPEC> {
         CROSS_INPUT_W::new(self, 16)
     }
     #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."]
     #[inline(always)]
-    #[must_use]
     pub fn cross_result(&mut self) -> CROSS_RESULT_W<INTERP1_CTRL_LANE1_SPEC> {
         CROSS_RESULT_W::new(self, 17)
     }
     #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."]
     #[inline(always)]
-    #[must_use]
     pub fn add_raw(&mut self) -> ADD_RAW_W<INTERP1_CTRL_LANE1_SPEC> {
         ADD_RAW_W::new(self, 18)
     }
     #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn force_msb(&mut self) -> FORCE_MSB_W<INTERP1_CTRL_LANE1_SPEC> {
         FORCE_MSB_W::new(self, 19)
     }
diff --git a/src/inner/sio/mtime.rs b/src/inner/sio/mtime.rs
index 5c6d32f..c5cb169 100644
--- a/src/inner/sio/mtime.rs
+++ b/src/inner/sio/mtime.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn mtime(&mut self) -> MTIME_W<MTIME_SPEC> {
         MTIME_W::new(self, 0)
     }
diff --git a/src/inner/sio/mtime_ctrl.rs b/src/inner/sio/mtime_ctrl.rs
index 865162c..6c716f6 100644
--- a/src/inner/sio/mtime_ctrl.rs
+++ b/src/inner/sio/mtime_ctrl.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Timer enable bit. When 0, the timer will not increment automatically."]
     #[inline(always)]
-    #[must_use]
     pub fn en(&mut self) -> EN_W<MTIME_CTRL_SPEC> {
         EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."]
     #[inline(always)]
-    #[must_use]
     pub fn fullspeed(&mut self) -> FULLSPEED_W<MTIME_CTRL_SPEC> {
         FULLSPEED_W::new(self, 1)
     }
     #[doc = "Bit 2 - If 1, the timer pauses when core 0 is in the debug halt state."]
     #[inline(always)]
-    #[must_use]
     pub fn dbgpause_core0(&mut self) -> DBGPAUSE_CORE0_W<MTIME_CTRL_SPEC> {
         DBGPAUSE_CORE0_W::new(self, 2)
     }
     #[doc = "Bit 3 - If 1, the timer pauses when core 1 is in the debug halt state."]
     #[inline(always)]
-    #[must_use]
     pub fn dbgpause_core1(&mut self) -> DBGPAUSE_CORE1_W<MTIME_CTRL_SPEC> {
         DBGPAUSE_CORE1_W::new(self, 3)
     }
diff --git a/src/inner/sio/mtimecmp.rs b/src/inner/sio/mtimecmp.rs
index ac4b899..08503dc 100644
--- a/src/inner/sio/mtimecmp.rs
+++ b/src/inner/sio/mtimecmp.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn mtimecmp(&mut self) -> MTIMECMP_W<MTIMECMP_SPEC> {
         MTIMECMP_W::new(self, 0)
     }
diff --git a/src/inner/sio/mtimecmph.rs b/src/inner/sio/mtimecmph.rs
index 4c59178..9dbd7b6 100644
--- a/src/inner/sio/mtimecmph.rs
+++ b/src/inner/sio/mtimecmph.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn mtimecmph(&mut self) -> MTIMECMPH_W<MTIMECMPH_SPEC> {
         MTIMECMPH_W::new(self, 0)
     }
diff --git a/src/inner/sio/mtimeh.rs b/src/inner/sio/mtimeh.rs
index 239e3d1..1862534 100644
--- a/src/inner/sio/mtimeh.rs
+++ b/src/inner/sio/mtimeh.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn mtimeh(&mut self) -> MTIMEH_W<MTIMEH_SPEC> {
         MTIMEH_W::new(self, 0)
     }
diff --git a/src/inner/sio/peri_nonsec.rs b/src/inner/sio/peri_nonsec.rs
index 0869d3b..2abce1b 100644
--- a/src/inner/sio/peri_nonsec.rs
+++ b/src/inner/sio/peri_nonsec.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
     #[inline(always)]
-    #[must_use]
     pub fn interp0(&mut self) -> INTERP0_W<PERI_NONSEC_SPEC> {
         INTERP0_W::new(self, 0)
     }
     #[doc = "Bit 1 - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
     #[inline(always)]
-    #[must_use]
     pub fn interp1(&mut self) -> INTERP1_W<PERI_NONSEC_SPEC> {
         INTERP1_W::new(self, 1)
     }
     #[doc = "Bit 5 - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."]
     #[inline(always)]
-    #[must_use]
     pub fn tmds(&mut self) -> TMDS_W<PERI_NONSEC_SPEC> {
         TMDS_W::new(self, 5)
     }
diff --git a/src/inner/sio/riscv_softirq.rs b/src/inner/sio/riscv_softirq.rs
index c063070..51e2a14 100644
--- a/src/inner/sio/riscv_softirq.rs
+++ b/src/inner/sio/riscv_softirq.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_set(&mut self) -> CORE0_SET_W<RISCV_SOFTIRQ_SPEC> {
         CORE0_SET_W::new(self, 0)
     }
     #[doc = "Bit 1 - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_set(&mut self) -> CORE1_SET_W<RISCV_SOFTIRQ_SPEC> {
         CORE1_SET_W::new(self, 1)
     }
     #[doc = "Bit 8 - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."]
     #[inline(always)]
-    #[must_use]
     pub fn core0_clr(&mut self) -> CORE0_CLR_W<RISCV_SOFTIRQ_SPEC> {
         CORE0_CLR_W::new(self, 8)
     }
     #[doc = "Bit 9 - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."]
     #[inline(always)]
-    #[must_use]
     pub fn core1_clr(&mut self) -> CORE1_CLR_W<RISCV_SOFTIRQ_SPEC> {
         CORE1_CLR_W::new(self, 9)
     }
diff --git a/src/inner/sio/spinlock.rs b/src/inner/sio/spinlock.rs
index 06064dc..cdaedca 100644
--- a/src/inner/sio/spinlock.rs
+++ b/src/inner/sio/spinlock.rs
@@ -18,12 +18,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn spinlock0(&mut self) -> SPINLOCK0_W<SPINLOCK_SPEC> {
         SPINLOCK0_W::new(self, 0)
     }
 }
-#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 &lt;&lt; lock number.  
+#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.  
 
 You can [`read`](crate::Reg::read) this register and get [`spinlock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct SPINLOCK_SPEC;
diff --git a/src/inner/sio/tmds_ctrl.rs b/src/inner/sio/tmds_ctrl.rs
index 3ddcdef..aacf70f 100644
--- a/src/inner/sio/tmds_ctrl.rs
+++ b/src/inner/sio/tmds_ctrl.rs
@@ -200,61 +200,51 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."]
     #[inline(always)]
-    #[must_use]
     pub fn l0_rot(&mut self) -> L0_ROT_W<TMDS_CTRL_SPEC> {
         L0_ROT_W::new(self, 0)
     }
     #[doc = "Bits 4:7 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."]
     #[inline(always)]
-    #[must_use]
     pub fn l1_rot(&mut self) -> L1_ROT_W<TMDS_CTRL_SPEC> {
         L1_ROT_W::new(self, 4)
     }
     #[doc = "Bits 8:11 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."]
     #[inline(always)]
-    #[must_use]
     pub fn l2_rot(&mut self) -> L2_ROT_W<TMDS_CTRL_SPEC> {
         L2_ROT_W::new(self, 8)
     }
     #[doc = "Bits 12:14 - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
     #[inline(always)]
-    #[must_use]
     pub fn l0_nbits(&mut self) -> L0_NBITS_W<TMDS_CTRL_SPEC> {
         L0_NBITS_W::new(self, 12)
     }
     #[doc = "Bits 15:17 - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
     #[inline(always)]
-    #[must_use]
     pub fn l1_nbits(&mut self) -> L1_NBITS_W<TMDS_CTRL_SPEC> {
         L1_NBITS_W::new(self, 15)
     }
     #[doc = "Bits 18:20 - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."]
     #[inline(always)]
-    #[must_use]
     pub fn l2_nbits(&mut self) -> L2_NBITS_W<TMDS_CTRL_SPEC> {
         L2_NBITS_W::new(self, 18)
     }
     #[doc = "Bit 23 - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."]
     #[inline(always)]
-    #[must_use]
     pub fn interleave(&mut self) -> INTERLEAVE_W<TMDS_CTRL_SPEC> {
         INTERLEAVE_W::new(self, 23)
     }
     #[doc = "Bits 24:26 - Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"]
     #[inline(always)]
-    #[must_use]
     pub fn pix_shift(&mut self) -> PIX_SHIFT_W<TMDS_CTRL_SPEC> {
         PIX_SHIFT_W::new(self, 24)
     }
     #[doc = "Bit 27 - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."]
     #[inline(always)]
-    #[must_use]
     pub fn pix2_noshift(&mut self) -> PIX2_NOSHIFT_W<TMDS_CTRL_SPEC> {
         PIX2_NOSHIFT_W::new(self, 27)
     }
     #[doc = "Bit 28 - Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline."]
     #[inline(always)]
-    #[must_use]
     pub fn clear_balance(&mut self) -> CLEAR_BALANCE_W<TMDS_CTRL_SPEC> {
         CLEAR_BALANCE_W::new(self, 28)
     }
diff --git a/src/inner/sio/tmds_wdata.rs b/src/inner/sio/tmds_wdata.rs
index 40d957d..f3e25e4 100644
--- a/src/inner/sio/tmds_wdata.rs
+++ b/src/inner/sio/tmds_wdata.rs
@@ -7,7 +7,6 @@ pub type TMDS_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn tmds_wdata(&mut self) -> TMDS_WDATA_W<TMDS_WDATA_SPEC> {
         TMDS_WDATA_W::new(self, 0)
     }
diff --git a/src/inner/spi0/sspcpsr.rs b/src/inner/spi0/sspcpsr.rs
index a33fd13..7c32e28 100644
--- a/src/inner/spi0/sspcpsr.rs
+++ b/src/inner/spi0/sspcpsr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."]
     #[inline(always)]
-    #[must_use]
     pub fn cpsdvsr(&mut self) -> CPSDVSR_W<SSPCPSR_SPEC> {
         CPSDVSR_W::new(self, 0)
     }
diff --git a/src/inner/spi0/sspcr0.rs b/src/inner/spi0/sspcr0.rs
index af346a6..8e08bfe 100644
--- a/src/inner/spi0/sspcr0.rs
+++ b/src/inner/spi0/sspcr0.rs
@@ -123,31 +123,26 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."]
     #[inline(always)]
-    #[must_use]
     pub fn dss(&mut self) -> DSS_W<SSPCR0_SPEC> {
         DSS_W::new(self, 0)
     }
     #[doc = "Bits 4:5 - Frame format."]
     #[inline(always)]
-    #[must_use]
     pub fn frf(&mut self) -> FRF_W<SSPCR0_SPEC> {
         FRF_W::new(self, 4)
     }
     #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."]
     #[inline(always)]
-    #[must_use]
     pub fn spo(&mut self) -> SPO_W<SSPCR0_SPEC> {
         SPO_W::new(self, 6)
     }
     #[doc = "Bit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."]
     #[inline(always)]
-    #[must_use]
     pub fn sph(&mut self) -> SPH_W<SSPCR0_SPEC> {
         SPH_W::new(self, 7)
     }
     #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."]
     #[inline(always)]
-    #[must_use]
     pub fn scr(&mut self) -> SCR_W<SSPCR0_SPEC> {
         SCR_W::new(self, 8)
     }
diff --git a/src/inner/spi0/sspcr1.rs b/src/inner/spi0/sspcr1.rs
index 83310a0..fa186d9 100644
--- a/src/inner/spi0/sspcr1.rs
+++ b/src/inner/spi0/sspcr1.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."]
     #[inline(always)]
-    #[must_use]
     pub fn lbm(&mut self) -> LBM_W<SSPCR1_SPEC> {
         LBM_W::new(self, 0)
     }
     #[doc = "Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn sse(&mut self) -> SSE_W<SSPCR1_SPEC> {
         SSE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."]
     #[inline(always)]
-    #[must_use]
     pub fn ms(&mut self) -> MS_W<SSPCR1_SPEC> {
         MS_W::new(self, 2)
     }
     #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."]
     #[inline(always)]
-    #[must_use]
     pub fn sod(&mut self) -> SOD_W<SSPCR1_SPEC> {
         SOD_W::new(self, 3)
     }
diff --git a/src/inner/spi0/sspdmacr.rs b/src/inner/spi0/sspdmacr.rs
index 6ce7ceb..c10c796 100644
--- a/src/inner/spi0/sspdmacr.rs
+++ b/src/inner/spi0/sspdmacr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rxdmae(&mut self) -> RXDMAE_W<SSPDMACR_SPEC> {
         RXDMAE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn txdmae(&mut self) -> TXDMAE_W<SSPDMACR_SPEC> {
         TXDMAE_W::new(self, 1)
     }
diff --git a/src/inner/spi0/sspdr.rs b/src/inner/spi0/sspdr.rs
index 008054a..e5fed89 100644
--- a/src/inner/spi0/sspdr.rs
+++ b/src/inner/spi0/sspdr.rs
@@ -18,7 +18,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<SSPDR_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/src/inner/spi0/sspicr.rs b/src/inner/spi0/sspicr.rs
index 68fd651..48cd23f 100644
--- a/src/inner/spi0/sspicr.rs
+++ b/src/inner/spi0/sspicr.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn roric(&mut self) -> RORIC_W<SSPICR_SPEC> {
         RORIC_W::new(self, 0)
     }
     #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"]
     #[inline(always)]
-    #[must_use]
     pub fn rtic(&mut self) -> RTIC_W<SSPICR_SPEC> {
         RTIC_W::new(self, 1)
     }
diff --git a/src/inner/spi0/sspimsc.rs b/src/inner/spi0/sspimsc.rs
index 230de5c..25aa8ce 100644
--- a/src/inner/spi0/sspimsc.rs
+++ b/src/inner/spi0/sspimsc.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn rorim(&mut self) -> RORIM_W<SSPIMSC_SPEC> {
         RORIM_W::new(self, 0)
     }
     #[doc = "Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn rtim(&mut self) -> RTIM_W<SSPIMSC_SPEC> {
         RTIM_W::new(self, 1)
     }
     #[doc = "Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn rxim(&mut self) -> RXIM_W<SSPIMSC_SPEC> {
         RXIM_W::new(self, 2)
     }
     #[doc = "Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."]
     #[inline(always)]
-    #[must_use]
     pub fn txim(&mut self) -> TXIM_W<SSPIMSC_SPEC> {
         TXIM_W::new(self, 3)
     }
diff --git a/src/inner/syscfg/auxctrl.rs b/src/inner/syscfg/auxctrl.rs
index 93c47aa..d64c1de 100644
--- a/src/inner/syscfg/auxctrl.rs
+++ b/src/inner/syscfg/auxctrl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."]
     #[inline(always)]
-    #[must_use]
     pub fn auxctrl(&mut self) -> AUXCTRL_W<AUXCTRL_SPEC> {
         AUXCTRL_W::new(self, 0)
     }
diff --git a/src/inner/syscfg/dbgforce.rs b/src/inner/syscfg/dbgforce.rs
index 771b0b0..bdeaae9 100644
--- a/src/inner/syscfg/dbgforce.rs
+++ b/src/inner/syscfg/dbgforce.rs
@@ -41,19 +41,16 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Directly drive SWDIO input, if ATTACH is set"]
     #[inline(always)]
-    #[must_use]
     pub fn swdi(&mut self) -> SWDI_W<DBGFORCE_SPEC> {
         SWDI_W::new(self, 1)
     }
     #[doc = "Bit 2 - Directly drive SWCLK, if ATTACH is set"]
     #[inline(always)]
-    #[must_use]
     pub fn swclk(&mut self) -> SWCLK_W<DBGFORCE_SPEC> {
         SWCLK_W::new(self, 2)
     }
     #[doc = "Bit 3 - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."]
     #[inline(always)]
-    #[must_use]
     pub fn attach(&mut self) -> ATTACH_W<DBGFORCE_SPEC> {
         ATTACH_W::new(self, 3)
     }
diff --git a/src/inner/syscfg/mempowerdown.rs b/src/inner/syscfg/mempowerdown.rs
index 47d7927..49d72fc 100644
--- a/src/inner/syscfg/mempowerdown.rs
+++ b/src/inner/syscfg/mempowerdown.rs
@@ -124,79 +124,66 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn sram0(&mut self) -> SRAM0_W<MEMPOWERDOWN_SPEC> {
         SRAM0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn sram1(&mut self) -> SRAM1_W<MEMPOWERDOWN_SPEC> {
         SRAM1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn sram2(&mut self) -> SRAM2_W<MEMPOWERDOWN_SPEC> {
         SRAM2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn sram3(&mut self) -> SRAM3_W<MEMPOWERDOWN_SPEC> {
         SRAM3_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn sram4(&mut self) -> SRAM4_W<MEMPOWERDOWN_SPEC> {
         SRAM4_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn sram5(&mut self) -> SRAM5_W<MEMPOWERDOWN_SPEC> {
         SRAM5_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn sram6(&mut self) -> SRAM6_W<MEMPOWERDOWN_SPEC> {
         SRAM6_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn sram7(&mut self) -> SRAM7_W<MEMPOWERDOWN_SPEC> {
         SRAM7_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn sram8(&mut self) -> SRAM8_W<MEMPOWERDOWN_SPEC> {
         SRAM8_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn sram9(&mut self) -> SRAM9_W<MEMPOWERDOWN_SPEC> {
         SRAM9_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn usb(&mut self) -> USB_W<MEMPOWERDOWN_SPEC> {
         USB_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn rom(&mut self) -> ROM_W<MEMPOWERDOWN_SPEC> {
         ROM_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn bootram(&mut self) -> BOOTRAM_W<MEMPOWERDOWN_SPEC> {
         BOOTRAM_W::new(self, 12)
     }
diff --git a/src/inner/syscfg/proc_in_sync_bypass.rs b/src/inner/syscfg/proc_in_sync_bypass.rs
index 44e7ff5..8c3658b 100644
--- a/src/inner/syscfg/proc_in_sync_bypass.rs
+++ b/src/inner/syscfg/proc_in_sync_bypass.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<PROC_IN_SYNC_BYPASS_SPEC> {
         GPIO_W::new(self, 0)
     }
diff --git a/src/inner/syscfg/proc_in_sync_bypass_hi.rs b/src/inner/syscfg/proc_in_sync_bypass_hi.rs
index ec7a2dd..cf29f2a 100644
--- a/src/inner/syscfg/proc_in_sync_bypass_hi.rs
+++ b/src/inner/syscfg/proc_in_sync_bypass_hi.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn gpio(&mut self) -> GPIO_W<PROC_IN_SYNC_BYPASS_HI_SPEC> {
         GPIO_W::new(self, 0)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dp(&mut self) -> USB_DP_W<PROC_IN_SYNC_BYPASS_HI_SPEC> {
         USB_DP_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn usb_dm(&mut self) -> USB_DM_W<PROC_IN_SYNC_BYPASS_HI_SPEC> {
         USB_DM_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sck(&mut self) -> QSPI_SCK_W<PROC_IN_SYNC_BYPASS_HI_SPEC> {
         QSPI_SCK_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_csn(&mut self) -> QSPI_CSN_W<PROC_IN_SYNC_BYPASS_HI_SPEC> {
         QSPI_CSN_W::new(self, 27)
     }
     #[doc = "Bits 28:31"]
     #[inline(always)]
-    #[must_use]
     pub fn qspi_sd(&mut self) -> QSPI_SD_W<PROC_IN_SYNC_BYPASS_HI_SPEC> {
         QSPI_SD_W::new(self, 28)
     }
diff --git a/src/inner/ticks.rs b/src/inner/ticks.rs
index 8183870..a849187 100644
--- a/src/inner/ticks.rs
+++ b/src/inner/ticks.rs
@@ -5,6 +5,8 @@ pub struct RegisterBlock {
 }
 impl RegisterBlock {
     #[doc = "0x00..0x48 - Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT"]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of cluster in the array. `n == 0` corresponds to `TICKPROC0` cluster.</div>"]
     #[inline(always)]
     pub const fn tick(&self, n: usize) -> &TICK {
         &self.tick[n]
diff --git a/src/inner/ticks/tick/ctrl.rs b/src/inner/ticks/tick/ctrl.rs
index 5d4a884..4ac24a3 100644
--- a/src/inner/ticks/tick/ctrl.rs
+++ b/src/inner/ticks/tick/ctrl.rs
@@ -23,7 +23,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - start / stop tick generation"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CTRL_SPEC> {
         ENABLE_W::new(self, 0)
     }
diff --git a/src/inner/ticks/tick/cycles.rs b/src/inner/ticks/tick/cycles.rs
index 474ab18..167641f 100644
--- a/src/inner/ticks/tick/cycles.rs
+++ b/src/inner/ticks/tick/cycles.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:8 - Total number of clk_tick cycles before the next tick."]
     #[inline(always)]
-    #[must_use]
     pub fn proc0_cycles(&mut self) -> PROC0_CYCLES_W<CYCLES_SPEC> {
         PROC0_CYCLES_W::new(self, 0)
     }
diff --git a/src/inner/timer0.rs b/src/inner/timer0.rs
index 355646b..8089360 100644
--- a/src/inner/timer0.rs
+++ b/src/inner/timer0.rs
@@ -112,7 +112,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0x48 - Interrupt status after masking &amp; forcing"]
+    #[doc = "0x48 - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -280,12 +280,12 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
diff --git a/src/inner/timer0/alarm0.rs b/src/inner/timer0/alarm0.rs
index 9ff99b3..3cc2cb9 100644
--- a/src/inner/timer0/alarm0.rs
+++ b/src/inner/timer0/alarm0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm0(&mut self) -> ALARM0_W<ALARM0_SPEC> {
         ALARM0_W::new(self, 0)
     }
diff --git a/src/inner/timer0/alarm1.rs b/src/inner/timer0/alarm1.rs
index ea3f943..c46d4e0 100644
--- a/src/inner/timer0/alarm1.rs
+++ b/src/inner/timer0/alarm1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm1(&mut self) -> ALARM1_W<ALARM1_SPEC> {
         ALARM1_W::new(self, 0)
     }
diff --git a/src/inner/timer0/alarm2.rs b/src/inner/timer0/alarm2.rs
index 415e64e..1c40e8d 100644
--- a/src/inner/timer0/alarm2.rs
+++ b/src/inner/timer0/alarm2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm2(&mut self) -> ALARM2_W<ALARM2_SPEC> {
         ALARM2_W::new(self, 0)
     }
diff --git a/src/inner/timer0/alarm3.rs b/src/inner/timer0/alarm3.rs
index 35d9405..4d5a504 100644
--- a/src/inner/timer0/alarm3.rs
+++ b/src/inner/timer0/alarm3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm3(&mut self) -> ALARM3_W<ALARM3_SPEC> {
         ALARM3_W::new(self, 0)
     }
diff --git a/src/inner/timer0/armed.rs b/src/inner/timer0/armed.rs
index 826edbf..a33447b 100644
--- a/src/inner/timer0/armed.rs
+++ b/src/inner/timer0/armed.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:3"]
     #[inline(always)]
-    #[must_use]
     pub fn armed(&mut self) -> ARMED_W<ARMED_SPEC> {
         ARMED_W::new(self, 0)
     }
diff --git a/src/inner/timer0/dbgpause.rs b/src/inner/timer0/dbgpause.rs
index 297ed69..93f2c4d 100644
--- a/src/inner/timer0/dbgpause.rs
+++ b/src/inner/timer0/dbgpause.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 1 - Pause when processor 0 is in debug mode"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg0(&mut self) -> DBG0_W<DBGPAUSE_SPEC> {
         DBG0_W::new(self, 1)
     }
     #[doc = "Bit 2 - Pause when processor 1 is in debug mode"]
     #[inline(always)]
-    #[must_use]
     pub fn dbg1(&mut self) -> DBG1_W<DBGPAUSE_SPEC> {
         DBG1_W::new(self, 2)
     }
diff --git a/src/inner/timer0/inte.rs b/src/inner/timer0/inte.rs
index d219e79..7be8d33 100644
--- a/src/inner/timer0/inte.rs
+++ b/src/inner/timer0/inte.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_0(&mut self) -> ALARM_0_W<INTE_SPEC> {
         ALARM_0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_1(&mut self) -> ALARM_1_W<INTE_SPEC> {
         ALARM_1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_2(&mut self) -> ALARM_2_W<INTE_SPEC> {
         ALARM_2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_3(&mut self) -> ALARM_3_W<INTE_SPEC> {
         ALARM_3_W::new(self, 3)
     }
diff --git a/src/inner/timer0/intf.rs b/src/inner/timer0/intf.rs
index 7ab273d..bebef7c 100644
--- a/src/inner/timer0/intf.rs
+++ b/src/inner/timer0/intf.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_0(&mut self) -> ALARM_0_W<INTF_SPEC> {
         ALARM_0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_1(&mut self) -> ALARM_1_W<INTF_SPEC> {
         ALARM_1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_2(&mut self) -> ALARM_2_W<INTF_SPEC> {
         ALARM_2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_3(&mut self) -> ALARM_3_W<INTF_SPEC> {
         ALARM_3_W::new(self, 3)
     }
diff --git a/src/inner/timer0/intr.rs b/src/inner/timer0/intr.rs
index 58e42f8..9b61d69 100644
--- a/src/inner/timer0/intr.rs
+++ b/src/inner/timer0/intr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_0(&mut self) -> ALARM_0_W<INTR_SPEC> {
         ALARM_0_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_1(&mut self) -> ALARM_1_W<INTR_SPEC> {
         ALARM_1_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_2(&mut self) -> ALARM_2_W<INTR_SPEC> {
         ALARM_2_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn alarm_3(&mut self) -> ALARM_3_W<INTR_SPEC> {
         ALARM_3_W::new(self, 3)
     }
diff --git a/src/inner/timer0/ints.rs b/src/inner/timer0/ints.rs
index a6411e0..fa8ff7e 100644
--- a/src/inner/timer0/ints.rs
+++ b/src/inner/timer0/ints.rs
@@ -33,7 +33,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/timer0/locked.rs b/src/inner/timer0/locked.rs
index 9a1dfb5..7e5c6ae 100644
--- a/src/inner/timer0/locked.rs
+++ b/src/inner/timer0/locked.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn locked(&mut self) -> LOCKED_W<LOCKED_SPEC> {
         LOCKED_W::new(self, 0)
     }
diff --git a/src/inner/timer0/pause.rs b/src/inner/timer0/pause.rs
index 1a466e2..0e84686 100644
--- a/src/inner/timer0/pause.rs
+++ b/src/inner/timer0/pause.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn pause(&mut self) -> PAUSE_W<PAUSE_SPEC> {
         PAUSE_W::new(self, 0)
     }
diff --git a/src/inner/timer0/source.rs b/src/inner/timer0/source.rs
index bdc3fe3..b983b75 100644
--- a/src/inner/timer0/source.rs
+++ b/src/inner/timer0/source.rs
@@ -67,7 +67,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn clk_sys(&mut self) -> CLK_SYS_W<SOURCE_SPEC> {
         CLK_SYS_W::new(self, 0)
     }
diff --git a/src/inner/timer0/timehw.rs b/src/inner/timer0/timehw.rs
index 616a9a4..c2404c8 100644
--- a/src/inner/timer0/timehw.rs
+++ b/src/inner/timer0/timehw.rs
@@ -7,7 +7,6 @@ pub type TIMEHW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn timehw(&mut self) -> TIMEHW_W<TIMEHW_SPEC> {
         TIMEHW_W::new(self, 0)
     }
diff --git a/src/inner/timer0/timelw.rs b/src/inner/timer0/timelw.rs
index 264b16e..36157c3 100644
--- a/src/inner/timer0/timelw.rs
+++ b/src/inner/timer0/timelw.rs
@@ -7,7 +7,6 @@ pub type TIMELW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn timelw(&mut self) -> TIMELW_W<TIMELW_SPEC> {
         TIMELW_W::new(self, 0)
     }
diff --git a/src/inner/trng/autocorr_statistic.rs b/src/inner/trng/autocorr_statistic.rs
index 8d2244e..f253f9f 100644
--- a/src/inner/trng/autocorr_statistic.rs
+++ b/src/inner/trng/autocorr_statistic.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:13 - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."]
     #[inline(always)]
-    #[must_use]
     pub fn autocorr_trys(&mut self) -> AUTOCORR_TRYS_W<AUTOCORR_STATISTIC_SPEC> {
         AUTOCORR_TRYS_W::new(self, 0)
     }
     #[doc = "Bits 14:21 - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."]
     #[inline(always)]
-    #[must_use]
     pub fn autocorr_fails(&mut self) -> AUTOCORR_FAILS_W<AUTOCORR_STATISTIC_SPEC> {
         AUTOCORR_FAILS_W::new(self, 14)
     }
diff --git a/src/inner/trng/rnd_source_enable.rs b/src/inner/trng/rnd_source_enable.rs
index 605e260..b74a179 100644
--- a/src/inner/trng/rnd_source_enable.rs
+++ b/src/inner/trng/rnd_source_enable.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn rnd_src_en(&mut self) -> RND_SRC_EN_W<RND_SOURCE_ENABLE_SPEC> {
         RND_SRC_EN_W::new(self, 0)
     }
diff --git a/src/inner/trng/rng_debug_en_input.rs b/src/inner/trng/rng_debug_en_input.rs
index e9b7c3e..caac752 100644
--- a/src/inner/trng/rng_debug_en_input.rs
+++ b/src/inner/trng/rng_debug_en_input.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"]
     #[inline(always)]
-    #[must_use]
     pub fn rng_debug_en(&mut self) -> RNG_DEBUG_EN_W<RNG_DEBUG_EN_INPUT_SPEC> {
         RNG_DEBUG_EN_W::new(self, 0)
     }
diff --git a/src/inner/trng/rng_icr.rs b/src/inner/trng/rng_icr.rs
index e7c9518..083f35a 100644
--- a/src/inner/trng/rng_icr.rs
+++ b/src/inner/trng/rng_icr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Write 1'b1 - clear corresponding bit in RNG_ISR."]
     #[inline(always)]
-    #[must_use]
     pub fn ehr_valid(&mut self) -> EHR_VALID_W<RNG_ICR_SPEC> {
         EHR_VALID_W::new(self, 0)
     }
     #[doc = "Bit 1 - Cannot be cleared by SW! Only RNG reset clears this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn autocorr_err(&mut self) -> AUTOCORR_ERR_W<RNG_ICR_SPEC> {
         AUTOCORR_ERR_W::new(self, 1)
     }
     #[doc = "Bit 2 - Write 1'b1 - clear corresponding bit in RNG_ISR."]
     #[inline(always)]
-    #[must_use]
     pub fn crngt_err(&mut self) -> CRNGT_ERR_W<RNG_ICR_SPEC> {
         CRNGT_ERR_W::new(self, 2)
     }
     #[doc = "Bit 3 - Write 1'b1 - clear corresponding bit in RNG_ISR."]
     #[inline(always)]
-    #[must_use]
     pub fn vn_err(&mut self) -> VN_ERR_W<RNG_ICR_SPEC> {
         VN_ERR_W::new(self, 3)
     }
diff --git a/src/inner/trng/rng_imr.rs b/src/inner/trng/rng_imr.rs
index 2a69ece..738e715 100644
--- a/src/inner/trng/rng_imr.rs
+++ b/src/inner/trng/rng_imr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ehr_valid_int_mask(&mut self) -> EHR_VALID_INT_MASK_W<RNG_IMR_SPEC> {
         EHR_VALID_INT_MASK_W::new(self, 0)
     }
     #[doc = "Bit 1 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn autocorr_err_int_mask(&mut self) -> AUTOCORR_ERR_INT_MASK_W<RNG_IMR_SPEC> {
         AUTOCORR_ERR_INT_MASK_W::new(self, 1)
     }
     #[doc = "Bit 2 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn crngt_err_int_mask(&mut self) -> CRNGT_ERR_INT_MASK_W<RNG_IMR_SPEC> {
         CRNGT_ERR_INT_MASK_W::new(self, 2)
     }
     #[doc = "Bit 3 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn vn_err_int_mask(&mut self) -> VN_ERR_INT_MASK_W<RNG_IMR_SPEC> {
         VN_ERR_INT_MASK_W::new(self, 3)
     }
diff --git a/src/inner/trng/rst_bits_counter.rs b/src/inner/trng/rst_bits_counter.rs
index ce7cfe5..290bf8f 100644
--- a/src/inner/trng/rst_bits_counter.rs
+++ b/src/inner/trng/rst_bits_counter.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."]
     #[inline(always)]
-    #[must_use]
     pub fn rst_bits_counter(&mut self) -> RST_BITS_COUNTER_W<RST_BITS_COUNTER_SPEC> {
         RST_BITS_COUNTER_W::new(self, 0)
     }
diff --git a/src/inner/trng/sample_cnt1.rs b/src/inner/trng/sample_cnt1.rs
index 9e7538c..096083b 100644
--- a/src/inner/trng/sample_cnt1.rs
+++ b/src/inner/trng/sample_cnt1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen"]
     #[inline(always)]
-    #[must_use]
     pub fn sample_cntr1(&mut self) -> SAMPLE_CNTR1_W<SAMPLE_CNT1_SPEC> {
         SAMPLE_CNTR1_W::new(self, 0)
     }
diff --git a/src/inner/trng/trng_config.rs b/src/inner/trng/trng_config.rs
index 21b0bf3..10b4b98 100644
--- a/src/inner/trng/trng_config.rs
+++ b/src/inner/trng/trng_config.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."]
     #[inline(always)]
-    #[must_use]
     pub fn rnd_src_sel(&mut self) -> RND_SRC_SEL_W<TRNG_CONFIG_SPEC> {
         RND_SRC_SEL_W::new(self, 0)
     }
diff --git a/src/inner/trng/trng_debug_control.rs b/src/inner/trng/trng_debug_control.rs
index b7d2bea..d39ffd9 100644
--- a/src/inner/trng/trng_debug_control.rs
+++ b/src/inner/trng/trng_debug_control.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 1 - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."]
     #[inline(always)]
-    #[must_use]
     pub fn vnc_bypass(&mut self) -> VNC_BYPASS_W<TRNG_DEBUG_CONTROL_SPEC> {
         VNC_BYPASS_W::new(self, 1)
     }
     #[doc = "Bit 2 - When set, the CRNGT test in the RNG is bypassed."]
     #[inline(always)]
-    #[must_use]
     pub fn trng_crngt_bypass(&mut self) -> TRNG_CRNGT_BYPASS_W<TRNG_DEBUG_CONTROL_SPEC> {
         TRNG_CRNGT_BYPASS_W::new(self, 2)
     }
     #[doc = "Bit 3 - When set, the autocorrelation test in the TRNG module is bypassed."]
     #[inline(always)]
-    #[must_use]
     pub fn auto_correlate_bypass(&mut self) -> AUTO_CORRELATE_BYPASS_W<TRNG_DEBUG_CONTROL_SPEC> {
         AUTO_CORRELATE_BYPASS_W::new(self, 3)
     }
diff --git a/src/inner/trng/trng_sw_reset.rs b/src/inner/trng/trng_sw_reset.rs
index 6f704aa..7911a38 100644
--- a/src/inner/trng/trng_sw_reset.rs
+++ b/src/inner/trng/trng_sw_reset.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Writing 1'b1 to this register causes an internal RNG reset."]
     #[inline(always)]
-    #[must_use]
     pub fn trng_sw_reset(&mut self) -> TRNG_SW_RESET_W<TRNG_SW_RESET_SPEC> {
         TRNG_SW_RESET_W::new(self, 0)
     }
diff --git a/src/inner/uart0/uartcr.rs b/src/inner/uart0/uartcr.rs
index 0fa9e03..1dd55b6 100644
--- a/src/inner/uart0/uartcr.rs
+++ b/src/inner/uart0/uartcr.rs
@@ -115,73 +115,61 @@ impl R {
 impl W {
     #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
     #[inline(always)]
-    #[must_use]
     pub fn uarten(&mut self) -> UARTEN_W<UARTCR_SPEC> {
         UARTEN_W::new(self, 0)
     }
     #[doc = "Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."]
     #[inline(always)]
-    #[must_use]
     pub fn siren(&mut self) -> SIREN_W<UARTCR_SPEC> {
         SIREN_W::new(self, 1)
     }
     #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
     #[inline(always)]
-    #[must_use]
     pub fn sirlp(&mut self) -> SIRLP_W<UARTCR_SPEC> {
         SIRLP_W::new(self, 2)
     }
     #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
     #[inline(always)]
-    #[must_use]
     pub fn lbe(&mut self) -> LBE_W<UARTCR_SPEC> {
         LBE_W::new(self, 7)
     }
     #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
     #[inline(always)]
-    #[must_use]
     pub fn txe(&mut self) -> TXE_W<UARTCR_SPEC> {
         TXE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
     #[inline(always)]
-    #[must_use]
     pub fn rxe(&mut self) -> RXE_W<UARTCR_SPEC> {
         RXE_W::new(self, 9)
     }
     #[doc = "Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."]
     #[inline(always)]
-    #[must_use]
     pub fn dtr(&mut self) -> DTR_W<UARTCR_SPEC> {
         DTR_W::new(self, 10)
     }
     #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
     #[inline(always)]
-    #[must_use]
     pub fn rts(&mut self) -> RTS_W<UARTCR_SPEC> {
         RTS_W::new(self, 11)
     }
     #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
     #[inline(always)]
-    #[must_use]
     pub fn out1(&mut self) -> OUT1_W<UARTCR_SPEC> {
         OUT1_W::new(self, 12)
     }
     #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
     #[inline(always)]
-    #[must_use]
     pub fn out2(&mut self) -> OUT2_W<UARTCR_SPEC> {
         OUT2_W::new(self, 13)
     }
     #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
     #[inline(always)]
-    #[must_use]
     pub fn rtsen(&mut self) -> RTSEN_W<UARTCR_SPEC> {
         RTSEN_W::new(self, 14)
     }
     #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
     #[inline(always)]
-    #[must_use]
     pub fn ctsen(&mut self) -> CTSEN_W<UARTCR_SPEC> {
         CTSEN_W::new(self, 15)
     }
diff --git a/src/inner/uart0/uartdmacr.rs b/src/inner/uart0/uartdmacr.rs
index 7540239..3894298 100644
--- a/src/inner/uart0/uartdmacr.rs
+++ b/src/inner/uart0/uartdmacr.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn rxdmae(&mut self) -> RXDMAE_W<UARTDMACR_SPEC> {
         RXDMAE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn txdmae(&mut self) -> TXDMAE_W<UARTDMACR_SPEC> {
         TXDMAE_W::new(self, 1)
     }
     #[doc = "Bit 2 - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."]
     #[inline(always)]
-    #[must_use]
     pub fn dmaonerr(&mut self) -> DMAONERR_W<UARTDMACR_SPEC> {
         DMAONERR_W::new(self, 2)
     }
diff --git a/src/inner/uart0/uartdr.rs b/src/inner/uart0/uartdr.rs
index d5bf81c..e015347 100644
--- a/src/inner/uart0/uartdr.rs
+++ b/src/inner/uart0/uartdr.rs
@@ -46,7 +46,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Receive (read) data character. Transmit (write) data character."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<UARTDR_SPEC> {
         DATA_W::new(self, 0)
     }
diff --git a/src/inner/uart0/uartfbrd.rs b/src/inner/uart0/uartfbrd.rs
index 535f80b..220e802 100644
--- a/src/inner/uart0/uartfbrd.rs
+++ b/src/inner/uart0/uartfbrd.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset."]
     #[inline(always)]
-    #[must_use]
     pub fn baud_divfrac(&mut self) -> BAUD_DIVFRAC_W<UARTFBRD_SPEC> {
         BAUD_DIVFRAC_W::new(self, 0)
     }
diff --git a/src/inner/uart0/uartibrd.rs b/src/inner/uart0/uartibrd.rs
index c3f86fe..6312be0 100644
--- a/src/inner/uart0/uartibrd.rs
+++ b/src/inner/uart0/uartibrd.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset."]
     #[inline(always)]
-    #[must_use]
     pub fn baud_divint(&mut self) -> BAUD_DIVINT_W<UARTIBRD_SPEC> {
         BAUD_DIVINT_W::new(self, 0)
     }
diff --git a/src/inner/uart0/uarticr.rs b/src/inner/uart0/uarticr.rs
index 8bfb38b..53d88ad 100644
--- a/src/inner/uart0/uarticr.rs
+++ b/src/inner/uart0/uarticr.rs
@@ -106,67 +106,56 @@ impl R {
 impl W {
     #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rimic(&mut self) -> RIMIC_W<UARTICR_SPEC> {
         RIMIC_W::new(self, 0)
     }
     #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn ctsmic(&mut self) -> CTSMIC_W<UARTICR_SPEC> {
         CTSMIC_W::new(self, 1)
     }
     #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dcdmic(&mut self) -> DCDMIC_W<UARTICR_SPEC> {
         DCDMIC_W::new(self, 2)
     }
     #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn dsrmic(&mut self) -> DSRMIC_W<UARTICR_SPEC> {
         DSRMIC_W::new(self, 3)
     }
     #[doc = "Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rxic(&mut self) -> RXIC_W<UARTICR_SPEC> {
         RXIC_W::new(self, 4)
     }
     #[doc = "Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn txic(&mut self) -> TXIC_W<UARTICR_SPEC> {
         TXIC_W::new(self, 5)
     }
     #[doc = "Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn rtic(&mut self) -> RTIC_W<UARTICR_SPEC> {
         RTIC_W::new(self, 6)
     }
     #[doc = "Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn feic(&mut self) -> FEIC_W<UARTICR_SPEC> {
         FEIC_W::new(self, 7)
     }
     #[doc = "Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn peic(&mut self) -> PEIC_W<UARTICR_SPEC> {
         PEIC_W::new(self, 8)
     }
     #[doc = "Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn beic(&mut self) -> BEIC_W<UARTICR_SPEC> {
         BEIC_W::new(self, 9)
     }
     #[doc = "Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."]
     #[inline(always)]
-    #[must_use]
     pub fn oeic(&mut self) -> OEIC_W<UARTICR_SPEC> {
         OEIC_W::new(self, 10)
     }
diff --git a/src/inner/uart0/uartifls.rs b/src/inner/uart0/uartifls.rs
index ce1621d..869420f 100644
--- a/src/inner/uart0/uartifls.rs
+++ b/src/inner/uart0/uartifls.rs
@@ -2,16 +2,16 @@
 pub type R = crate::R<UARTIFLS_SPEC>;
 #[doc = "Register `UARTIFLS` writer"]
 pub type W = crate::W<UARTIFLS_SPEC>;
-#[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
+#[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."]
 pub type TXIFLSEL_R = crate::FieldReader;
-#[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
+#[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."]
 pub type TXIFLSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
 #[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
 pub type RXIFLSEL_R = crate::FieldReader;
 #[doc = "Field `RXIFLSEL` writer - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
 pub type RXIFLSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
 impl R {
-    #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
+    #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."]
     #[inline(always)]
     pub fn txiflsel(&self) -> TXIFLSEL_R {
         TXIFLSEL_R::new((self.bits & 7) as u8)
@@ -23,15 +23,13 @@ impl R {
     }
 }
 impl W {
-    #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes &lt;= 1 / 8 full b001 = Transmit FIFO becomes &lt;= 1 / 4 full b010 = Transmit FIFO becomes &lt;= 1 / 2 full b011 = Transmit FIFO becomes &lt;= 3 / 4 full b100 = Transmit FIFO becomes &lt;= 7 / 8 full b101-b111 = reserved."]
+    #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn txiflsel(&mut self) -> TXIFLSEL_W<UARTIFLS_SPEC> {
         TXIFLSEL_W::new(self, 0)
     }
     #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."]
     #[inline(always)]
-    #[must_use]
     pub fn rxiflsel(&mut self) -> RXIFLSEL_W<UARTIFLS_SPEC> {
         RXIFLSEL_W::new(self, 3)
     }
diff --git a/src/inner/uart0/uartilpr.rs b/src/inner/uart0/uartilpr.rs
index a45bd41..dace5b0 100644
--- a/src/inner/uart0/uartilpr.rs
+++ b/src/inner/uart0/uartilpr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset."]
     #[inline(always)]
-    #[must_use]
     pub fn ilpdvsr(&mut self) -> ILPDVSR_W<UARTILPR_SPEC> {
         ILPDVSR_W::new(self, 0)
     }
diff --git a/src/inner/uart0/uartimsc.rs b/src/inner/uart0/uartimsc.rs
index 3b79a43..7418481 100644
--- a/src/inner/uart0/uartimsc.rs
+++ b/src/inner/uart0/uartimsc.rs
@@ -106,67 +106,56 @@ impl R {
 impl W {
     #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn rimim(&mut self) -> RIMIM_W<UARTIMSC_SPEC> {
         RIMIM_W::new(self, 0)
     }
     #[doc = "Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn ctsmim(&mut self) -> CTSMIM_W<UARTIMSC_SPEC> {
         CTSMIM_W::new(self, 1)
     }
     #[doc = "Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn dcdmim(&mut self) -> DCDMIM_W<UARTIMSC_SPEC> {
         DCDMIM_W::new(self, 2)
     }
     #[doc = "Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn dsrmim(&mut self) -> DSRMIM_W<UARTIMSC_SPEC> {
         DSRMIM_W::new(self, 3)
     }
     #[doc = "Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn rxim(&mut self) -> RXIM_W<UARTIMSC_SPEC> {
         RXIM_W::new(self, 4)
     }
     #[doc = "Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn txim(&mut self) -> TXIM_W<UARTIMSC_SPEC> {
         TXIM_W::new(self, 5)
     }
     #[doc = "Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn rtim(&mut self) -> RTIM_W<UARTIMSC_SPEC> {
         RTIM_W::new(self, 6)
     }
     #[doc = "Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn feim(&mut self) -> FEIM_W<UARTIMSC_SPEC> {
         FEIM_W::new(self, 7)
     }
     #[doc = "Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn peim(&mut self) -> PEIM_W<UARTIMSC_SPEC> {
         PEIM_W::new(self, 8)
     }
     #[doc = "Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn beim(&mut self) -> BEIM_W<UARTIMSC_SPEC> {
         BEIM_W::new(self, 9)
     }
     #[doc = "Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."]
     #[inline(always)]
-    #[must_use]
     pub fn oeim(&mut self) -> OEIM_W<UARTIMSC_SPEC> {
         OEIM_W::new(self, 10)
     }
diff --git a/src/inner/uart0/uartlcr_h.rs b/src/inner/uart0/uartlcr_h.rs
index 8263484..7bb69f6 100644
--- a/src/inner/uart0/uartlcr_h.rs
+++ b/src/inner/uart0/uartlcr_h.rs
@@ -70,43 +70,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."]
     #[inline(always)]
-    #[must_use]
     pub fn brk(&mut self) -> BRK_W<UARTLCR_H_SPEC> {
         BRK_W::new(self, 0)
     }
     #[doc = "Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn pen(&mut self) -> PEN_W<UARTLCR_H_SPEC> {
         PEN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."]
     #[inline(always)]
-    #[must_use]
     pub fn eps(&mut self) -> EPS_W<UARTLCR_H_SPEC> {
         EPS_W::new(self, 2)
     }
     #[doc = "Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."]
     #[inline(always)]
-    #[must_use]
     pub fn stp2(&mut self) -> STP2_W<UARTLCR_H_SPEC> {
         STP2_W::new(self, 3)
     }
     #[doc = "Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."]
     #[inline(always)]
-    #[must_use]
     pub fn fen(&mut self) -> FEN_W<UARTLCR_H_SPEC> {
         FEN_W::new(self, 4)
     }
     #[doc = "Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."]
     #[inline(always)]
-    #[must_use]
     pub fn wlen(&mut self) -> WLEN_W<UARTLCR_H_SPEC> {
         WLEN_W::new(self, 5)
     }
     #[doc = "Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."]
     #[inline(always)]
-    #[must_use]
     pub fn sps(&mut self) -> SPS_W<UARTLCR_H_SPEC> {
         SPS_W::new(self, 7)
     }
diff --git a/src/inner/uart0/uartrsr.rs b/src/inner/uart0/uartrsr.rs
index 4a692df..81dde94 100644
--- a/src/inner/uart0/uartrsr.rs
+++ b/src/inner/uart0/uartrsr.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn fe(&mut self) -> FE_W<UARTRSR_SPEC> {
         FE_W::new(self, 0)
     }
     #[doc = "Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn pe(&mut self) -> PE_W<UARTRSR_SPEC> {
         PE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
     #[inline(always)]
-    #[must_use]
     pub fn be(&mut self) -> BE_W<UARTRSR_SPEC> {
         BE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."]
     #[inline(always)]
-    #[must_use]
     pub fn oe(&mut self) -> OE_W<UARTRSR_SPEC> {
         OE_W::new(self, 3)
     }
diff --git a/src/inner/usb.rs b/src/inner/usb.rs
index eaeffa8..d33034c 100644
--- a/src/inner/usb.rs
+++ b/src/inner/usb.rs
@@ -41,6 +41,8 @@ impl RegisterBlock {
         &self.addr_endp
     }
     #[doc = "0x04..0x40 - Interrupt endpoints. Only valid in HOST mode."]
+    #[doc = ""]
+    #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `HOST_ADDR_ENDP1` register.</div>"]
     #[inline(always)]
     pub const fn host_addr_endp(&self, n: usize) -> &HOST_ADDR_ENDP {
         &self.host_addr_endp[n]
@@ -236,7 +238,7 @@ impl RegisterBlock {
     pub const fn intf(&self) -> &INTF {
         &self.intf
     }
-    #[doc = "0x98 - Interrupt status after masking &amp; forcing"]
+    #[doc = "0x98 - Interrupt status after masking & forcing"]
     #[inline(always)]
     pub const fn ints(&self) -> &INTS {
         &self.ints
@@ -488,14 +490,14 @@ module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (rw) register accessor: Interrupt status after masking &amp; forcing  
+#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@ints`]
 module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
-#[doc = "Interrupt status after masking &amp; forcing"]
+#[doc = "Interrupt status after masking & forcing"]
 pub mod ints;
 #[doc = "SOF_TIMESTAMP_RAW (rw) register accessor: Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events.  
 
diff --git a/src/inner/usb/addr_endp.rs b/src/inner/usb/addr_endp.rs
index 657abf7..fc9d0c9 100644
--- a/src/inner/usb/addr_endp.rs
+++ b/src/inner/usb/addr_endp.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<ADDR_ENDP_SPEC> {
         ADDRESS_W::new(self, 0)
     }
     #[doc = "Bits 16:19 - Device endpoint to send data to. Only valid for HOST mode."]
     #[inline(always)]
-    #[must_use]
     pub fn endpoint(&mut self) -> ENDPOINT_W<ADDR_ENDP_SPEC> {
         ENDPOINT_W::new(self, 16)
     }
diff --git a/src/inner/usb/buff_status.rs b/src/inner/usb/buff_status.rs
index a658710..cd84798 100644
--- a/src/inner/usb/buff_status.rs
+++ b/src/inner/usb/buff_status.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_in(&mut self) -> EP0_IN_W<BUFF_STATUS_SPEC> {
         EP0_IN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_out(&mut self) -> EP0_OUT_W<BUFF_STATUS_SPEC> {
         EP0_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_in(&mut self) -> EP1_IN_W<BUFF_STATUS_SPEC> {
         EP1_IN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_out(&mut self) -> EP1_OUT_W<BUFF_STATUS_SPEC> {
         EP1_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_in(&mut self) -> EP2_IN_W<BUFF_STATUS_SPEC> {
         EP2_IN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_out(&mut self) -> EP2_OUT_W<BUFF_STATUS_SPEC> {
         EP2_OUT_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_in(&mut self) -> EP3_IN_W<BUFF_STATUS_SPEC> {
         EP3_IN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_out(&mut self) -> EP3_OUT_W<BUFF_STATUS_SPEC> {
         EP3_OUT_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_in(&mut self) -> EP4_IN_W<BUFF_STATUS_SPEC> {
         EP4_IN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_out(&mut self) -> EP4_OUT_W<BUFF_STATUS_SPEC> {
         EP4_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_in(&mut self) -> EP5_IN_W<BUFF_STATUS_SPEC> {
         EP5_IN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_out(&mut self) -> EP5_OUT_W<BUFF_STATUS_SPEC> {
         EP5_OUT_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_in(&mut self) -> EP6_IN_W<BUFF_STATUS_SPEC> {
         EP6_IN_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_out(&mut self) -> EP6_OUT_W<BUFF_STATUS_SPEC> {
         EP6_OUT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_in(&mut self) -> EP7_IN_W<BUFF_STATUS_SPEC> {
         EP7_IN_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_out(&mut self) -> EP7_OUT_W<BUFF_STATUS_SPEC> {
         EP7_OUT_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_in(&mut self) -> EP8_IN_W<BUFF_STATUS_SPEC> {
         EP8_IN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_out(&mut self) -> EP8_OUT_W<BUFF_STATUS_SPEC> {
         EP8_OUT_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_in(&mut self) -> EP9_IN_W<BUFF_STATUS_SPEC> {
         EP9_IN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_out(&mut self) -> EP9_OUT_W<BUFF_STATUS_SPEC> {
         EP9_OUT_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_in(&mut self) -> EP10_IN_W<BUFF_STATUS_SPEC> {
         EP10_IN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_out(&mut self) -> EP10_OUT_W<BUFF_STATUS_SPEC> {
         EP10_OUT_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_in(&mut self) -> EP11_IN_W<BUFF_STATUS_SPEC> {
         EP11_IN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_out(&mut self) -> EP11_OUT_W<BUFF_STATUS_SPEC> {
         EP11_OUT_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_in(&mut self) -> EP12_IN_W<BUFF_STATUS_SPEC> {
         EP12_IN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_out(&mut self) -> EP12_OUT_W<BUFF_STATUS_SPEC> {
         EP12_OUT_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_in(&mut self) -> EP13_IN_W<BUFF_STATUS_SPEC> {
         EP13_IN_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_out(&mut self) -> EP13_OUT_W<BUFF_STATUS_SPEC> {
         EP13_OUT_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_in(&mut self) -> EP14_IN_W<BUFF_STATUS_SPEC> {
         EP14_IN_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_out(&mut self) -> EP14_OUT_W<BUFF_STATUS_SPEC> {
         EP14_OUT_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_in(&mut self) -> EP15_IN_W<BUFF_STATUS_SPEC> {
         EP15_IN_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_out(&mut self) -> EP15_OUT_W<BUFF_STATUS_SPEC> {
         EP15_OUT_W::new(self, 31)
     }
diff --git a/src/inner/usb/dev_sm_watchdog.rs b/src/inner/usb/dev_sm_watchdog.rs
index 8971b68..694a816 100644
--- a/src/inner/usb/dev_sm_watchdog.rs
+++ b/src/inner/usb/dev_sm_watchdog.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:17"]
     #[inline(always)]
-    #[must_use]
     pub fn limit(&mut self) -> LIMIT_W<DEV_SM_WATCHDOG_SPEC> {
         LIMIT_W::new(self, 0)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<DEV_SM_WATCHDOG_SPEC> {
         ENABLE_W::new(self, 18)
     }
     #[doc = "Bit 19 - Set to 1 to forcibly reset the device state machine on watchdog expiry"]
     #[inline(always)]
-    #[must_use]
     pub fn reset(&mut self) -> RESET_W<DEV_SM_WATCHDOG_SPEC> {
         RESET_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn fired(&mut self) -> FIRED_W<DEV_SM_WATCHDOG_SPEC> {
         FIRED_W::new(self, 20)
     }
diff --git a/src/inner/usb/ep_abort.rs b/src/inner/usb/ep_abort.rs
index ad40d1d..331e2bd 100644
--- a/src/inner/usb/ep_abort.rs
+++ b/src/inner/usb/ep_abort.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_in(&mut self) -> EP0_IN_W<EP_ABORT_SPEC> {
         EP0_IN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_out(&mut self) -> EP0_OUT_W<EP_ABORT_SPEC> {
         EP0_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_in(&mut self) -> EP1_IN_W<EP_ABORT_SPEC> {
         EP1_IN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_out(&mut self) -> EP1_OUT_W<EP_ABORT_SPEC> {
         EP1_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_in(&mut self) -> EP2_IN_W<EP_ABORT_SPEC> {
         EP2_IN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_out(&mut self) -> EP2_OUT_W<EP_ABORT_SPEC> {
         EP2_OUT_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_in(&mut self) -> EP3_IN_W<EP_ABORT_SPEC> {
         EP3_IN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_out(&mut self) -> EP3_OUT_W<EP_ABORT_SPEC> {
         EP3_OUT_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_in(&mut self) -> EP4_IN_W<EP_ABORT_SPEC> {
         EP4_IN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_out(&mut self) -> EP4_OUT_W<EP_ABORT_SPEC> {
         EP4_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_in(&mut self) -> EP5_IN_W<EP_ABORT_SPEC> {
         EP5_IN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_out(&mut self) -> EP5_OUT_W<EP_ABORT_SPEC> {
         EP5_OUT_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_in(&mut self) -> EP6_IN_W<EP_ABORT_SPEC> {
         EP6_IN_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_out(&mut self) -> EP6_OUT_W<EP_ABORT_SPEC> {
         EP6_OUT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_in(&mut self) -> EP7_IN_W<EP_ABORT_SPEC> {
         EP7_IN_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_out(&mut self) -> EP7_OUT_W<EP_ABORT_SPEC> {
         EP7_OUT_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_in(&mut self) -> EP8_IN_W<EP_ABORT_SPEC> {
         EP8_IN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_out(&mut self) -> EP8_OUT_W<EP_ABORT_SPEC> {
         EP8_OUT_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_in(&mut self) -> EP9_IN_W<EP_ABORT_SPEC> {
         EP9_IN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_out(&mut self) -> EP9_OUT_W<EP_ABORT_SPEC> {
         EP9_OUT_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_in(&mut self) -> EP10_IN_W<EP_ABORT_SPEC> {
         EP10_IN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_out(&mut self) -> EP10_OUT_W<EP_ABORT_SPEC> {
         EP10_OUT_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_in(&mut self) -> EP11_IN_W<EP_ABORT_SPEC> {
         EP11_IN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_out(&mut self) -> EP11_OUT_W<EP_ABORT_SPEC> {
         EP11_OUT_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_in(&mut self) -> EP12_IN_W<EP_ABORT_SPEC> {
         EP12_IN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_out(&mut self) -> EP12_OUT_W<EP_ABORT_SPEC> {
         EP12_OUT_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_in(&mut self) -> EP13_IN_W<EP_ABORT_SPEC> {
         EP13_IN_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_out(&mut self) -> EP13_OUT_W<EP_ABORT_SPEC> {
         EP13_OUT_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_in(&mut self) -> EP14_IN_W<EP_ABORT_SPEC> {
         EP14_IN_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_out(&mut self) -> EP14_OUT_W<EP_ABORT_SPEC> {
         EP14_OUT_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_in(&mut self) -> EP15_IN_W<EP_ABORT_SPEC> {
         EP15_IN_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_out(&mut self) -> EP15_OUT_W<EP_ABORT_SPEC> {
         EP15_OUT_W::new(self, 31)
     }
diff --git a/src/inner/usb/ep_abort_done.rs b/src/inner/usb/ep_abort_done.rs
index cbb4c8e..9e0027e 100644
--- a/src/inner/usb/ep_abort_done.rs
+++ b/src/inner/usb/ep_abort_done.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_in(&mut self) -> EP0_IN_W<EP_ABORT_DONE_SPEC> {
         EP0_IN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_out(&mut self) -> EP0_OUT_W<EP_ABORT_DONE_SPEC> {
         EP0_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_in(&mut self) -> EP1_IN_W<EP_ABORT_DONE_SPEC> {
         EP1_IN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_out(&mut self) -> EP1_OUT_W<EP_ABORT_DONE_SPEC> {
         EP1_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_in(&mut self) -> EP2_IN_W<EP_ABORT_DONE_SPEC> {
         EP2_IN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_out(&mut self) -> EP2_OUT_W<EP_ABORT_DONE_SPEC> {
         EP2_OUT_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_in(&mut self) -> EP3_IN_W<EP_ABORT_DONE_SPEC> {
         EP3_IN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_out(&mut self) -> EP3_OUT_W<EP_ABORT_DONE_SPEC> {
         EP3_OUT_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_in(&mut self) -> EP4_IN_W<EP_ABORT_DONE_SPEC> {
         EP4_IN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_out(&mut self) -> EP4_OUT_W<EP_ABORT_DONE_SPEC> {
         EP4_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_in(&mut self) -> EP5_IN_W<EP_ABORT_DONE_SPEC> {
         EP5_IN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_out(&mut self) -> EP5_OUT_W<EP_ABORT_DONE_SPEC> {
         EP5_OUT_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_in(&mut self) -> EP6_IN_W<EP_ABORT_DONE_SPEC> {
         EP6_IN_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_out(&mut self) -> EP6_OUT_W<EP_ABORT_DONE_SPEC> {
         EP6_OUT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_in(&mut self) -> EP7_IN_W<EP_ABORT_DONE_SPEC> {
         EP7_IN_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_out(&mut self) -> EP7_OUT_W<EP_ABORT_DONE_SPEC> {
         EP7_OUT_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_in(&mut self) -> EP8_IN_W<EP_ABORT_DONE_SPEC> {
         EP8_IN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_out(&mut self) -> EP8_OUT_W<EP_ABORT_DONE_SPEC> {
         EP8_OUT_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_in(&mut self) -> EP9_IN_W<EP_ABORT_DONE_SPEC> {
         EP9_IN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_out(&mut self) -> EP9_OUT_W<EP_ABORT_DONE_SPEC> {
         EP9_OUT_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_in(&mut self) -> EP10_IN_W<EP_ABORT_DONE_SPEC> {
         EP10_IN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_out(&mut self) -> EP10_OUT_W<EP_ABORT_DONE_SPEC> {
         EP10_OUT_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_in(&mut self) -> EP11_IN_W<EP_ABORT_DONE_SPEC> {
         EP11_IN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_out(&mut self) -> EP11_OUT_W<EP_ABORT_DONE_SPEC> {
         EP11_OUT_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_in(&mut self) -> EP12_IN_W<EP_ABORT_DONE_SPEC> {
         EP12_IN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_out(&mut self) -> EP12_OUT_W<EP_ABORT_DONE_SPEC> {
         EP12_OUT_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_in(&mut self) -> EP13_IN_W<EP_ABORT_DONE_SPEC> {
         EP13_IN_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_out(&mut self) -> EP13_OUT_W<EP_ABORT_DONE_SPEC> {
         EP13_OUT_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_in(&mut self) -> EP14_IN_W<EP_ABORT_DONE_SPEC> {
         EP14_IN_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_out(&mut self) -> EP14_OUT_W<EP_ABORT_DONE_SPEC> {
         EP14_OUT_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_in(&mut self) -> EP15_IN_W<EP_ABORT_DONE_SPEC> {
         EP15_IN_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_out(&mut self) -> EP15_OUT_W<EP_ABORT_DONE_SPEC> {
         EP15_OUT_W::new(self, 31)
     }
diff --git a/src/inner/usb/ep_rx_error.rs b/src/inner/usb/ep_rx_error.rs
index 426fa6d..2ff8b33 100644
--- a/src/inner/usb/ep_rx_error.rs
+++ b/src/inner/usb/ep_rx_error.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_transaction(&mut self) -> EP0_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP0_TRANSACTION_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_seq(&mut self) -> EP0_SEQ_W<EP_RX_ERROR_SPEC> {
         EP0_SEQ_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_transaction(&mut self) -> EP1_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP1_TRANSACTION_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_seq(&mut self) -> EP1_SEQ_W<EP_RX_ERROR_SPEC> {
         EP1_SEQ_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_transaction(&mut self) -> EP2_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP2_TRANSACTION_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_seq(&mut self) -> EP2_SEQ_W<EP_RX_ERROR_SPEC> {
         EP2_SEQ_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_transaction(&mut self) -> EP3_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP3_TRANSACTION_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_seq(&mut self) -> EP3_SEQ_W<EP_RX_ERROR_SPEC> {
         EP3_SEQ_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_transaction(&mut self) -> EP4_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP4_TRANSACTION_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_seq(&mut self) -> EP4_SEQ_W<EP_RX_ERROR_SPEC> {
         EP4_SEQ_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_transaction(&mut self) -> EP5_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP5_TRANSACTION_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_seq(&mut self) -> EP5_SEQ_W<EP_RX_ERROR_SPEC> {
         EP5_SEQ_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_transaction(&mut self) -> EP6_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP6_TRANSACTION_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_seq(&mut self) -> EP6_SEQ_W<EP_RX_ERROR_SPEC> {
         EP6_SEQ_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_transaction(&mut self) -> EP7_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP7_TRANSACTION_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_seq(&mut self) -> EP7_SEQ_W<EP_RX_ERROR_SPEC> {
         EP7_SEQ_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_transaction(&mut self) -> EP8_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP8_TRANSACTION_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_seq(&mut self) -> EP8_SEQ_W<EP_RX_ERROR_SPEC> {
         EP8_SEQ_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_transaction(&mut self) -> EP9_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP9_TRANSACTION_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_seq(&mut self) -> EP9_SEQ_W<EP_RX_ERROR_SPEC> {
         EP9_SEQ_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_transaction(&mut self) -> EP10_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP10_TRANSACTION_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_seq(&mut self) -> EP10_SEQ_W<EP_RX_ERROR_SPEC> {
         EP10_SEQ_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_transaction(&mut self) -> EP11_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP11_TRANSACTION_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_seq(&mut self) -> EP11_SEQ_W<EP_RX_ERROR_SPEC> {
         EP11_SEQ_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_transaction(&mut self) -> EP12_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP12_TRANSACTION_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_seq(&mut self) -> EP12_SEQ_W<EP_RX_ERROR_SPEC> {
         EP12_SEQ_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_transaction(&mut self) -> EP13_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP13_TRANSACTION_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_seq(&mut self) -> EP13_SEQ_W<EP_RX_ERROR_SPEC> {
         EP13_SEQ_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_transaction(&mut self) -> EP14_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP14_TRANSACTION_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_seq(&mut self) -> EP14_SEQ_W<EP_RX_ERROR_SPEC> {
         EP14_SEQ_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_transaction(&mut self) -> EP15_TRANSACTION_W<EP_RX_ERROR_SPEC> {
         EP15_TRANSACTION_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_seq(&mut self) -> EP15_SEQ_W<EP_RX_ERROR_SPEC> {
         EP15_SEQ_W::new(self, 31)
     }
diff --git a/src/inner/usb/ep_stall_arm.rs b/src/inner/usb/ep_stall_arm.rs
index 4d1d45a..2536e15 100644
--- a/src/inner/usb/ep_stall_arm.rs
+++ b/src/inner/usb/ep_stall_arm.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_in(&mut self) -> EP0_IN_W<EP_STALL_ARM_SPEC> {
         EP0_IN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_out(&mut self) -> EP0_OUT_W<EP_STALL_ARM_SPEC> {
         EP0_OUT_W::new(self, 1)
     }
diff --git a/src/inner/usb/ep_status_stall_nak.rs b/src/inner/usb/ep_status_stall_nak.rs
index cc46a4e..342fd96 100644
--- a/src/inner/usb/ep_status_stall_nak.rs
+++ b/src/inner/usb/ep_status_stall_nak.rs
@@ -295,193 +295,161 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_in(&mut self) -> EP0_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP0_IN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_out(&mut self) -> EP0_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP0_OUT_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_in(&mut self) -> EP1_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP1_IN_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1_out(&mut self) -> EP1_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP1_OUT_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_in(&mut self) -> EP2_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP2_IN_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2_out(&mut self) -> EP2_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP2_OUT_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_in(&mut self) -> EP3_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP3_IN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3_out(&mut self) -> EP3_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP3_OUT_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_in(&mut self) -> EP4_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP4_IN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4_out(&mut self) -> EP4_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP4_OUT_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_in(&mut self) -> EP5_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP5_IN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5_out(&mut self) -> EP5_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP5_OUT_W::new(self, 11)
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_in(&mut self) -> EP6_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP6_IN_W::new(self, 12)
     }
     #[doc = "Bit 13"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6_out(&mut self) -> EP6_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP6_OUT_W::new(self, 13)
     }
     #[doc = "Bit 14"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_in(&mut self) -> EP7_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP7_IN_W::new(self, 14)
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7_out(&mut self) -> EP7_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP7_OUT_W::new(self, 15)
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_in(&mut self) -> EP8_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP8_IN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8_out(&mut self) -> EP8_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP8_OUT_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_in(&mut self) -> EP9_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP9_IN_W::new(self, 18)
     }
     #[doc = "Bit 19"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9_out(&mut self) -> EP9_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP9_OUT_W::new(self, 19)
     }
     #[doc = "Bit 20"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_in(&mut self) -> EP10_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP10_IN_W::new(self, 20)
     }
     #[doc = "Bit 21"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10_out(&mut self) -> EP10_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP10_OUT_W::new(self, 21)
     }
     #[doc = "Bit 22"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_in(&mut self) -> EP11_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP11_IN_W::new(self, 22)
     }
     #[doc = "Bit 23"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11_out(&mut self) -> EP11_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP11_OUT_W::new(self, 23)
     }
     #[doc = "Bit 24"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_in(&mut self) -> EP12_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP12_IN_W::new(self, 24)
     }
     #[doc = "Bit 25"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12_out(&mut self) -> EP12_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP12_OUT_W::new(self, 25)
     }
     #[doc = "Bit 26"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_in(&mut self) -> EP13_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP13_IN_W::new(self, 26)
     }
     #[doc = "Bit 27"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13_out(&mut self) -> EP13_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP13_OUT_W::new(self, 27)
     }
     #[doc = "Bit 28"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_in(&mut self) -> EP14_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP14_IN_W::new(self, 28)
     }
     #[doc = "Bit 29"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14_out(&mut self) -> EP14_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP14_OUT_W::new(self, 29)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_in(&mut self) -> EP15_IN_W<EP_STATUS_STALL_NAK_SPEC> {
         EP15_IN_W::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15_out(&mut self) -> EP15_OUT_W<EP_STATUS_STALL_NAK_SPEC> {
         EP15_OUT_W::new(self, 31)
     }
diff --git a/src/inner/usb/ep_tx_error.rs b/src/inner/usb/ep_tx_error.rs
index 276fb45..613c0a7 100644
--- a/src/inner/usb/ep_tx_error.rs
+++ b/src/inner/usb/ep_tx_error.rs
@@ -151,97 +151,81 @@ impl R {
 impl W {
     #[doc = "Bits 0:1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0(&mut self) -> EP0_W<EP_TX_ERROR_SPEC> {
         EP0_W::new(self, 0)
     }
     #[doc = "Bits 2:3"]
     #[inline(always)]
-    #[must_use]
     pub fn ep1(&mut self) -> EP1_W<EP_TX_ERROR_SPEC> {
         EP1_W::new(self, 2)
     }
     #[doc = "Bits 4:5"]
     #[inline(always)]
-    #[must_use]
     pub fn ep2(&mut self) -> EP2_W<EP_TX_ERROR_SPEC> {
         EP2_W::new(self, 4)
     }
     #[doc = "Bits 6:7"]
     #[inline(always)]
-    #[must_use]
     pub fn ep3(&mut self) -> EP3_W<EP_TX_ERROR_SPEC> {
         EP3_W::new(self, 6)
     }
     #[doc = "Bits 8:9"]
     #[inline(always)]
-    #[must_use]
     pub fn ep4(&mut self) -> EP4_W<EP_TX_ERROR_SPEC> {
         EP4_W::new(self, 8)
     }
     #[doc = "Bits 10:11"]
     #[inline(always)]
-    #[must_use]
     pub fn ep5(&mut self) -> EP5_W<EP_TX_ERROR_SPEC> {
         EP5_W::new(self, 10)
     }
     #[doc = "Bits 12:13"]
     #[inline(always)]
-    #[must_use]
     pub fn ep6(&mut self) -> EP6_W<EP_TX_ERROR_SPEC> {
         EP6_W::new(self, 12)
     }
     #[doc = "Bits 14:15"]
     #[inline(always)]
-    #[must_use]
     pub fn ep7(&mut self) -> EP7_W<EP_TX_ERROR_SPEC> {
         EP7_W::new(self, 14)
     }
     #[doc = "Bits 16:17"]
     #[inline(always)]
-    #[must_use]
     pub fn ep8(&mut self) -> EP8_W<EP_TX_ERROR_SPEC> {
         EP8_W::new(self, 16)
     }
     #[doc = "Bits 18:19"]
     #[inline(always)]
-    #[must_use]
     pub fn ep9(&mut self) -> EP9_W<EP_TX_ERROR_SPEC> {
         EP9_W::new(self, 18)
     }
     #[doc = "Bits 20:21"]
     #[inline(always)]
-    #[must_use]
     pub fn ep10(&mut self) -> EP10_W<EP_TX_ERROR_SPEC> {
         EP10_W::new(self, 20)
     }
     #[doc = "Bits 22:23"]
     #[inline(always)]
-    #[must_use]
     pub fn ep11(&mut self) -> EP11_W<EP_TX_ERROR_SPEC> {
         EP11_W::new(self, 22)
     }
     #[doc = "Bits 24:25"]
     #[inline(always)]
-    #[must_use]
     pub fn ep12(&mut self) -> EP12_W<EP_TX_ERROR_SPEC> {
         EP12_W::new(self, 24)
     }
     #[doc = "Bits 26:27"]
     #[inline(always)]
-    #[must_use]
     pub fn ep13(&mut self) -> EP13_W<EP_TX_ERROR_SPEC> {
         EP13_W::new(self, 26)
     }
     #[doc = "Bits 28:29"]
     #[inline(always)]
-    #[must_use]
     pub fn ep14(&mut self) -> EP14_W<EP_TX_ERROR_SPEC> {
         EP14_W::new(self, 28)
     }
     #[doc = "Bits 30:31"]
     #[inline(always)]
-    #[must_use]
     pub fn ep15(&mut self) -> EP15_W<EP_TX_ERROR_SPEC> {
         EP15_W::new(self, 30)
     }
diff --git a/src/inner/usb/host_addr_endp.rs b/src/inner/usb/host_addr_endp.rs
index 7d20548..5dbc83f 100644
--- a/src/inner/usb/host_addr_endp.rs
+++ b/src/inner/usb/host_addr_endp.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:6 - Device address"]
     #[inline(always)]
-    #[must_use]
     pub fn address(&mut self) -> ADDRESS_W<HOST_ADDR_ENDP_SPEC> {
         ADDRESS_W::new(self, 0)
     }
     #[doc = "Bits 16:19 - Endpoint number of the interrupt endpoint"]
     #[inline(always)]
-    #[must_use]
     pub fn endpoint(&mut self) -> ENDPOINT_W<HOST_ADDR_ENDP_SPEC> {
         ENDPOINT_W::new(self, 16)
     }
     #[doc = "Bit 25 - Direction of the interrupt endpoint. In=0, Out=1"]
     #[inline(always)]
-    #[must_use]
     pub fn intep_dir(&mut self) -> INTEP_DIR_W<HOST_ADDR_ENDP_SPEC> {
         INTEP_DIR_W::new(self, 25)
     }
     #[doc = "Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)"]
     #[inline(always)]
-    #[must_use]
     pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W<HOST_ADDR_ENDP_SPEC> {
         INTEP_PREAMBLE_W::new(self, 26)
     }
diff --git a/src/inner/usb/int_ep_ctrl.rs b/src/inner/usb/int_ep_ctrl.rs
index 5dcdd08..ee59452 100644
--- a/src/inner/usb/int_ep_ctrl.rs
+++ b/src/inner/usb/int_ep_ctrl.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"]
     #[inline(always)]
-    #[must_use]
     pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W<INT_EP_CTRL_SPEC> {
         INT_EP_ACTIVE_W::new(self, 1)
     }
diff --git a/src/inner/usb/inte.rs b/src/inner/usb/inte.rs
index 1464e75..2224714 100644
--- a/src/inner/usb/inte.rs
+++ b/src/inner/usb/inte.rs
@@ -223,145 +223,121 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"]
     #[inline(always)]
-    #[must_use]
     pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W<INTE_SPEC> {
         HOST_CONN_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"]
     #[inline(always)]
-    #[must_use]
     pub fn host_resume(&mut self) -> HOST_RESUME_W<INTE_SPEC> {
         HOST_RESUME_W::new(self, 1)
     }
     #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"]
     #[inline(always)]
-    #[must_use]
     pub fn host_sof(&mut self) -> HOST_SOF_W<INTE_SPEC> {
         HOST_SOF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INTE_SPEC> {
         TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."]
     #[inline(always)]
-    #[must_use]
     pub fn buff_status(&mut self) -> BUFF_STATUS_W<INTE_SPEC> {
         BUFF_STATUS_W::new(self, 4)
     }
     #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W<INTE_SPEC> {
         ERROR_DATA_SEQ_W::new(self, 5)
     }
     #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"]
     #[inline(always)]
-    #[must_use]
     pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W<INTE_SPEC> {
         ERROR_RX_TIMEOUT_W::new(self, 6)
     }
     #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"]
     #[inline(always)]
-    #[must_use]
     pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W<INTE_SPEC> {
         ERROR_RX_OVERFLOW_W::new(self, 7)
     }
     #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W<INTE_SPEC> {
         ERROR_BIT_STUFF_W::new(self, 8)
     }
     #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn error_crc(&mut self) -> ERROR_CRC_W<INTE_SPEC> {
         ERROR_CRC_W::new(self, 9)
     }
     #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<INTE_SPEC> {
         STALL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<INTE_SPEC> {
         VBUS_DETECT_W::new(self, 11)
     }
     #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"]
     #[inline(always)]
-    #[must_use]
     pub fn bus_reset(&mut self) -> BUS_RESET_W<INTE_SPEC> {
         BUS_RESET_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W<INTE_SPEC> {
         DEV_CONN_DIS_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W<INTE_SPEC> {
         DEV_SUSPEND_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W<INTE_SPEC> {
         DEV_RESUME_FROM_HOST_W::new(self, 15)
     }
     #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"]
     #[inline(always)]
-    #[must_use]
     pub fn setup_req(&mut self) -> SETUP_REQ_W<INTE_SPEC> {
         SETUP_REQ_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_sof(&mut self) -> DEV_SOF_W<INTE_SPEC> {
         DEV_SOF_W::new(self, 17)
     }
     #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_done(&mut self) -> ABORT_DONE_W<INTE_SPEC> {
         ABORT_DONE_W::new(self, 18)
     }
     #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."]
     #[inline(always)]
-    #[must_use]
     pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W<INTE_SPEC> {
         EP_STALL_NAK_W::new(self, 19)
     }
     #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_short_packet(&mut self) -> RX_SHORT_PACKET_W<INTE_SPEC> {
         RX_SHORT_PACKET_W::new(self, 20)
     }
     #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn endpoint_error(&mut self) -> ENDPOINT_ERROR_W<INTE_SPEC> {
         ENDPOINT_ERROR_W::new(self, 21)
     }
     #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_sm_watchdog_fired(&mut self) -> DEV_SM_WATCHDOG_FIRED_W<INTE_SPEC> {
         DEV_SM_WATCHDOG_FIRED_W::new(self, 22)
     }
     #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"]
     #[inline(always)]
-    #[must_use]
     pub fn epx_stopped_on_nak(&mut self) -> EPX_STOPPED_ON_NAK_W<INTE_SPEC> {
         EPX_STOPPED_ON_NAK_W::new(self, 23)
     }
diff --git a/src/inner/usb/intf.rs b/src/inner/usb/intf.rs
index bee29f6..b0b3b78 100644
--- a/src/inner/usb/intf.rs
+++ b/src/inner/usb/intf.rs
@@ -223,145 +223,121 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"]
     #[inline(always)]
-    #[must_use]
     pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W<INTF_SPEC> {
         HOST_CONN_DIS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"]
     #[inline(always)]
-    #[must_use]
     pub fn host_resume(&mut self) -> HOST_RESUME_W<INTF_SPEC> {
         HOST_RESUME_W::new(self, 1)
     }
     #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"]
     #[inline(always)]
-    #[must_use]
     pub fn host_sof(&mut self) -> HOST_SOF_W<INTF_SPEC> {
         HOST_SOF_W::new(self, 2)
     }
     #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INTF_SPEC> {
         TRANS_COMPLETE_W::new(self, 3)
     }
     #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."]
     #[inline(always)]
-    #[must_use]
     pub fn buff_status(&mut self) -> BUFF_STATUS_W<INTF_SPEC> {
         BUFF_STATUS_W::new(self, 4)
     }
     #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W<INTF_SPEC> {
         ERROR_DATA_SEQ_W::new(self, 5)
     }
     #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"]
     #[inline(always)]
-    #[must_use]
     pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W<INTF_SPEC> {
         ERROR_RX_TIMEOUT_W::new(self, 6)
     }
     #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"]
     #[inline(always)]
-    #[must_use]
     pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W<INTF_SPEC> {
         ERROR_RX_OVERFLOW_W::new(self, 7)
     }
     #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W<INTF_SPEC> {
         ERROR_BIT_STUFF_W::new(self, 8)
     }
     #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn error_crc(&mut self) -> ERROR_CRC_W<INTF_SPEC> {
         ERROR_CRC_W::new(self, 9)
     }
     #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<INTF_SPEC> {
         STALL_W::new(self, 10)
     }
     #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<INTF_SPEC> {
         VBUS_DETECT_W::new(self, 11)
     }
     #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"]
     #[inline(always)]
-    #[must_use]
     pub fn bus_reset(&mut self) -> BUS_RESET_W<INTF_SPEC> {
         BUS_RESET_W::new(self, 12)
     }
     #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W<INTF_SPEC> {
         DEV_CONN_DIS_W::new(self, 13)
     }
     #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W<INTF_SPEC> {
         DEV_SUSPEND_W::new(self, 14)
     }
     #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W<INTF_SPEC> {
         DEV_RESUME_FROM_HOST_W::new(self, 15)
     }
     #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"]
     #[inline(always)]
-    #[must_use]
     pub fn setup_req(&mut self) -> SETUP_REQ_W<INTF_SPEC> {
         SETUP_REQ_W::new(self, 16)
     }
     #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_sof(&mut self) -> DEV_SOF_W<INTF_SPEC> {
         DEV_SOF_W::new(self, 17)
     }
     #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."]
     #[inline(always)]
-    #[must_use]
     pub fn abort_done(&mut self) -> ABORT_DONE_W<INTF_SPEC> {
         ABORT_DONE_W::new(self, 18)
     }
     #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."]
     #[inline(always)]
-    #[must_use]
     pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W<INTF_SPEC> {
         EP_STALL_NAK_W::new(self, 19)
     }
     #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_short_packet(&mut self) -> RX_SHORT_PACKET_W<INTF_SPEC> {
         RX_SHORT_PACKET_W::new(self, 20)
     }
     #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"]
     #[inline(always)]
-    #[must_use]
     pub fn endpoint_error(&mut self) -> ENDPOINT_ERROR_W<INTF_SPEC> {
         ENDPOINT_ERROR_W::new(self, 21)
     }
     #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_sm_watchdog_fired(&mut self) -> DEV_SM_WATCHDOG_FIRED_W<INTF_SPEC> {
         DEV_SM_WATCHDOG_FIRED_W::new(self, 22)
     }
     #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"]
     #[inline(always)]
-    #[must_use]
     pub fn epx_stopped_on_nak(&mut self) -> EPX_STOPPED_ON_NAK_W<INTF_SPEC> {
         EPX_STOPPED_ON_NAK_W::new(self, 23)
     }
diff --git a/src/inner/usb/ints.rs b/src/inner/usb/ints.rs
index 0e80b9c..f88f1e6 100644
--- a/src/inner/usb/ints.rs
+++ b/src/inner/usb/ints.rs
@@ -173,7 +173,7 @@ impl R {
     }
 }
 impl W {}
-#[doc = "Interrupt status after masking &amp; forcing  
+#[doc = "Interrupt status after masking & forcing  
 
 You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct INTS_SPEC;
diff --git a/src/inner/usb/linestate_tuning.rs b/src/inner/usb/linestate_tuning.rs
index 4f2aafa..99902b1 100644
--- a/src/inner/usb/linestate_tuning.rs
+++ b/src/inner/usb/linestate_tuning.rs
@@ -88,25 +88,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."]
     #[inline(always)]
-    #[must_use]
     pub fn rcv_delay(&mut self) -> RCV_DELAY_W<LINESTATE_TUNING_SPEC> {
         RCV_DELAY_W::new(self, 0)
     }
     #[doc = "Bit 1 - Device/Host - add an extra 1-bit debounce of linestate sampling."]
     #[inline(always)]
-    #[must_use]
     pub fn linestate_delay(&mut self) -> LINESTATE_DELAY_W<LINESTATE_TUNING_SPEC> {
         LINESTATE_DELAY_W::new(self, 1)
     }
     #[doc = "Bit 2 - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."]
     #[inline(always)]
-    #[must_use]
     pub fn multi_hub_fix(&mut self) -> MULTI_HUB_FIX_W<LINESTATE_TUNING_SPEC> {
         MULTI_HUB_FIX_W::new(self, 2)
     }
     #[doc = "Bit 3 - Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."]
     #[inline(always)]
-    #[must_use]
     pub fn dev_buff_control_double_read_fix(
         &mut self,
     ) -> DEV_BUFF_CONTROL_DOUBLE_READ_FIX_W<LINESTATE_TUNING_SPEC> {
@@ -114,31 +110,26 @@ impl W {
     }
     #[doc = "Bit 4 - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."]
     #[inline(always)]
-    #[must_use]
     pub fn sie_rx_bitstuff_fix(&mut self) -> SIE_RX_BITSTUFF_FIX_W<LINESTATE_TUNING_SPEC> {
         SIE_RX_BITSTUFF_FIX_W::new(self, 4)
     }
     #[doc = "Bit 5 - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."]
     #[inline(always)]
-    #[must_use]
     pub fn sie_rx_chatter_se0_fix(&mut self) -> SIE_RX_CHATTER_SE0_FIX_W<LINESTATE_TUNING_SPEC> {
         SIE_RX_CHATTER_SE0_FIX_W::new(self, 5)
     }
     #[doc = "Bit 6 - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."]
     #[inline(always)]
-    #[must_use]
     pub fn dev_rx_err_quiesce(&mut self) -> DEV_RX_ERR_QUIESCE_W<LINESTATE_TUNING_SPEC> {
         DEV_RX_ERR_QUIESCE_W::new(self, 6)
     }
     #[doc = "Bit 7 - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"]
     #[inline(always)]
-    #[must_use]
     pub fn dev_ls_wake_fix(&mut self) -> DEV_LS_WAKE_FIX_W<LINESTATE_TUNING_SPEC> {
         DEV_LS_WAKE_FIX_W::new(self, 7)
     }
     #[doc = "Bits 8:11"]
     #[inline(always)]
-    #[must_use]
     pub fn spare_fix(&mut self) -> SPARE_FIX_W<LINESTATE_TUNING_SPEC> {
         SPARE_FIX_W::new(self, 8)
     }
diff --git a/src/inner/usb/main_ctrl.rs b/src/inner/usb/main_ctrl.rs
index 5f210f1..0d49ea0 100644
--- a/src/inner/usb/main_ctrl.rs
+++ b/src/inner/usb/main_ctrl.rs
@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable controller"]
     #[inline(always)]
-    #[must_use]
     pub fn controller_en(&mut self) -> CONTROLLER_EN_W<MAIN_CTRL_SPEC> {
         CONTROLLER_EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Device mode = 0, Host mode = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn host_ndevice(&mut self) -> HOST_NDEVICE_W<MAIN_CTRL_SPEC> {
         HOST_NDEVICE_W::new(self, 1)
     }
     #[doc = "Bit 2 - Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn phy_iso(&mut self) -> PHY_ISO_W<MAIN_CTRL_SPEC> {
         PHY_ISO_W::new(self, 2)
     }
     #[doc = "Bit 31 - Reduced timings for simulation"]
     #[inline(always)]
-    #[must_use]
     pub fn sim_timing(&mut self) -> SIM_TIMING_W<MAIN_CTRL_SPEC> {
         SIM_TIMING_W::new(self, 31)
     }
diff --git a/src/inner/usb/nak_poll.rs b/src/inner/usb/nak_poll.rs
index 1d71527..58024d2 100644
--- a/src/inner/usb/nak_poll.rs
+++ b/src/inner/usb/nak_poll.rs
@@ -57,25 +57,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:9 - NAK polling interval for a low speed device"]
     #[inline(always)]
-    #[must_use]
     pub fn delay_ls(&mut self) -> DELAY_LS_W<NAK_POLL_SPEC> {
         DELAY_LS_W::new(self, 0)
     }
     #[doc = "Bits 16:25 - NAK polling interval for a full speed device"]
     #[inline(always)]
-    #[must_use]
     pub fn delay_fs(&mut self) -> DELAY_FS_W<NAK_POLL_SPEC> {
         DELAY_FS_W::new(self, 16)
     }
     #[doc = "Bit 26 - Stop polling epx when a nak is received"]
     #[inline(always)]
-    #[must_use]
     pub fn stop_epx_on_nak(&mut self) -> STOP_EPX_ON_NAK_W<NAK_POLL_SPEC> {
         STOP_EPX_ON_NAK_W::new(self, 26)
     }
     #[doc = "Bit 27 - EPX polling has stopped because a nak was received"]
     #[inline(always)]
-    #[must_use]
     pub fn epx_stopped_on_nak(&mut self) -> EPX_STOPPED_ON_NAK_W<NAK_POLL_SPEC> {
         EPX_STOPPED_ON_NAK_W::new(self, 27)
     }
diff --git a/src/inner/usb/sie_ctrl.rs b/src/inner/usb/sie_ctrl.rs
index 73c4fd4..4f7ee95 100644
--- a/src/inner/usb/sie_ctrl.rs
+++ b/src/inner/usb/sie_ctrl.rs
@@ -204,151 +204,126 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Host: Start transaction"]
     #[inline(always)]
-    #[must_use]
     pub fn start_trans(&mut self) -> START_TRANS_W<SIE_CTRL_SPEC> {
         START_TRANS_W::new(self, 0)
     }
     #[doc = "Bit 1 - Host: Send Setup packet"]
     #[inline(always)]
-    #[must_use]
     pub fn send_setup(&mut self) -> SEND_SETUP_W<SIE_CTRL_SPEC> {
         SEND_SETUP_W::new(self, 1)
     }
     #[doc = "Bit 2 - Host: Send transaction (OUT from host)"]
     #[inline(always)]
-    #[must_use]
     pub fn send_data(&mut self) -> SEND_DATA_W<SIE_CTRL_SPEC> {
         SEND_DATA_W::new(self, 2)
     }
     #[doc = "Bit 3 - Host: Receive transaction (IN to host)"]
     #[inline(always)]
-    #[must_use]
     pub fn receive_data(&mut self) -> RECEIVE_DATA_W<SIE_CTRL_SPEC> {
         RECEIVE_DATA_W::new(self, 3)
     }
     #[doc = "Bit 4 - Host: Stop transaction"]
     #[inline(always)]
-    #[must_use]
     pub fn stop_trans(&mut self) -> STOP_TRANS_W<SIE_CTRL_SPEC> {
         STOP_TRANS_W::new(self, 4)
     }
     #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"]
     #[inline(always)]
-    #[must_use]
     pub fn preamble_en(&mut self) -> PREAMBLE_EN_W<SIE_CTRL_SPEC> {
         PREAMBLE_EN_W::new(self, 6)
     }
     #[doc = "Bit 8 - Host: Delay packet(s) until after SOF"]
     #[inline(always)]
-    #[must_use]
     pub fn sof_sync(&mut self) -> SOF_SYNC_W<SIE_CTRL_SPEC> {
         SOF_SYNC_W::new(self, 8)
     }
     #[doc = "Bit 9 - Host: Enable SOF generation (for full speed bus)"]
     #[inline(always)]
-    #[must_use]
     pub fn sof_en(&mut self) -> SOF_EN_W<SIE_CTRL_SPEC> {
         SOF_EN_W::new(self, 9)
     }
     #[doc = "Bit 10 - Host: Enable keep alive packet (for low speed bus)"]
     #[inline(always)]
-    #[must_use]
     pub fn keep_alive_en(&mut self) -> KEEP_ALIVE_EN_W<SIE_CTRL_SPEC> {
         KEEP_ALIVE_EN_W::new(self, 10)
     }
     #[doc = "Bit 11 - Host: Enable VBUS"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_en(&mut self) -> VBUS_EN_W<SIE_CTRL_SPEC> {
         VBUS_EN_W::new(self, 11)
     }
     #[doc = "Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend."]
     #[inline(always)]
-    #[must_use]
     pub fn resume(&mut self) -> RESUME_W<SIE_CTRL_SPEC> {
         RESUME_W::new(self, 12)
     }
     #[doc = "Bit 13 - Host: Reset bus"]
     #[inline(always)]
-    #[must_use]
     pub fn reset_bus(&mut self) -> RESET_BUS_W<SIE_CTRL_SPEC> {
         RESET_BUS_W::new(self, 13)
     }
     #[doc = "Bit 15 - Host: Enable pull down resistors"]
     #[inline(always)]
-    #[must_use]
     pub fn pulldown_en(&mut self) -> PULLDOWN_EN_W<SIE_CTRL_SPEC> {
         PULLDOWN_EN_W::new(self, 15)
     }
     #[doc = "Bit 16 - Device: Enable pull up resistor"]
     #[inline(always)]
-    #[must_use]
     pub fn pullup_en(&mut self) -> PULLUP_EN_W<SIE_CTRL_SPEC> {
         PULLUP_EN_W::new(self, 16)
     }
     #[doc = "Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)"]
     #[inline(always)]
-    #[must_use]
     pub fn rpu_opt(&mut self) -> RPU_OPT_W<SIE_CTRL_SPEC> {
         RPU_OPT_W::new(self, 17)
     }
     #[doc = "Bit 18 - Power down bus transceiver"]
     #[inline(always)]
-    #[must_use]
     pub fn transceiver_pd(&mut self) -> TRANSCEIVER_PD_W<SIE_CTRL_SPEC> {
         TRANSCEIVER_PD_W::new(self, 18)
     }
     #[doc = "Bit 19 - Device: Stop EP0 on a short packet."]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_stop_on_short_packet(&mut self) -> EP0_STOP_ON_SHORT_PACKET_W<SIE_CTRL_SPEC> {
         EP0_STOP_ON_SHORT_PACKET_W::new(self, 19)
     }
     #[doc = "Bit 24 - Direct control of DM"]
     #[inline(always)]
-    #[must_use]
     pub fn direct_dm(&mut self) -> DIRECT_DM_W<SIE_CTRL_SPEC> {
         DIRECT_DM_W::new(self, 24)
     }
     #[doc = "Bit 25 - Direct control of DP"]
     #[inline(always)]
-    #[must_use]
     pub fn direct_dp(&mut self) -> DIRECT_DP_W<SIE_CTRL_SPEC> {
         DIRECT_DP_W::new(self, 25)
     }
     #[doc = "Bit 26 - Direct bus drive enable"]
     #[inline(always)]
-    #[must_use]
     pub fn direct_en(&mut self) -> DIRECT_EN_W<SIE_CTRL_SPEC> {
         DIRECT_EN_W::new(self, 26)
     }
     #[doc = "Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_int_nak(&mut self) -> EP0_INT_NAK_W<SIE_CTRL_SPEC> {
         EP0_INT_NAK_W::new(self, 27)
     }
     #[doc = "Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_int_2buf(&mut self) -> EP0_INT_2BUF_W<SIE_CTRL_SPEC> {
         EP0_INT_2BUF_W::new(self, 28)
     }
     #[doc = "Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_int_1buf(&mut self) -> EP0_INT_1BUF_W<SIE_CTRL_SPEC> {
         EP0_INT_1BUF_W::new(self, 29)
     }
     #[doc = "Bit 30 - Device: EP0 single buffered = 0, double buffered = 1"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_double_buf(&mut self) -> EP0_DOUBLE_BUF_W<SIE_CTRL_SPEC> {
         EP0_DOUBLE_BUF_W::new(self, 30)
     }
     #[doc = "Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"]
     #[inline(always)]
-    #[must_use]
     pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W<SIE_CTRL_SPEC> {
         EP0_INT_STALL_W::new(self, 31)
     }
diff --git a/src/inner/usb/sie_status.rs b/src/inner/usb/sie_status.rs
index f725385..d6c92d9 100644
--- a/src/inner/usb/sie_status.rs
+++ b/src/inner/usb/sie_status.rs
@@ -235,91 +235,76 @@ impl R {
 impl W {
     #[doc = "Bit 4 - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn suspended(&mut self) -> SUSPENDED_W<SIE_STATUS_SPEC> {
         SUSPENDED_W::new(self, 4)
     }
     #[doc = "Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume."]
     #[inline(always)]
-    #[must_use]
     pub fn resume(&mut self) -> RESUME_W<SIE_STATUS_SPEC> {
         RESUME_W::new(self, 11)
     }
     #[doc = "Bit 12 - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_short_packet(&mut self) -> RX_SHORT_PACKET_W<SIE_STATUS_SPEC> {
         RX_SHORT_PACKET_W::new(self, 12)
     }
     #[doc = "Bit 17 - Device: Setup packet received"]
     #[inline(always)]
-    #[must_use]
     pub fn setup_rec(&mut self) -> SETUP_REC_W<SIE_STATUS_SPEC> {
         SETUP_REC_W::new(self, 17)
     }
     #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"]
     #[inline(always)]
-    #[must_use]
     pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<SIE_STATUS_SPEC> {
         TRANS_COMPLETE_W::new(self, 18)
     }
     #[doc = "Bit 19 - Device: bus reset received"]
     #[inline(always)]
-    #[must_use]
     pub fn bus_reset(&mut self) -> BUS_RESET_W<SIE_STATUS_SPEC> {
         BUS_RESET_W::new(self, 19)
     }
     #[doc = "Bit 23 - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."]
     #[inline(always)]
-    #[must_use]
     pub fn endpoint_error(&mut self) -> ENDPOINT_ERROR_W<SIE_STATUS_SPEC> {
         ENDPOINT_ERROR_W::new(self, 23)
     }
     #[doc = "Bit 24 - CRC Error. Raised by the Serial RX engine."]
     #[inline(always)]
-    #[must_use]
     pub fn crc_error(&mut self) -> CRC_ERROR_W<SIE_STATUS_SPEC> {
         CRC_ERROR_W::new(self, 24)
     }
     #[doc = "Bit 25 - Bit Stuff Error. Raised by the Serial RX engine."]
     #[inline(always)]
-    #[must_use]
     pub fn bit_stuff_error(&mut self) -> BIT_STUFF_ERROR_W<SIE_STATUS_SPEC> {
         BIT_STUFF_ERROR_W::new(self, 25)
     }
     #[doc = "Bit 26 - RX overflow is raised by the Serial RX engine if the incoming data is too fast."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_overflow(&mut self) -> RX_OVERFLOW_W<SIE_STATUS_SPEC> {
         RX_OVERFLOW_W::new(self, 26)
     }
     #[doc = "Bit 27 - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_timeout(&mut self) -> RX_TIMEOUT_W<SIE_STATUS_SPEC> {
         RX_TIMEOUT_W::new(self, 27)
     }
     #[doc = "Bit 28 - Host: NAK received"]
     #[inline(always)]
-    #[must_use]
     pub fn nak_rec(&mut self) -> NAK_REC_W<SIE_STATUS_SPEC> {
         NAK_REC_W::new(self, 28)
     }
     #[doc = "Bit 29 - Host: STALL received"]
     #[inline(always)]
-    #[must_use]
     pub fn stall_rec(&mut self) -> STALL_REC_W<SIE_STATUS_SPEC> {
         STALL_REC_W::new(self, 29)
     }
     #[doc = "Bit 30 - ACK received. Raised by both host and device."]
     #[inline(always)]
-    #[must_use]
     pub fn ack_rec(&mut self) -> ACK_REC_W<SIE_STATUS_SPEC> {
         ACK_REC_W::new(self, 30)
     }
     #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"]
     #[inline(always)]
-    #[must_use]
     pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W<SIE_STATUS_SPEC> {
         DATA_SEQ_ERROR_W::new(self, 31)
     }
diff --git a/src/inner/usb/sof_wr.rs b/src/inner/usb/sof_wr.rs
index 5354b9f..0dadaa0 100644
--- a/src/inner/usb/sof_wr.rs
+++ b/src/inner/usb/sof_wr.rs
@@ -7,7 +7,6 @@ pub type COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
 impl W {
     #[doc = "Bits 0:10"]
     #[inline(always)]
-    #[must_use]
     pub fn count(&mut self) -> COUNT_W<SOF_WR_SPEC> {
         COUNT_W::new(self, 0)
     }
diff --git a/src/inner/usb/usb_muxing.rs b/src/inner/usb/usb_muxing.rs
index 6a0405f..f084416 100644
--- a/src/inner/usb/usb_muxing.rs
+++ b/src/inner/usb/usb_muxing.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn to_phy(&mut self) -> TO_PHY_W<USB_MUXING_SPEC> {
         TO_PHY_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn to_extphy(&mut self) -> TO_EXTPHY_W<USB_MUXING_SPEC> {
         TO_EXTPHY_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn to_digital_pad(&mut self) -> TO_DIGITAL_PAD_W<USB_MUXING_SPEC> {
         TO_DIGITAL_PAD_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn softcon(&mut self) -> SOFTCON_W<USB_MUXING_SPEC> {
         SOFTCON_W::new(self, 3)
     }
     #[doc = "Bit 4 - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."]
     #[inline(always)]
-    #[must_use]
     pub fn usbphy_as_gpio(&mut self) -> USBPHY_AS_GPIO_W<USB_MUXING_SPEC> {
         USBPHY_AS_GPIO_W::new(self, 4)
     }
     #[doc = "Bit 31 - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."]
     #[inline(always)]
-    #[must_use]
     pub fn swap_dpdm(&mut self) -> SWAP_DPDM_W<USB_MUXING_SPEC> {
         SWAP_DPDM_W::new(self, 31)
     }
diff --git a/src/inner/usb/usb_pwr.rs b/src/inner/usb/usb_pwr.rs
index f57d719..57534d0 100644
--- a/src/inner/usb/usb_pwr.rs
+++ b/src/inner/usb/usb_pwr.rs
@@ -61,37 +61,31 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_en(&mut self) -> VBUS_EN_W<USB_PWR_SPEC> {
         VBUS_EN_W::new(self, 0)
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_en_override_en(&mut self) -> VBUS_EN_OVERRIDE_EN_W<USB_PWR_SPEC> {
         VBUS_EN_OVERRIDE_EN_W::new(self, 1)
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_detect(&mut self) -> VBUS_DETECT_W<USB_PWR_SPEC> {
         VBUS_DETECT_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn vbus_detect_override_en(&mut self) -> VBUS_DETECT_OVERRIDE_EN_W<USB_PWR_SPEC> {
         VBUS_DETECT_OVERRIDE_EN_W::new(self, 3)
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn overcurr_detect(&mut self) -> OVERCURR_DETECT_W<USB_PWR_SPEC> {
         OVERCURR_DETECT_W::new(self, 4)
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn overcurr_detect_en(&mut self) -> OVERCURR_DETECT_EN_W<USB_PWR_SPEC> {
         OVERCURR_DETECT_EN_W::new(self, 5)
     }
diff --git a/src/inner/usb/usbphy_direct.rs b/src/inner/usb/usbphy_direct.rs
index dcb34e8..64709cd 100644
--- a/src/inner/usb/usbphy_direct.rs
+++ b/src/inner/usb/usbphy_direct.rs
@@ -209,103 +209,86 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup_hisel(&mut self) -> DP_PULLUP_HISEL_W<USBPHY_DIRECT_SPEC> {
         DP_PULLUP_HISEL_W::new(self, 0)
     }
     #[doc = "Bit 1 - DP pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup_en(&mut self) -> DP_PULLUP_EN_W<USBPHY_DIRECT_SPEC> {
         DP_PULLUP_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - DP pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pulldn_en(&mut self) -> DP_PULLDN_EN_W<USBPHY_DIRECT_SPEC> {
         DP_PULLDN_EN_W::new(self, 2)
     }
     #[doc = "Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup_hisel(&mut self) -> DM_PULLUP_HISEL_W<USBPHY_DIRECT_SPEC> {
         DM_PULLUP_HISEL_W::new(self, 4)
     }
     #[doc = "Bit 5 - DM pull up enable"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup_en(&mut self) -> DM_PULLUP_EN_W<USBPHY_DIRECT_SPEC> {
         DM_PULLUP_EN_W::new(self, 5)
     }
     #[doc = "Bit 6 - DM pull down enable"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pulldn_en(&mut self) -> DM_PULLDN_EN_W<USBPHY_DIRECT_SPEC> {
         DM_PULLDN_EN_W::new(self, 6)
     }
     #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W<USBPHY_DIRECT_SPEC> {
         TX_DP_OE_W::new(self, 8)
     }
     #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W<USBPHY_DIRECT_SPEC> {
         TX_DM_OE_W::new(self, 9)
     }
     #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dp(&mut self) -> TX_DP_W<USBPHY_DIRECT_SPEC> {
         TX_DP_W::new(self, 10)
     }
     #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dm(&mut self) -> TX_DM_W<USBPHY_DIRECT_SPEC> {
         TX_DM_W::new(self, 11)
     }
     #[doc = "Bit 12 - RX power down override (if override enable is set). 1 = powered down."]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pd(&mut self) -> RX_PD_W<USBPHY_DIRECT_SPEC> {
         RX_PD_W::new(self, 12)
     }
     #[doc = "Bit 13 - TX power down override (if override enable is set). 1 = powered down."]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pd(&mut self) -> TX_PD_W<USBPHY_DIRECT_SPEC> {
         TX_PD_W::new(self, 13)
     }
     #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W<USBPHY_DIRECT_SPEC> {
         TX_FSSLEW_W::new(self, 14)
     }
     #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W<USBPHY_DIRECT_SPEC> {
         TX_DIFFMODE_W::new(self, 15)
     }
     #[doc = "Bit 23 - Override rx_dd value into controller"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dd_override(&mut self) -> RX_DD_OVERRIDE_W<USBPHY_DIRECT_SPEC> {
         RX_DD_OVERRIDE_W::new(self, 23)
     }
     #[doc = "Bit 24 - Override rx_dp value into controller"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dp_override(&mut self) -> RX_DP_OVERRIDE_W<USBPHY_DIRECT_SPEC> {
         RX_DP_OVERRIDE_W::new(self, 24)
     }
     #[doc = "Bit 25 - Override rx_dm value into controller"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dm_override(&mut self) -> RX_DM_OVERRIDE_W<USBPHY_DIRECT_SPEC> {
         RX_DM_OVERRIDE_W::new(self, 25)
     }
diff --git a/src/inner/usb/usbphy_direct_override.rs b/src/inner/usb/usbphy_direct_override.rs
index 7ad29b0..3ba7bae 100644
--- a/src/inner/usb/usbphy_direct_override.rs
+++ b/src/inner/usb/usbphy_direct_override.rs
@@ -160,7 +160,6 @@ impl R {
 impl W {
     #[doc = "Bit 0"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup_hisel_override_en(
         &mut self,
     ) -> DP_PULLUP_HISEL_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -168,7 +167,6 @@ impl W {
     }
     #[doc = "Bit 1"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup_hisel_override_en(
         &mut self,
     ) -> DM_PULLUP_HISEL_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -176,7 +174,6 @@ impl W {
     }
     #[doc = "Bit 2"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pullup_en_override_en(
         &mut self,
     ) -> DP_PULLUP_EN_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -184,7 +181,6 @@ impl W {
     }
     #[doc = "Bit 3"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pulldn_en_override_en(
         &mut self,
     ) -> DP_PULLDN_EN_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -192,7 +188,6 @@ impl W {
     }
     #[doc = "Bit 4"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pulldn_en_override_en(
         &mut self,
     ) -> DM_PULLDN_EN_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -200,43 +195,36 @@ impl W {
     }
     #[doc = "Bit 5"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dp_oe_override_en(&mut self) -> TX_DP_OE_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         TX_DP_OE_OVERRIDE_EN_W::new(self, 5)
     }
     #[doc = "Bit 6"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dm_oe_override_en(&mut self) -> TX_DM_OE_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         TX_DM_OE_OVERRIDE_EN_W::new(self, 6)
     }
     #[doc = "Bit 7"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dp_override_en(&mut self) -> TX_DP_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         TX_DP_OVERRIDE_EN_W::new(self, 7)
     }
     #[doc = "Bit 8"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_dm_override_en(&mut self) -> TX_DM_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         TX_DM_OVERRIDE_EN_W::new(self, 8)
     }
     #[doc = "Bit 9"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_pd_override_en(&mut self) -> RX_PD_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         RX_PD_OVERRIDE_EN_W::new(self, 9)
     }
     #[doc = "Bit 10"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_pd_override_en(&mut self) -> TX_PD_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         TX_PD_OVERRIDE_EN_W::new(self, 10)
     }
     #[doc = "Bit 11"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_fsslew_override_en(
         &mut self,
     ) -> TX_FSSLEW_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -244,7 +232,6 @@ impl W {
     }
     #[doc = "Bit 12"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pullup_override_en(
         &mut self,
     ) -> DM_PULLUP_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -252,7 +239,6 @@ impl W {
     }
     #[doc = "Bit 15"]
     #[inline(always)]
-    #[must_use]
     pub fn tx_diffmode_override_en(
         &mut self,
     ) -> TX_DIFFMODE_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
@@ -260,19 +246,16 @@ impl W {
     }
     #[doc = "Bit 16"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dd_override_en(&mut self) -> RX_DD_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         RX_DD_OVERRIDE_EN_W::new(self, 16)
     }
     #[doc = "Bit 17"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dp_override_en(&mut self) -> RX_DP_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         RX_DP_OVERRIDE_EN_W::new(self, 17)
     }
     #[doc = "Bit 18"]
     #[inline(always)]
-    #[must_use]
     pub fn rx_dm_override_en(&mut self) -> RX_DM_OVERRIDE_EN_W<USBPHY_DIRECT_OVERRIDE_SPEC> {
         RX_DM_OVERRIDE_EN_W::new(self, 18)
     }
diff --git a/src/inner/usb/usbphy_trim.rs b/src/inner/usb/usbphy_trim.rs
index 56114cf..027364f 100644
--- a/src/inner/usb/usbphy_trim.rs
+++ b/src/inner/usb/usbphy_trim.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"]
     #[inline(always)]
-    #[must_use]
     pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W<USBPHY_TRIM_SPEC> {
         DP_PULLDN_TRIM_W::new(self, 0)
     }
     #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"]
     #[inline(always)]
-    #[must_use]
     pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W<USBPHY_TRIM_SPEC> {
         DM_PULLDN_TRIM_W::new(self, 8)
     }
diff --git a/src/inner/usb_dpram/ep_buffer_control.rs b/src/inner/usb_dpram/ep_buffer_control.rs
index 6fcafa0..80f9563 100644
--- a/src/inner/usb_dpram/ep_buffer_control.rs
+++ b/src/inner/usb_dpram/ep_buffer_control.rs
@@ -209,61 +209,51 @@ impl R {
 impl W {
     #[doc = "Bits 0:9 - The length of the data in buffer 1."]
     #[inline(always)]
-    #[must_use]
     pub fn length_0(&mut self) -> LENGTH_0_W<EP_BUFFER_CONTROL_SPEC> {
         LENGTH_0_W::new(self, 0)
     }
     #[doc = "Bit 10 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."]
     #[inline(always)]
-    #[must_use]
     pub fn available_0(&mut self) -> AVAILABLE_0_W<EP_BUFFER_CONTROL_SPEC> {
         AVAILABLE_0_W::new(self, 10)
     }
     #[doc = "Bit 11 - Reply with a stall (valid for both buffers)."]
     #[inline(always)]
-    #[must_use]
     pub fn stall(&mut self) -> STALL_W<EP_BUFFER_CONTROL_SPEC> {
         STALL_W::new(self, 11)
     }
     #[doc = "Bit 12 - Reset the buffer selector to buffer 0."]
     #[inline(always)]
-    #[must_use]
     pub fn reset(&mut self) -> RESET_W<EP_BUFFER_CONTROL_SPEC> {
         RESET_W::new(self, 12)
     }
     #[doc = "Bit 13 - The data pid of buffer 0."]
     #[inline(always)]
-    #[must_use]
     pub fn pid_0(&mut self) -> PID_0_W<EP_BUFFER_CONTROL_SPEC> {
         PID_0_W::new(self, 13)
     }
     #[doc = "Bit 14 - Buffer 0 is the last buffer of the transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn last_0(&mut self) -> LAST_0_W<EP_BUFFER_CONTROL_SPEC> {
         LAST_0_W::new(self, 14)
     }
     #[doc = "Bit 15 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."]
     #[inline(always)]
-    #[must_use]
     pub fn full_0(&mut self) -> FULL_0_W<EP_BUFFER_CONTROL_SPEC> {
         FULL_0_W::new(self, 15)
     }
     #[doc = "Bits 16:25 - The length of the data in buffer 1."]
     #[inline(always)]
-    #[must_use]
     pub fn length_1(&mut self) -> LENGTH_1_W<EP_BUFFER_CONTROL_SPEC> {
         LENGTH_1_W::new(self, 16)
     }
     #[doc = "Bit 26 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."]
     #[inline(always)]
-    #[must_use]
     pub fn available_1(&mut self) -> AVAILABLE_1_W<EP_BUFFER_CONTROL_SPEC> {
         AVAILABLE_1_W::new(self, 26)
     }
     #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."]
     #[inline(always)]
-    #[must_use]
     pub fn double_buffer_iso_offset(
         &mut self,
     ) -> DOUBLE_BUFFER_ISO_OFFSET_W<EP_BUFFER_CONTROL_SPEC> {
@@ -271,19 +261,16 @@ impl W {
     }
     #[doc = "Bit 29 - The data pid of buffer 1."]
     #[inline(always)]
-    #[must_use]
     pub fn pid_1(&mut self) -> PID_1_W<EP_BUFFER_CONTROL_SPEC> {
         PID_1_W::new(self, 29)
     }
     #[doc = "Bit 30 - Buffer 1 is the last buffer of the transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn last_1(&mut self) -> LAST_1_W<EP_BUFFER_CONTROL_SPEC> {
         LAST_1_W::new(self, 30)
     }
     #[doc = "Bit 31 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."]
     #[inline(always)]
-    #[must_use]
     pub fn full_1(&mut self) -> FULL_1_W<EP_BUFFER_CONTROL_SPEC> {
         FULL_1_W::new(self, 31)
     }
diff --git a/src/inner/usb_dpram/ep_control.rs b/src/inner/usb_dpram/ep_control.rs
index bc6cbb1..8736136 100644
--- a/src/inner/usb_dpram/ep_control.rs
+++ b/src/inner/usb_dpram/ep_control.rs
@@ -163,49 +163,41 @@ impl R {
 impl W {
     #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."]
     #[inline(always)]
-    #[must_use]
     pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W<EP_CONTROL_SPEC> {
         BUFFER_ADDRESS_W::new(self, 0)
     }
     #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W<EP_CONTROL_SPEC> {
         INTERRUPT_ON_NAK_W::new(self, 16)
     }
     #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W<EP_CONTROL_SPEC> {
         INTERRUPT_ON_STALL_W::new(self, 17)
     }
     #[doc = "Bits 26:27"]
     #[inline(always)]
-    #[must_use]
     pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W<EP_CONTROL_SPEC> {
         ENDPOINT_TYPE_W::new(self, 26)
     }
     #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_per_double_buff(&mut self) -> INTERRUPT_PER_DOUBLE_BUFF_W<EP_CONTROL_SPEC> {
         INTERRUPT_PER_DOUBLE_BUFF_W::new(self, 28)
     }
     #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."]
     #[inline(always)]
-    #[must_use]
     pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W<EP_CONTROL_SPEC> {
         INTERRUPT_PER_BUFF_W::new(self, 29)
     }
     #[doc = "Bit 30 - This endpoint is double buffered."]
     #[inline(always)]
-    #[must_use]
     pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W<EP_CONTROL_SPEC> {
         DOUBLE_BUFFERED_W::new(self, 30)
     }
     #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<EP_CONTROL_SPEC> {
         ENABLE_W::new(self, 31)
     }
diff --git a/src/inner/usb_dpram/setup_packet_high.rs b/src/inner/usb_dpram/setup_packet_high.rs
index 8842075..d373739 100644
--- a/src/inner/usb_dpram/setup_packet_high.rs
+++ b/src/inner/usb_dpram/setup_packet_high.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn windex(&mut self) -> WINDEX_W<SETUP_PACKET_HIGH_SPEC> {
         WINDEX_W::new(self, 0)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wlength(&mut self) -> WLENGTH_W<SETUP_PACKET_HIGH_SPEC> {
         WLENGTH_W::new(self, 16)
     }
diff --git a/src/inner/usb_dpram/setup_packet_low.rs b/src/inner/usb_dpram/setup_packet_low.rs
index 96743d8..e7fc2c8 100644
--- a/src/inner/usb_dpram/setup_packet_low.rs
+++ b/src/inner/usb_dpram/setup_packet_low.rs
@@ -34,19 +34,16 @@ impl R {
 impl W {
     #[doc = "Bits 0:7"]
     #[inline(always)]
-    #[must_use]
     pub fn bmrequesttype(&mut self) -> BMREQUESTTYPE_W<SETUP_PACKET_LOW_SPEC> {
         BMREQUESTTYPE_W::new(self, 0)
     }
     #[doc = "Bits 8:15"]
     #[inline(always)]
-    #[must_use]
     pub fn brequest(&mut self) -> BREQUEST_W<SETUP_PACKET_LOW_SPEC> {
         BREQUEST_W::new(self, 8)
     }
     #[doc = "Bits 16:31"]
     #[inline(always)]
-    #[must_use]
     pub fn wvalue(&mut self) -> WVALUE_W<SETUP_PACKET_LOW_SPEC> {
         WVALUE_W::new(self, 16)
     }
diff --git a/src/inner/watchdog/ctrl.rs b/src/inner/watchdog/ctrl.rs
index 9ce8cb6..b03a08f 100644
--- a/src/inner/watchdog/ctrl.rs
+++ b/src/inner/watchdog/ctrl.rs
@@ -52,31 +52,26 @@ impl R {
 impl W {
     #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"]
     #[inline(always)]
-    #[must_use]
     pub fn pause_jtag(&mut self) -> PAUSE_JTAG_W<CTRL_SPEC> {
         PAUSE_JTAG_W::new(self, 24)
     }
     #[doc = "Bit 25 - Pause the watchdog timer when processor 0 is in debug mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pause_dbg0(&mut self) -> PAUSE_DBG0_W<CTRL_SPEC> {
         PAUSE_DBG0_W::new(self, 25)
     }
     #[doc = "Bit 26 - Pause the watchdog timer when processor 1 is in debug mode"]
     #[inline(always)]
-    #[must_use]
     pub fn pause_dbg1(&mut self) -> PAUSE_DBG1_W<CTRL_SPEC> {
         PAUSE_DBG1_W::new(self, 26)
     }
     #[doc = "Bit 30 - When not enabled the watchdog timer is paused"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CTRL_SPEC> {
         ENABLE_W::new(self, 30)
     }
     #[doc = "Bit 31 - Trigger a watchdog reset"]
     #[inline(always)]
-    #[must_use]
     pub fn trigger(&mut self) -> TRIGGER_W<CTRL_SPEC> {
         TRIGGER_W::new(self, 31)
     }
diff --git a/src/inner/watchdog/load.rs b/src/inner/watchdog/load.rs
index d14ff70..422464e 100644
--- a/src/inner/watchdog/load.rs
+++ b/src/inner/watchdog/load.rs
@@ -7,7 +7,6 @@ pub type LOAD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
 impl W {
     #[doc = "Bits 0:23"]
     #[inline(always)]
-    #[must_use]
     pub fn load(&mut self) -> LOAD_W<LOAD_SPEC> {
         LOAD_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch0.rs b/src/inner/watchdog/scratch0.rs
index f25b6da..4c1ca71 100644
--- a/src/inner/watchdog/scratch0.rs
+++ b/src/inner/watchdog/scratch0.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch0(&mut self) -> SCRATCH0_W<SCRATCH0_SPEC> {
         SCRATCH0_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch1.rs b/src/inner/watchdog/scratch1.rs
index c4732de..0e49436 100644
--- a/src/inner/watchdog/scratch1.rs
+++ b/src/inner/watchdog/scratch1.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch1(&mut self) -> SCRATCH1_W<SCRATCH1_SPEC> {
         SCRATCH1_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch2.rs b/src/inner/watchdog/scratch2.rs
index 3e4e8a9..7a4e696 100644
--- a/src/inner/watchdog/scratch2.rs
+++ b/src/inner/watchdog/scratch2.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch2(&mut self) -> SCRATCH2_W<SCRATCH2_SPEC> {
         SCRATCH2_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch3.rs b/src/inner/watchdog/scratch3.rs
index 3d04b5b..c11fe17 100644
--- a/src/inner/watchdog/scratch3.rs
+++ b/src/inner/watchdog/scratch3.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch3(&mut self) -> SCRATCH3_W<SCRATCH3_SPEC> {
         SCRATCH3_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch4.rs b/src/inner/watchdog/scratch4.rs
index b6be489..40eac7c 100644
--- a/src/inner/watchdog/scratch4.rs
+++ b/src/inner/watchdog/scratch4.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch4(&mut self) -> SCRATCH4_W<SCRATCH4_SPEC> {
         SCRATCH4_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch5.rs b/src/inner/watchdog/scratch5.rs
index 1c6786b..30847a0 100644
--- a/src/inner/watchdog/scratch5.rs
+++ b/src/inner/watchdog/scratch5.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch5(&mut self) -> SCRATCH5_W<SCRATCH5_SPEC> {
         SCRATCH5_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch6.rs b/src/inner/watchdog/scratch6.rs
index bfcdba7..46f0086 100644
--- a/src/inner/watchdog/scratch6.rs
+++ b/src/inner/watchdog/scratch6.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch6(&mut self) -> SCRATCH6_W<SCRATCH6_SPEC> {
         SCRATCH6_W::new(self, 0)
     }
diff --git a/src/inner/watchdog/scratch7.rs b/src/inner/watchdog/scratch7.rs
index 73c2575..8e76c98 100644
--- a/src/inner/watchdog/scratch7.rs
+++ b/src/inner/watchdog/scratch7.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31"]
     #[inline(always)]
-    #[must_use]
     pub fn scratch7(&mut self) -> SCRATCH7_W<SCRATCH7_SPEC> {
         SCRATCH7_W::new(self, 0)
     }
diff --git a/src/inner/xip_aux/qmi_direct_tx.rs b/src/inner/xip_aux/qmi_direct_tx.rs
index 6254ca4..f9e68f9 100644
--- a/src/inner/xip_aux/qmi_direct_tx.rs
+++ b/src/inner/xip_aux/qmi_direct_tx.rs
@@ -59,31 +59,26 @@ pub type NOPUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bits 0:15 - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."]
     #[inline(always)]
-    #[must_use]
     pub fn data(&mut self) -> DATA_W<QMI_DIRECT_TX_SPEC> {
         DATA_W::new(self, 0)
     }
     #[doc = "Bits 16:17 - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."]
     #[inline(always)]
-    #[must_use]
     pub fn iwidth(&mut self) -> IWIDTH_W<QMI_DIRECT_TX_SPEC> {
         IWIDTH_W::new(self, 16)
     }
     #[doc = "Bit 18 - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."]
     #[inline(always)]
-    #[must_use]
     pub fn dwidth(&mut self) -> DWIDTH_W<QMI_DIRECT_TX_SPEC> {
         DWIDTH_W::new(self, 18)
     }
     #[doc = "Bit 19 - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn oe(&mut self) -> OE_W<QMI_DIRECT_TX_SPEC> {
         OE_W::new(self, 19)
     }
     #[doc = "Bit 20 - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."]
     #[inline(always)]
-    #[must_use]
     pub fn nopush(&mut self) -> NOPUSH_W<QMI_DIRECT_TX_SPEC> {
         NOPUSH_W::new(self, 20)
     }
diff --git a/src/inner/xip_ctrl/ctr_acc.rs b/src/inner/xip_ctrl/ctr_acc.rs
index 6c0d8a7..633d943 100644
--- a/src/inner/xip_ctrl/ctr_acc.rs
+++ b/src/inner/xip_ctrl/ctr_acc.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn ctr_acc(&mut self) -> CTR_ACC_W<CTR_ACC_SPEC> {
         CTR_ACC_W::new(self, 0)
     }
diff --git a/src/inner/xip_ctrl/ctr_hit.rs b/src/inner/xip_ctrl/ctr_hit.rs
index bf5a807..5af9ea8 100644
--- a/src/inner/xip_ctrl/ctr_hit.rs
+++ b/src/inner/xip_ctrl/ctr_hit.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."]
     #[inline(always)]
-    #[must_use]
     pub fn ctr_hit(&mut self) -> CTR_HIT_W<CTR_HIT_SPEC> {
         CTR_HIT_W::new(self, 0)
     }
diff --git a/src/inner/xip_ctrl/ctrl.rs b/src/inner/xip_ctrl/ctrl.rs
index 9fe18c9..d418b7a 100644
--- a/src/inner/xip_ctrl/ctrl.rs
+++ b/src/inner/xip_ctrl/ctrl.rs
@@ -138,7 +138,6 @@ impl W {
 == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\]
 == 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."]
     #[inline(always)]
-    #[must_use]
     pub fn en_secure(&mut self) -> EN_SECURE_W<CTRL_SPEC> {
         EN_SECURE_W::new(self, 0)
     }
@@ -146,41 +145,35 @@ impl W {
 == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\]
 == 1) window will never query the cache, irrespective of this bit."]
     #[inline(always)]
-    #[must_use]
     pub fn en_nonsecure(&mut self) -> EN_NONSECURE_W<CTRL_SPEC> {
         EN_NONSECURE_W::new(self, 1)
     }
     #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."]
     #[inline(always)]
-    #[must_use]
     pub fn power_down(&mut self) -> POWER_DOWN_W<CTRL_SPEC> {
         POWER_DOWN_W::new(self, 3)
     }
     #[doc = "Bit 4 - When 1, Secure accesses to the uncached window (addr\\[27:26\\]
 == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."]
     #[inline(always)]
-    #[must_use]
     pub fn no_uncached_sec(&mut self) -> NO_UNCACHED_SEC_W<CTRL_SPEC> {
         NO_UNCACHED_SEC_W::new(self, 4)
     }
     #[doc = "Bit 5 - When 1, Non-secure accesses to the uncached window (addr\\[27:26\\]
 == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."]
     #[inline(always)]
-    #[must_use]
     pub fn no_uncached_nonsec(&mut self) -> NO_UNCACHED_NONSEC_W<CTRL_SPEC> {
         NO_UNCACHED_NONSEC_W::new(self, 5)
     }
     #[doc = "Bit 6 - When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\]
 == 3) will generate a bus error."]
     #[inline(always)]
-    #[must_use]
     pub fn no_untranslated_sec(&mut self) -> NO_UNTRANSLATED_SEC_W<CTRL_SPEC> {
         NO_UNTRANSLATED_SEC_W::new(self, 6)
     }
     #[doc = "Bit 7 - When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\]
 == 3) will generate a bus error."]
     #[inline(always)]
-    #[must_use]
     pub fn no_untranslated_nonsec(&mut self) -> NO_UNTRANSLATED_NONSEC_W<CTRL_SPEC> {
         NO_UNTRANSLATED_NONSEC_W::new(self, 7)
     }
@@ -188,25 +181,21 @@ impl W {
 == 1, addr\\[26\\]
 == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."]
     #[inline(always)]
-    #[must_use]
     pub fn maint_nonsec(&mut self) -> MAINT_NONSEC_W<CTRL_SPEC> {
         MAINT_NONSEC_W::new(self, 8)
     }
     #[doc = "Bit 9 - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."]
     #[inline(always)]
-    #[must_use]
     pub fn split_ways(&mut self) -> SPLIT_WAYS_W<CTRL_SPEC> {
         SPLIT_WAYS_W::new(self, 9)
     }
     #[doc = "Bit 10 - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."]
     #[inline(always)]
-    #[must_use]
     pub fn writable_m0(&mut self) -> WRITABLE_M0_W<CTRL_SPEC> {
         WRITABLE_M0_W::new(self, 10)
     }
     #[doc = "Bit 11 - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."]
     #[inline(always)]
-    #[must_use]
     pub fn writable_m1(&mut self) -> WRITABLE_M1_W<CTRL_SPEC> {
         WRITABLE_M1_W::new(self, 11)
     }
diff --git a/src/inner/xip_ctrl/stream_addr.rs b/src/inner/xip_ctrl/stream_addr.rs
index 6ea292d..974bac7 100644
--- a/src/inner/xip_ctrl/stream_addr.rs
+++ b/src/inner/xip_ctrl/stream_addr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."]
     #[inline(always)]
-    #[must_use]
     pub fn stream_addr(&mut self) -> STREAM_ADDR_W<STREAM_ADDR_SPEC> {
         STREAM_ADDR_W::new(self, 2)
     }
diff --git a/src/inner/xip_ctrl/stream_ctr.rs b/src/inner/xip_ctrl/stream_ctr.rs
index bac9330..db1cd69 100644
--- a/src/inner/xip_ctrl/stream_ctr.rs
+++ b/src/inner/xip_ctrl/stream_ctr.rs
@@ -16,7 +16,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"]
     #[inline(always)]
-    #[must_use]
     pub fn stream_ctr(&mut self) -> STREAM_CTR_W<STREAM_CTR_SPEC> {
         STREAM_CTR_W::new(self, 0)
     }
diff --git a/src/inner/xosc.rs b/src/inner/xosc.rs
index 3ee5bfe..7f46c58 100644
--- a/src/inner/xosc.rs
+++ b/src/inner/xosc.rs
@@ -28,7 +28,7 @@ impl RegisterBlock {
     pub const fn startup(&self) -> &STARTUP {
         &self.startup
     }
-    #[doc = "0x10 - A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values &lt;4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."]
+    #[doc = "0x10 - A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."]
     #[inline(always)]
     pub const fn count(&self) -> &COUNT {
         &self.count
@@ -70,12 +70,12 @@ module"]
 pub type STARTUP = crate::Reg<startup::STARTUP_SPEC>;
 #[doc = "Controls the startup delay"]
 pub mod startup;
-#[doc = "COUNT (rw) register accessor: A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values &lt;4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that.  
+#[doc = "COUNT (rw) register accessor: A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that.  
 
 You can [`read`](crate::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
 
 For information about available fields see [`mod@count`]
 module"]
 pub type COUNT = crate::Reg<count::COUNT_SPEC>;
-#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values &lt;4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."]
+#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."]
 pub mod count;
diff --git a/src/inner/xosc/count.rs b/src/inner/xosc/count.rs
index fddfc24..e6eb3d7 100644
--- a/src/inner/xosc/count.rs
+++ b/src/inner/xosc/count.rs
@@ -16,12 +16,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:15"]
     #[inline(always)]
-    #[must_use]
     pub fn count(&mut self) -> COUNT_W<COUNT_SPEC> {
         COUNT_W::new(self, 0)
     }
 }
-#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values &lt;4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that.  
+#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that.  
 
 You can [`read`](crate::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct COUNT_SPEC;
diff --git a/src/inner/xosc/ctrl.rs b/src/inner/xosc/ctrl.rs
index 102b786..5d6d985 100644
--- a/src/inner/xosc/ctrl.rs
+++ b/src/inner/xosc/ctrl.rs
@@ -167,13 +167,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:11 - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"]
     #[inline(always)]
-    #[must_use]
     pub fn freq_range(&mut self) -> FREQ_RANGE_W<CTRL_SPEC> {
         FREQ_RANGE_W::new(self, 0)
     }
     #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> ENABLE_W<CTRL_SPEC> {
         ENABLE_W::new(self, 12)
     }
diff --git a/src/inner/xosc/dormant.rs b/src/inner/xosc/dormant.rs
index 29b8e7a..ad883d8 100644
--- a/src/inner/xosc/dormant.rs
+++ b/src/inner/xosc/dormant.rs
@@ -74,7 +74,6 @@ impl R {
 impl W {
     #[doc = "Bits 0:31 - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"]
     #[inline(always)]
-    #[must_use]
     pub fn dormant(&mut self) -> DORMANT_W<DORMANT_SPEC> {
         DORMANT_W::new(self, 0)
     }
diff --git a/src/inner/xosc/startup.rs b/src/inner/xosc/startup.rs
index 4e83943..57531e5 100644
--- a/src/inner/xosc/startup.rs
+++ b/src/inner/xosc/startup.rs
@@ -25,13 +25,11 @@ impl R {
 impl W {
     #[doc = "Bits 0:13 - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."]
     #[inline(always)]
-    #[must_use]
     pub fn delay(&mut self) -> DELAY_W<STARTUP_SPEC> {
         DELAY_W::new(self, 0)
     }
     #[doc = "Bit 20 - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."]
     #[inline(always)]
-    #[must_use]
     pub fn x4(&mut self) -> X4_W<STARTUP_SPEC> {
         X4_W::new(self, 20)
     }
diff --git a/src/inner/xosc/status.rs b/src/inner/xosc/status.rs
index c3469eb..e6beb6b 100644
--- a/src/inner/xosc/status.rs
+++ b/src/inner/xosc/status.rs
@@ -95,7 +95,6 @@ impl R {
 impl W {
     #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"]
     #[inline(always)]
-    #[must_use]
     pub fn badwrite(&mut self) -> BADWRITE_W<STATUS_SPEC> {
         BADWRITE_W::new(self, 24)
     }