ibex_core_tracing.core

CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ibex:ibex_core_tracing:0.1"
description: "Ibex CPU core with tracing enabled"
filesets:
  files_rtl:
    depend:
      - lowrisc:ibex:ibex_core
      - lowrisc:ibex:ibex_tracer
    files:
      - rtl/ibex_core_tracing.sv
    file_type: systemVerilogSource

  files_lint:
    depend:
      - lowrisc:ibex:sim_shared

  files_lint_verilator:
    files:
      - lint/verilator_waiver.vlt: {file_type: vlt}

parameters:
  # The tracer uses the RISC-V Formal Interface (RVFI) to collect trace signals.
  RVFI:
    datatype: bool
    paramtype: vlogdefine
    default: true

  SYNTHESIS:
    datatype: bool
    paramtype: vlogdefine

  RV32E:
    datatype: bool
    paramtype: vlogparam

  RV32M:
    datatype: bool
    paramtype: vlogparam

  MultiplierImplementation:
    datatype: str
    paramtype: vlogparam
    description: "Multiplier implementation. Valid values: fast, slow"
    default: fast

  BranchTargetALU:
    datatype: int
    paramtype: vlogparam
    default: 0
    description: "Enables seperate branch target ALU (increasing branch performance EXPERIMENTAL) [0/1]"



targets:
  default:
    filesets:
      - files_rtl
    parameters:
      - RVFI=true

  lint:
    filesets:
      # Note on Verilator waivers:
      # You *must* include the waiver file first, otherwise only global waivers
      # are applied, but not file-specific waivers.
      - tool_verilator ? (files_lint_verilator)
      - files_rtl
      - files_lint
    parameters:
      - RVFI=true
      - SYNTHESIS=true
    default_tool: verilator
    toplevel: ibex_core_tracing
    tools:
      verilator:
        mode: lint-only
        verilator_options:
          - "-Wall"