diff --git a/src/registers.rs b/src/registers.rs index 4c5bc8c..c4cf57f 100644 --- a/src/registers.rs +++ b/src/registers.rs @@ -28,12 +28,14 @@ mod cntp_ctl_el0; mod cntp_cval_el0; mod cntp_tval_el0; mod cntpct_el0; +mod cntpoff_el2; mod cntv_ctl_el0; mod cntv_cval_el0; mod cntv_tval_el0; mod cntvct_el0; mod cntvoff_el2; mod cpacr_el1; +mod cptr_el2; mod csselr_el1; mod currentel; mod dacr32_el2; @@ -52,10 +54,48 @@ mod far_el2; mod far_el3; mod fp; mod hcr_el2; +mod hpfar_el2; +mod icc_ctlr_el1; +mod icc_sre_el2; +mod ich_ap0r0_el2; +mod ich_ap0r1_el2; +mod ich_ap0r2_el2; +mod ich_ap0r3_el2; +mod ich_ap1r0_el2; +mod ich_ap1r1_el2; +mod ich_ap1r2_el2; +mod ich_ap1r3_el2; +mod ich_hcr_el2; +mod ich_lr0_el2; +mod ich_lr10_el2; +mod ich_lr11_el2; +mod ich_lr12_el2; +mod ich_lr13_el2; +mod ich_lr14_el2; +mod ich_lr15_el2; +mod ich_lr1_el2; +mod ich_lr2_el2; +mod ich_lr3_el2; +mod ich_lr4_el2; +mod ich_lr5_el2; +mod ich_lr6_el2; +mod ich_lr7_el2; +mod ich_lr8_el2; +mod ich_lr9_el2; +mod ich_misr_el2; +mod ich_vmcr_el2; +mod ich_vtr_el2; +mod id_aa64afr0_el1; +mod id_aa64afr1_el1; +mod id_aa64dfr0_el1; +mod id_aa64dfr1_el1; mod id_aa64isar0_el1; +mod id_aa64isar1_el1; mod id_aa64mmfr0_el1; mod id_aa64mmfr1_el1; mod id_aa64mmfr2_el1; +mod id_aa64pfr0_el1; +mod id_aa64pfr1_el1; mod lr; mod mair_el1; mod mair_el2; @@ -116,12 +156,14 @@ pub use cntp_ctl_el0::CNTP_CTL_EL0; pub use cntp_cval_el0::CNTP_CVAL_EL0; pub use cntp_tval_el0::CNTP_TVAL_EL0; pub use cntpct_el0::CNTPCT_EL0; +pub use cntpoff_el2::CNTPOFF_EL2; pub use cntv_ctl_el0::CNTV_CTL_EL0; pub use cntv_cval_el0::CNTV_CVAL_EL0; pub use cntv_tval_el0::CNTV_TVAL_EL0; pub use cntvct_el0::CNTVCT_EL0; pub use cntvoff_el2::CNTVOFF_EL2; pub use cpacr_el1::CPACR_EL1; +pub use cptr_el2::CPTR_EL2; pub use csselr_el1::CSSELR_EL1; pub use currentel::CurrentEL; pub use dacr32_el2::DACR32_EL2; @@ -140,10 +182,48 @@ pub use far_el2::FAR_EL2; pub use far_el3::FAR_EL3; pub use fp::FP; pub use hcr_el2::HCR_EL2; +pub use hpfar_el2::HPFAR_EL2; +pub use icc_ctlr_el1::ICC_CTLR_EL1; +pub use icc_sre_el2::ICC_SRE_EL2; +pub use ich_ap0r0_el2::ICH_AP0R0_EL2; +pub use ich_ap0r1_el2::ICH_AP0R1_EL2; +pub use ich_ap0r2_el2::ICH_AP0R2_EL2; +pub use ich_ap0r3_el2::ICH_AP0R3_EL2; +pub use ich_ap1r0_el2::ICH_AP1R0_EL2; +pub use ich_ap1r1_el2::ICH_AP1R1_EL2; +pub use ich_ap1r2_el2::ICH_AP1R2_EL2; +pub use ich_ap1r3_el2::ICH_AP1R3_EL2; +pub use ich_hcr_el2::ICH_HCR_EL2; +pub use ich_lr0_el2::ICH_LR0_EL2; +pub use ich_lr10_el2::ICH_LR10_EL2; +pub use ich_lr11_el2::ICH_LR11_EL2; +pub use ich_lr12_el2::ICH_LR12_EL2; +pub use ich_lr13_el2::ICH_LR13_EL2; +pub use ich_lr14_el2::ICH_LR14_EL2; +pub use ich_lr15_el2::ICH_LR15_EL2; +pub use ich_lr1_el2::ICH_LR1_EL2; +pub use ich_lr2_el2::ICH_LR2_EL2; +pub use ich_lr3_el2::ICH_LR3_EL2; +pub use ich_lr4_el2::ICH_LR4_EL2; +pub use ich_lr5_el2::ICH_LR5_EL2; +pub use ich_lr6_el2::ICH_LR6_EL2; +pub use ich_lr7_el2::ICH_LR7_EL2; +pub use ich_lr8_el2::ICH_LR8_EL2; +pub use ich_lr9_el2::ICH_LR9_EL2; +pub use ich_misr_el2::ICH_MISR_EL2; +pub use ich_vmcr_el2::ICH_VMCR_EL2; +pub use ich_vtr_el2::ICH_VTR_EL2; +pub use id_aa64afr0_el1::ID_AA64AFR0_EL1; +pub use id_aa64afr1_el1::ID_AA64AFR1_EL1; +pub use id_aa64dfr0_el1::ID_AA64DFR0_EL1; +pub use id_aa64dfr1_el1::ID_AA64DFR1_EL1; pub use id_aa64isar0_el1::ID_AA64ISAR0_EL1; +pub use id_aa64isar1_el1::ID_AA64ISAR1_EL1; pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1; pub use id_aa64mmfr1_el1::ID_AA64MMFR1_EL1; pub use id_aa64mmfr2_el1::ID_AA64MMFR2_EL1; +pub use id_aa64pfr0_el1::ID_AA64PFR0_EL1; +pub use id_aa64pfr1_el1::ID_AA64PFR1_EL1; pub use lr::LR; pub use mair_el1::MAIR_EL1; pub use mair_el2::MAIR_EL2; diff --git a/src/registers/cntkctl_el1.rs b/src/registers/cntkctl_el1.rs index 902b1a7..41b564b 100644 --- a/src/registers/cntkctl_el1.rs +++ b/src/registers/cntkctl_el1.rs @@ -9,8 +9,8 @@ //! Counter-timer Kernel Control register - EL1 //! //! When FEAT_VHE is implemented and HCR_EL2.{E2H, TGE} is {1, 1}, this register does not -//! cause any event stream from the virtual counter to be generated, and does not control access to the -//! counters and timers. The access to counters and timers at EL0 is controlled by CNTHCTL_EL2. +//! cause any event stream from the virtual counter to be generated, and does not control access to +//! the counters and timers. The access to counters and timers at EL0 is controlled by CNTHCTL_EL2. //! //! When FEAT_VHE is not implemented, or when HCR_EL2.{E2H, TGE} is not {1, 1}, this register //! controls the generation of an event stream from the virtual counter, and access from EL0 to the diff --git a/src/registers/cntpoff_el2.rs b/src/registers/cntpoff_el2.rs new file mode 100644 index 0000000..d885be9 --- /dev/null +++ b/src/registers/cntpoff_el2.rs @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Counter-timer Physical Offset register - EL2 +//! +//! Holds the 64-bit physical offset. +//! This is the offset for the AArch64 physical timers and counters +//! when Enhanced Counter Virtualization is enabled. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "CNTPOFF_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "CNTPOFF_EL2", "x"); +} + +pub const CNTPOFF_EL2: Reg = Reg {}; diff --git a/src/registers/cptr_el2.rs b/src/registers/cptr_el2.rs new file mode 100644 index 0000000..5d4e205 --- /dev/null +++ b/src/registers/cptr_el2.rs @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Architectural Feature Trap Register - EL2 +//! +//! Controls trapping to EL2 of accesses to CPACR, CPACR_EL1, trace, Activity Monitor, SME, +//! Streaming SVE, SVE, and Advanced SIMD and floating-point functionality. + +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +}; + +register_bitfields! {u64, + pub CPTR_EL2 [ + /// Trap Activity Monitor access. Traps EL1 and EL0 accesses to all Activity Monitor + /// registers to EL2. + /// + /// 0 Accesses from EL1 and EL0 to Activity Monitor registers are not trapped. + /// + /// 1 Accesses from EL1 and EL0 to Activity Monitor registers are trapped to EL2, + /// when EL2 is enabled in the current Security state. + TAM OFFSET(30) NUMBITS(1) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = CPTR_EL2::Register; + + sys_coproc_read_raw!(u64, "CPTR_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = CPTR_EL2::Register; + + sys_coproc_write_raw!(u64, "CPTR_EL2", "x"); +} + +pub const CPTR_EL2: Reg = Reg {}; diff --git a/src/registers/esr_el1.rs b/src/registers/esr_el1.rs index cd4e2a1..a68f51b 100644 --- a/src/registers/esr_el1.rs +++ b/src/registers/esr_el1.rs @@ -84,7 +84,7 @@ impl Readable for Reg { impl Writeable for Reg { type T = u64; - type R = (); + type R = ESR_EL1::Register; sys_coproc_write_raw!(u64, "ESR_EL1", "x"); } diff --git a/src/registers/hcr_el2.rs b/src/registers/hcr_el2.rs index 1f10bcd..61a14bf 100644 --- a/src/registers/hcr_el2.rs +++ b/src/registers/hcr_el2.rs @@ -66,6 +66,21 @@ register_bitfields! {u64, EnableTrapSyncExtAbortsToEl2 = 1, ], + /// Trap accesses of Error Record registers. Enables a trap to EL2 on accesses of + /// Error Record registers. + /// + /// 0 Accesses of the specified Error Record registers are not trapped by this mechanism. + /// 1 Accesses of the specified Error Record registers at EL1 are trapped to EL2, + /// unless the instruction generates a higher priority exception. + TERR OFFSET(36) NUMBITS(1) [], + + /// Trap LOR registers. Traps Non-secure EL1 accesses to LORSA_EL1, LOREA_EL1, LORN_EL1, + /// LORC_EL1, and LORID_EL1 registers to EL2. + /// + /// 0 This control does not cause any instructions to be trapped. + /// 1 Non-secure EL1 accesses to the LOR registers are trapped to EL2. + TLOR OFFSET(35) NUMBITS(1) [], + /// EL2 Host. Enables a configuration where a Host Operating System is running in EL2, and /// the Host Operating System's applications are running in EL0. E2H OFFSET(34) NUMBITS(1) [ @@ -128,6 +143,41 @@ register_bitfields! {u64, EnableTrapGeneralExceptionsToEl2 = 1, ], + /// Trap data or unified cache maintenance instructions that operate by Set/Way. + /// Traps execution of those cache maintenance instructions at EL1 to EL2, when + /// EL2 is enabled in the current Security state. + /// + /// 0 This control does not cause any instructions to be trapped. + /// 1 Execution of the specified instructions is trapped to EL2, when EL2 is enabled + /// in the current Security state. + TSW OFFSET(22) NUMBITS(1) [], + + /// Trap Auxiliary Control Registers. Traps EL1 accesses to the Auxiliary Control Registers + /// to EL2, when EL2 is enabled in the current Security state + /// + /// 0 This control does not cause any instructions to be trapped. + /// 1 EL1 accesses to the specified registers are trapped to EL2, when EL2 is enabled in the + /// current Security state. + TACR OFFSET(21) NUMBITS(1) [], + + /// Trap IMPLEMENTATION DEFINED functionality. Traps EL1 accesses to the encodings reserved + /// for IMPLEMENTATION DEFINED functionality to EL2, when EL2 is enabled in the current + /// Security state + /// + /// 0 This control does not cause any instructions to be trapped. + /// 1 EL1 accesses to or execution of the specified encodings reserved for IMPLEMENTATION + /// DEFINED functionality are trapped to EL2, when EL2 is enabled in the current Security + /// state. + TIDCP OFFSET(20) NUMBITS(1) [], + + /// Trap ID group 3. Traps EL1 reads of group 3 ID registers to EL2, when EL2 is enabled + /// in the current Security state. + /// + /// 0 This control does not cause any instructions to be trapped. + /// 1 The specified EL1 read accesses to ID group 3 registers are trapped to EL2, when EL2 + /// is enabled in the current Security state. + TID3 OFFSET(18) NUMBITS(1) [], + /// Trap SMC instructions. Traps EL1 execution of SMC instructions to EL2, when EL2 is /// enabled in the current Security state. /// @@ -196,6 +246,23 @@ register_bitfields! {u64, /// field behaves as 0 for all purposes other than a direct read of the value of this field. DC OFFSET(12) NUMBITS(1) [], + /// Barrier Shareability upgrade. This field determines the minimum shareability domain that + /// is applied to any barrier instruction executed from EL1 or EL0. + BSU OFFSET(10) NUMBITS(2) [ + NoEffect = 0b00, + InnerShareable = 0b01, + OuterShareable = 0b10, + FullSystem = 0b11 + ], + + /// Force broadcast. Causes the following instructions to be broadcast within the Inner + /// Shareable domain when executed from EL1. + /// + /// 0 This field has no effect on the operation of the specified instructions. + /// 1 When one of the specified instruction is executed at EL1, the instruction is broadcast + /// within the Inner Shareable shareability domain. + FB OFFSET(9) NUMBITS(1) [], + /// Physical SError interrupt routing. /// - If bit is 1 when executing at any Exception level, and EL2 is enabled in the current /// Security state: diff --git a/src/registers/hpfar_el2.rs b/src/registers/hpfar_el2.rs new file mode 100644 index 0000000..beb9903 --- /dev/null +++ b/src/registers/hpfar_el2.rs @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Hypervisor IPA Fault Address Register - EL2 +//! +//! Holds the faulting IPA for some aborts on a stage 2 translation taken to EL2. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub HPFAR_EL2 [ + /// Faulting IPA address space. + NS OFFSET(63) NUMBITS(1) [], + + /// Faulting Intermediate Physical Address. + FIPA OFFSET(4) NUMBITS(48) [] + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = HPFAR_EL2::Register; + + sys_coproc_read_raw!(u64, "HPFAR_EL2", "x"); +} + +pub const HPFAR_EL2: Reg = Reg {}; diff --git a/src/registers/icc_ctlr_el1.rs b/src/registers/icc_ctlr_el1.rs new file mode 100644 index 0000000..79bf22f --- /dev/null +++ b/src/registers/icc_ctlr_el1.rs @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Control Register - EL1 +//! +//! Controls aspects of the behavior of the GIC CPU interface and provides information +//! about the features implemented. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub ICC_CTLR_EL1 [ + /// Extended INTID range (read-only). + ExtRange OFFSET(19) NUMBITS(1) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ICC_CTLR_EL1::Register; + + sys_coproc_read_raw!(u64, "ICC_CTLR_EL1", "x"); +} + +pub const ICC_CTLR_EL1: Reg = Reg {}; diff --git a/src/registers/icc_sre_el2.rs b/src/registers/icc_sre_el2.rs new file mode 100644 index 0000000..2db4ed4 --- /dev/null +++ b/src/registers/icc_sre_el2.rs @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller System Register Enable Register - EL2 +//! +//! Controls whether the System register interface or the memory-mapped interface +//! to the GIC CPU interface is used for EL2. + +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +}; + +register_bitfields! {u64, + pub ICC_SRE_EL2 [ + /// Enables lower Exception level access to ICC_SRE_EL1. + /// + /// 0 When EL2 is implemented and enabled in the current Security state, + /// EL1 accesses to ICC_SRE_EL1 trap to EL2. + /// + /// 1 EL1 accesses to ICC_SRE_EL1 do not trap to EL2. + ENABLE OFFSET(3) NUMBITS(1) [], + + /// Disable IRQ bypass. + /// + /// 0 IRQ bypass enabled. + /// + /// 1 IRQ bypass disabled. + DIB OFFSET(2) NUMBITS(1) [], + + /// Disable FIQ bypass. + /// + /// 0 FIQ bypass enabled. + /// + /// 1 FIQ bypass disabled. + DFB OFFSET(1) NUMBITS(1) [], + + /// System Register Enable. + /// + /// 0 The memory-mapped interface must be used. Access at EL2 to any ICH_* or + /// ICC_* register other than ICC_SRE_EL1 or ICC_SRE_EL2, is trapped to EL2. + /// + /// 1 The System register interface to the ICH_* registers and the EL1 and EL2 + /// ICC_* registers is enabled for EL2. + SRE OFFSET(0) NUMBITS(1) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ICC_SRE_EL2::Register; + + sys_coproc_read_raw!(u64, "ICC_SRE_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = ICC_SRE_EL2::Register; + + sys_coproc_write_raw!(u64, "ICC_SRE_EL2", "x"); +} + +pub const ICC_SRE_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap0r0_el2.rs b/src/registers/ich_ap0r0_el2.rs new file mode 100644 index 0000000..ce8a97d --- /dev/null +++ b/src/registers/ich_ap0r0_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 0 Registers - EL2 +//! +//! Provides information about Group 0 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP0R0_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP0R0_EL2", "x"); +} + +pub const ICH_AP0R0_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap0r1_el2.rs b/src/registers/ich_ap0r1_el2.rs new file mode 100644 index 0000000..27443d5 --- /dev/null +++ b/src/registers/ich_ap0r1_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 0 Registers - EL2 +//! +//! Provides information about Group 0 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP0R1_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP0R1_EL2", "x"); +} + +pub const ICH_AP0R1_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap0r2_el2.rs b/src/registers/ich_ap0r2_el2.rs new file mode 100644 index 0000000..1a0172d --- /dev/null +++ b/src/registers/ich_ap0r2_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 0 Registers - EL2 +//! +//! Provides information about Group 0 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP0R2_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP0R2_EL2", "x"); +} + +pub const ICH_AP0R2_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap0r3_el2.rs b/src/registers/ich_ap0r3_el2.rs new file mode 100644 index 0000000..7f02e22 --- /dev/null +++ b/src/registers/ich_ap0r3_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 0 Registers - EL2 +//! +//! Provides information about Group 0 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP0R3_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP0R3_EL2", "x"); +} + +pub const ICH_AP0R3_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap1r0_el2.rs b/src/registers/ich_ap1r0_el2.rs new file mode 100644 index 0000000..e92025a --- /dev/null +++ b/src/registers/ich_ap1r0_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 1 Registers - EL2 +//! +//! Provides information about Group 1 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP1R0_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP1R0_EL2", "x"); +} + +pub const ICH_AP1R0_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap1r1_el2.rs b/src/registers/ich_ap1r1_el2.rs new file mode 100644 index 0000000..b562199 --- /dev/null +++ b/src/registers/ich_ap1r1_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 1 Registers - EL2 +//! +//! Provides information about Group 1 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP1R1_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP1R1_EL2", "x"); +} + +pub const ICH_AP1R1_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap1r2_el2.rs b/src/registers/ich_ap1r2_el2.rs new file mode 100644 index 0000000..21c97ef --- /dev/null +++ b/src/registers/ich_ap1r2_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 1 Registers - EL2 +//! +//! Provides information about Group 1 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP1R2_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP1R2_EL2", "x"); +} + +pub const ICH_AP1R2_EL2: Reg = Reg {}; diff --git a/src/registers/ich_ap1r3_el2.rs b/src/registers/ich_ap1r3_el2.rs new file mode 100644 index 0000000..87ab683 --- /dev/null +++ b/src/registers/ich_ap1r3_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Active Priorities Group 1 Registers - EL2 +//! +//! Provides information about Group 1 virtual active priorities for EL2. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_AP1R3_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_AP1R3_EL2", "x"); +} + +pub const ICH_AP1R3_EL2: Reg = Reg {}; diff --git a/src/registers/ich_hcr_el2.rs b/src/registers/ich_hcr_el2.rs new file mode 100644 index 0000000..451b686 --- /dev/null +++ b/src/registers/ich_hcr_el2.rs @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Hyp Control Register - EL2 +//! +//! Controls the environment for VMs. + +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +}; + +register_bitfields! {u64, + pub ICH_HCR_EL2 [ + /// This field is incremented whenever a successful write to a virtual EOIR or + /// DIR register would have resulted in a virtual interrupt deactivation. + EOIcount OFFSET(27) NUMBITS(5) [], + + /// When ICH_VTR_EL2.DVIM == 1: + /// Directly-injected Virtual Interrupt Mask. + DVIM OFFSET(15) NUMBITS(1) [], + + /// When FEAT_GICv3_TDIR is implemented: + /// Trap EL1 writes to ICC_DIR_EL1 and ICV_DIR_EL1. + TDIR OFFSET(14) NUMBITS(1) [], + + /// When FEAT_GICv4p1 is implemented: + /// Controls whether deactivation of virtual SGIs can increment ICH_HCR_EL2.EOIcount. + vSGIEOICount OFFSET(8) NUMBITS(1) [], + + /// VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt + /// while signaling of Group 1 interrupts from the virtual CPU interface to the connected + /// vPE is disabled. + VGrp1DIE OFFSET(7) NUMBITS(1) [], + + /// VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt + /// while signaling of Group 1 interrupts from the virtual CPU interface to the connected + /// vPE is enabled + VGrp1EIE OFFSET(6) NUMBITS(1) [], + + /// VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt + /// while signaling of Group 0 interrupts from the virtual CPU interface to the connected + /// vPE is disabled. + VGrp0DIE OFFSET(5) NUMBITS(1) [], + + /// VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt + /// while signaling of Group 0 interrupts from the virtual CPU interface to the connected + /// vPE is enabled + VGrp0EIE OFFSET(4) NUMBITS(1) [], + + /// No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt when + /// there are no List registers with the State field set to 0b01 (pending). + NPIE OFFSET(3) NUMBITS(1) [], + + /// List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance + /// interrupt while the virtual CPU interface does not have a corresponding valid List + /// register entry for an EOI request. + LRENPIE OFFSET(2) NUMBITS(1) [], + + /// Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the + /// List registers are empty, or hold only one valid entry. + UIE OFFSET(1) NUMBITS(1) [], + + /// Enable. Global enable bit for the virtual CPU interface. + En OFFSET(0) NUMBITS(1) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ICH_HCR_EL2::Register; + + sys_coproc_read_raw!(u64, "ICH_HCR_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = ICH_HCR_EL2::Register; + + sys_coproc_write_raw!(u64, "ICH_HCR_EL2", "x"); +} + +pub const ICH_HCR_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr0_el2.rs b/src/registers/ich_lr0_el2.rs new file mode 100644 index 0000000..b58756e --- /dev/null +++ b/src/registers/ich_lr0_el2.rs @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::{ + interfaces::{Readable, Writeable}, + register_bitfields, +}; + +register_bitfields! {u64, + pub ICH_LR0_EL2 [ + /// The state of the interrupt. + State OFFSET(62) NUMBITS(2) [ + Invalid = 0b00, + Pending = 0b01, + Active = 0b10, + PendingAndActive = 0b11, + ], + + /// Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning + /// that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also + /// causes the deactivation of the physical interrupt with the ID that the pINTID field + /// indicates. + HW OFFSET(61) NUMBITS(1) [], + + /// Indicates the group for this virtual interrupt. + Group OFFSET(60) NUMBITS(1) [], + + /// When FEAT_GICv3_NMI is implemented: + /// Indicates whether the virtual priority has the non-maskable property. + NMI OFFSET(59) NUMBITS(1) [], + + /// The priority of this interrupt. + Priority OFFSET(48) NUMBITS(8) [], + + /// Physical INTID, for hardware interrupts. + pINTID OFFSET(32) NUMBITS(13) [], + + /// If this bit is 1, then when the interrupt identified by vINTID is deactivated, + /// a maintenance interrupt is asserted. + EOI OFFSET(41) NUMBITS(1) [], + + /// Virtual INTID of the interrupt. + vINTID OFFSET(0) NUMBITS(32) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR0_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR0_EL2", "x"); +} + +pub const ICH_LR0_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr10_el2.rs b/src/registers/ich_lr10_el2.rs new file mode 100644 index 0000000..cc2875e --- /dev/null +++ b/src/registers/ich_lr10_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR10_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR10_EL2", "x"); +} + +pub const ICH_LR10_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr11_el2.rs b/src/registers/ich_lr11_el2.rs new file mode 100644 index 0000000..f19f3ba --- /dev/null +++ b/src/registers/ich_lr11_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR11_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR11_EL2", "x"); +} + +pub const ICH_LR11_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr12_el2.rs b/src/registers/ich_lr12_el2.rs new file mode 100644 index 0000000..e74010d --- /dev/null +++ b/src/registers/ich_lr12_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR12_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR12_EL2", "x"); +} + +pub const ICH_LR12_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr13_el2.rs b/src/registers/ich_lr13_el2.rs new file mode 100644 index 0000000..e62d27c --- /dev/null +++ b/src/registers/ich_lr13_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR13_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR13_EL2", "x"); +} + +pub const ICH_LR13_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr14_el2.rs b/src/registers/ich_lr14_el2.rs new file mode 100644 index 0000000..a363a2b --- /dev/null +++ b/src/registers/ich_lr14_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR14_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR14_EL2", "x"); +} + +pub const ICH_LR14_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr15_el2.rs b/src/registers/ich_lr15_el2.rs new file mode 100644 index 0000000..86c0e89 --- /dev/null +++ b/src/registers/ich_lr15_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR15_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR15_EL2", "x"); +} + +pub const ICH_LR15_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr1_el2.rs b/src/registers/ich_lr1_el2.rs new file mode 100644 index 0000000..fa7541c --- /dev/null +++ b/src/registers/ich_lr1_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR1_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR1_EL2", "x"); +} + +pub const ICH_LR1_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr2_el2.rs b/src/registers/ich_lr2_el2.rs new file mode 100644 index 0000000..b598b4c --- /dev/null +++ b/src/registers/ich_lr2_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR2_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR2_EL2", "x"); +} + +pub const ICH_LR2_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr3_el2.rs b/src/registers/ich_lr3_el2.rs new file mode 100644 index 0000000..a2a74db --- /dev/null +++ b/src/registers/ich_lr3_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR3_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR3_EL2", "x"); +} + +pub const ICH_LR3_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr4_el2.rs b/src/registers/ich_lr4_el2.rs new file mode 100644 index 0000000..7aa41e9 --- /dev/null +++ b/src/registers/ich_lr4_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR4_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR4_EL2", "x"); +} + +pub const ICH_LR4_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr5_el2.rs b/src/registers/ich_lr5_el2.rs new file mode 100644 index 0000000..f4af983 --- /dev/null +++ b/src/registers/ich_lr5_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR5_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR5_EL2", "x"); +} + +pub const ICH_LR5_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr6_el2.rs b/src/registers/ich_lr6_el2.rs new file mode 100644 index 0000000..293bbb5 --- /dev/null +++ b/src/registers/ich_lr6_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR6_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR6_EL2", "x"); +} + +pub const ICH_LR6_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr7_el2.rs b/src/registers/ich_lr7_el2.rs new file mode 100644 index 0000000..44221d2 --- /dev/null +++ b/src/registers/ich_lr7_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR7_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR7_EL2", "x"); +} + +pub const ICH_LR7_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr8_el2.rs b/src/registers/ich_lr8_el2.rs new file mode 100644 index 0000000..7560193 --- /dev/null +++ b/src/registers/ich_lr8_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR8_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR8_EL2", "x"); +} + +pub const ICH_LR8_EL2: Reg = Reg {}; diff --git a/src/registers/ich_lr9_el2.rs b/src/registers/ich_lr9_el2.rs new file mode 100644 index 0000000..cb1e779 --- /dev/null +++ b/src/registers/ich_lr9_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller List Registers - EL2 +//! +//! Provides interrupt context information for the virtual CPU interface. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_LR9_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_LR9_EL2", "x"); +} + +pub const ICH_LR9_EL2: Reg = Reg {}; diff --git a/src/registers/ich_misr_el2.rs b/src/registers/ich_misr_el2.rs new file mode 100644 index 0000000..99ba785 --- /dev/null +++ b/src/registers/ich_misr_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Maintenance Interrupt State Register - EL2 +//! +//! Indicates which maintenance interrupts are asserted. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_MISR_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_MISR_EL2", "x"); +} + +pub const ICH_MISR_EL2: Reg = Reg {}; diff --git a/src/registers/ich_vmcr_el2.rs b/src/registers/ich_vmcr_el2.rs new file mode 100644 index 0000000..a7c848e --- /dev/null +++ b/src/registers/ich_vmcr_el2.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller Virtual Machine Control Register - EL2 +//! +//! Enables the hypervisor to save and restore the virtual machine view of the GIC state. + +use tock_registers::interfaces::{Readable, Writeable}; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ICH_VMCR_EL2", "x"); +} + +impl Writeable for Reg { + type T = u64; + type R = (); + + sys_coproc_write_raw!(u64, "ICH_VMCR_EL2", "x"); +} + +pub const ICH_VMCR_EL2: Reg = Reg {}; diff --git a/src/registers/ich_vtr_el2.rs b/src/registers/ich_vtr_el2.rs new file mode 100644 index 0000000..1f3a3a7 --- /dev/null +++ b/src/registers/ich_vtr_el2.rs @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! Interrupt Controller VGIC Type Register - EL2 +//! +//! Reports supported GIC virtualization features. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub ICH_VTR_EL2 [ + /// Priority bits. Indicates the number of virtual priority bits implemented, minus one. + PRIbits OFFSET(29) NUMBITS(3) [], + + /// Preemption bits. Indicates the number of virtual preemption bits implemented, minus one. + PREbits OFFSET(26) NUMBITS(3) [], + + /// The number of virtual interrupt identifier bits supported. + IDbits OFFSET(23) NUMBITS(3) [], + + /// List Registers. Indicates the number of List registers implemented, minus one. + ListRegs OFFSET(0) NUMBITS(5) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ICH_VTR_EL2::Register; + + sys_coproc_read_raw!(u64, "ICH_VTR_EL2", "x"); +} + +pub const ICH_VTR_EL2: Reg = Reg {}; diff --git a/src/registers/id_aa64afr0_el1.rs b/src/registers/id_aa64afr0_el1.rs new file mode 100644 index 0000000..8332365 --- /dev/null +++ b/src/registers/id_aa64afr0_el1.rs @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Auxiliary Feature Register 0 - EL1 +//! +//! Provides information about the IMPLEMENTATION DEFINED features of the PE in AArch64 state. + +use tock_registers::interfaces::Readable; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ID_AA64AFR0_EL1", "x"); +} + +pub const ID_AA64AFR0_EL1: Reg = Reg {}; diff --git a/src/registers/id_aa64afr1_el1.rs b/src/registers/id_aa64afr1_el1.rs new file mode 100644 index 0000000..de04cb5 --- /dev/null +++ b/src/registers/id_aa64afr1_el1.rs @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Auxiliary Feature Register 1 - EL1 +//! +//! Reserved for future expansion of information about the IMPLEMENTATION DEFINED +//! features of the PE in AArch64 state. + +use tock_registers::interfaces::Readable; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ID_AA64AFR1_EL1", "x"); +} + +pub const ID_AA64AFR1_EL1: Reg = Reg {}; diff --git a/src/registers/id_aa64dfr0_el1.rs b/src/registers/id_aa64dfr0_el1.rs new file mode 100644 index 0000000..57bbe46 --- /dev/null +++ b/src/registers/id_aa64dfr0_el1.rs @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Debug Feature Register 0 - EL1 +//! +//! Provides top level information about the debug system in AArch64 state. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub ID_AA64DFR0_EL1 [ + /// Branch Record Buffer Extension. + /// + /// - 0000 Branch Record Buffer Extension not implemented. + /// - 0001 Branch Record Buffer Extension implemented. + /// - 0010 As 0b0001, and adds support for branch recording at EL3. + /// + /// All other values are reserved. + BRBE OFFSET(52) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + Implemented_El3Support = 0b0010, + ], + + /// Multi-threaded PMU extension. + /// + /// - 0000 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, it is IMPLEMENTATION + /// DEFINED whether PMEVTYPER_EL0.MT and PMEVTYPER.MT are read/write or RES0. + /// - 0001 FEAT_MTPMU and FEAT_PMUv3 implemented. PMEVTYPER_EL0.MT and PMEVTYPER.MT + /// are read/write. When FEAT_MTPMU is disabled, the Effective values of + /// PMEVTYPER_EL0.MT and PMEVTYPER.MT are 0. + /// - 1111 FEAT_MTPMU not implemented. If FEAT_PMUv3 is implemented, PMEVTYPER_EL0.MT + /// and PMEVTYPER.MT are RES0. + /// + /// All other values are reserved. + MTPMU OFFSET(48) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + NotImplemented_Res0 = 0b1111, + ], + + /// Trace Buffer Extension. + /// + /// - 0000 Trace Buffer Extension not implemented. + /// - 0001 Trace Buffer Extension implemented. + /// - 0010 As 0b0001, and adds: + /// - If EL2 and FEAT_FGT are implemented, a fine-grained trap on the TSB CSYNC instruction. + /// - If EL2 is implemented, an EL2 control to override TRBLIMITR_EL1.nVM. + /// - The TRBE Profiling exception extension, FEAT_TRBE_EXC. + /// + /// All other values are reserved. + TraceBuffer OFFSET(44) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + Implemented_Trbe = 0b0010, + ], + + /// Armv8.4 Self-hosted Trace Extension version. + TraceFilt OFFSET(40) NUMBITS(4) [ + NotImplemented = 0b0000, + Implemented = 0b0001, + ], + + /// Statistical Profiling Extension version. + PMSVer OFFSET(32) NUMBITS(4) [], + + /// Number of context-aware breakpoints, minus 1. + CTX_CMPs OFFSET(28) NUMBITS(4) [], + + /// Number of watchpoints, minus 1. + WRPs OFFSET(20) NUMBITS(4) [], + + /// Number of breakpoints, minus 1. + BRPs OFFSET(12) NUMBITS(4) [], + + /// Performance Monitors Extension version. + PMUVer OFFSET(8) NUMBITS(4) [], + + /// Trace support. Indicates whether System register interface to a trace unit is + /// implemented. + TraceVer OFFSET(4) NUMBITS(4) [], + + /// Debug architecture version. Indicates presence of Armv8 debug architecture. + DebugVer OFFSET(0) NUMBITS(4) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ID_AA64DFR0_EL1::Register; + + sys_coproc_read_raw!(u64, "ID_AA64DFR0_EL1", "x"); +} + +pub const ID_AA64DFR0_EL1: Reg = Reg {}; diff --git a/src/registers/id_aa64dfr1_el1.rs b/src/registers/id_aa64dfr1_el1.rs new file mode 100644 index 0000000..d8aa670 --- /dev/null +++ b/src/registers/id_aa64dfr1_el1.rs @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Debug Feature Register 1 - EL1 +//! +//! Provides top level information about the debug system in AArch64. + +use tock_registers::interfaces::Readable; + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = (); + + sys_coproc_read_raw!(u64, "ID_AA64DFR1_EL1", "x"); +} + +pub const ID_AA64DFR1_EL1: Reg = Reg {}; diff --git a/src/registers/id_aa64isar1_el1.rs b/src/registers/id_aa64isar1_el1.rs new file mode 100644 index 0000000..f3d0739 --- /dev/null +++ b/src/registers/id_aa64isar1_el1.rs @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Instruction Set Attribute Register 1 - EL1 +//! +//! Provides information about the features and instructions implemented in AArch64 state. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub ID_AA64ISAR1_EL1 [ + /// Indicates support for an IMPLEMENTATION DEFINED algorithm is implemented in the PE for + /// generic code authentication in AArch64 state. + GPI OFFSET(28) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001 + ], + + /// Indicates whether the QARMA5 algorithm is implemented in the PE for generic code + /// authentication in AArch64 state. + GPA OFFSET(24) NUMBITS(4) [ + NotSupported = 0b0000, + Supported = 0b0001 + ], + + /// Indicates whether an IMPLEMENTATION DEFINED algorithm is implemented in the PE for + /// address authentication, in AArch64 state. This applies to all Pointer Authentication + /// instructions other than the PACGA instruction. + API OFFSET(8) NUMBITS(4) [], + + /// Indicates whether the QARMA5 algorithm is implemented in the PE for address + /// authentication, in AArch64 state. This applies to all Pointer Authentication + /// instructions other than the PACGA instruction. + APA OFFSET(4) NUMBITS(4) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ID_AA64ISAR1_EL1::Register; + + sys_coproc_read_raw!(u64, "ID_AA64ISAR1_EL1", "x"); +} + +pub const ID_AA64ISAR1_EL1: Reg = Reg {}; diff --git a/src/registers/id_aa64pfr0_el1.rs b/src/registers/id_aa64pfr0_el1.rs new file mode 100644 index 0000000..e56726c --- /dev/null +++ b/src/registers/id_aa64pfr0_el1.rs @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Processor Feature Register 0 - EL1 +//! +//! Provides additional information about implemented PE features in AArch64 state. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub ID_AA64PFR0_EL1 [ + /// Indicates support for Activity Monitors Extension. + AMU OFFSET(44) NUMBITS(4) [], + + /// Scalable Vector Extension. + SVE OFFSET(32) NUMBITS(4) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ID_AA64PFR0_EL1::Register; + + sys_coproc_read_raw!(u64, "ID_AA64PFR0_EL1", "x"); +} + +pub const ID_AA64PFR0_EL1: Reg = Reg {}; diff --git a/src/registers/id_aa64pfr1_el1.rs b/src/registers/id_aa64pfr1_el1.rs new file mode 100644 index 0000000..e4fd1bc --- /dev/null +++ b/src/registers/id_aa64pfr1_el1.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 OR MIT +// +// Copyright (c) 2024 by the author(s) +// +// Author(s): +// - Sangwan Kwon + +//! AArch64 Processor Feature Register 1 - EL1 +//! +//! Provides additional information about implemented PE features in AArch64 state. + +use tock_registers::{interfaces::Readable, register_bitfields}; + +register_bitfields! {u64, + pub ID_AA64PFR1_EL1 [ + /// Support for the Memory Tagging Extension. + MTE OFFSET(8) NUMBITS(4) [], + ] +} + +pub struct Reg; + +impl Readable for Reg { + type T = u64; + type R = ID_AA64PFR1_EL1::Register; + + sys_coproc_read_raw!(u64, "ID_AA64PFR1_EL1", "x"); +} + +pub const ID_AA64PFR1_EL1: Reg = Reg {}; diff --git a/src/registers/mpidr_el1.rs b/src/registers/mpidr_el1.rs index e7d6583..ffa9746 100644 --- a/src/registers/mpidr_el1.rs +++ b/src/registers/mpidr_el1.rs @@ -17,6 +17,9 @@ register_bitfields! {u64, /// Affinity level 3. See the description of Aff0 for more information. Aff3 OFFSET(32) NUMBITS(8) [], + /// Reserved, RES1. + RES1 OFFSET(31) NUMBITS(1) [], + /// Indicates a Uniprocessor system, as distinct from PE 0 in a multiprocessor system. U OFFSET(30) NUMBITS(1) [ MultiprocessorSystem = 0b0, diff --git a/src/registers/sctlr_el2.rs b/src/registers/sctlr_el2.rs index ecca18b..64ab713 100644 --- a/src/registers/sctlr_el2.rs +++ b/src/registers/sctlr_el2.rs @@ -77,6 +77,12 @@ register_bitfields! {u64, Cacheable = 1 ], + /// When FEAT_ExS is implemented Exception exit is a context synchronization event. + EOS OFFSET(11) NUMBITS(1) [ + IsNotSynch = 0, + IsSynch = 1 + ], + /// SP Alignment check enable. /// /// When set to 1, if a load or store instruction executed at EL2 uses the SP diff --git a/src/registers/vtcr_el2.rs b/src/registers/vtcr_el2.rs index 3ebb554..3d5833b 100644 --- a/src/registers/vtcr_el2.rs +++ b/src/registers/vtcr_el2.rs @@ -16,6 +16,14 @@ use tock_registers::{ register_bitfields! {u64, pub VTCR_EL2 [ + /// Reserved, RES1. + RES1 OFFSET(31) NUMBITS(1) [], + /// When FEAT_SEL2 is implemented: + /// Non-secure stage 2 translation output address space for the Secure EL1&0 translation regime. + NSA OFFSET(30) NUMBITS(1) [ + SecurePASpace = 0, + NonSecurePASpace = 1, + ], /// Hardware dirty flag update in stage2 translations when EL2 is enabled HD OFFSET(22) NUMBITS(1) [ /// Stage2 hardware management of dirty state disabled @@ -98,7 +106,12 @@ register_bitfields! {u64, NormalWBRAnWA = 0b11, ], /// Starting level of the stage2 translation lookup - SL0 OFFSET(6) NUMBITS(2) [], + SL0 OFFSET(6) NUMBITS(2) [ + Granule4KBLevel2 = 0b00, + Granule4KBLevel1 = 0b01, + Granule4KBLevel0 = 0b10, + Granule4KBLevel3 = 0b11, + ], /// The size of the offest of the memory region addressed by the `VTTBR_EL2` T0SZ OFFSET(0) NUMBITS(6) [],