From 983d9aee1395d11ac52f1d419954788614d515c8 Mon Sep 17 00:00:00 2001
From: Henri Lunnikivi <henri.lunnikivi@tuni.fi>
Date: Fri, 23 Feb 2024 14:32:31 +0200
Subject: [PATCH] HACK(RVE): use a5 instead of t3 for RAM init

RVE does not support registers x16--x31, including t3 (x28). I replaced
the use of t3 in the flash algorithm with a5 (x15) to make it compile.
---
 riscv-rt/src/asm.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index 826e1ee5..8fed7798 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -164,9 +164,9 @@ cfg_global_asm!(
     bgeu t0, t2, 2f
 1:  ",
     #[cfg(target_arch = "riscv32")]
-    "lw t3, 0(t1)
+    "lw a5, 0(t1)
     addi t1, t1, 4
-    sw t3, 0(t0)
+    sw a5, 0(t0)
     addi t0, t0, 4
     bltu t0, t2, 1b",
     #[cfg(target_arch = "riscv64")]